treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_link_encoder.c
blobe4ac73035c84a4522e2781ee44ac176157d2b46b
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: AMD
26 #include "reg_helper.h"
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn20_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "i2caux_interface.h"
33 #include "dc_bios_types.h"
35 #include "gpio_service_interface.h"
37 #define CTX \
38 enc10->base.ctx
39 #define DC_LOGGER \
40 enc10->base.ctx->logger
42 #define REG(reg)\
43 (enc10->link_regs->reg)
45 #undef FN
46 #define FN(reg_name, field_name) \
47 enc10->link_shift->field_name, enc10->link_mask->field_name
49 #define IND_REG(index) \
50 (enc10->link_regs->index)
53 static struct mpll_cfg dcn2_mpll_cfg[] = {
54 // RBR
56 .hdmimode_enable = 1,
57 .ref_range = 3,
58 .ref_clk_mpllb_div = 2,
59 .mpllb_ssc_en = 1,
60 .mpllb_div5_clk_en = 1,
61 .mpllb_multiplier = 226,
62 .mpllb_fracn_en = 1,
63 .mpllb_fracn_quot = 39321,
64 .mpllb_fracn_rem = 3,
65 .mpllb_fracn_den = 5,
66 .mpllb_ssc_up_spread = 0,
67 .mpllb_ssc_peak = 38221,
68 .mpllb_ssc_stepsize = 49314,
69 .mpllb_div_clk_en = 0,
70 .mpllb_div_multiplier = 0,
71 .mpllb_hdmi_div = 0,
72 .mpllb_tx_clk_div = 2,
73 .tx_vboost_lvl = 4,
74 .mpllb_pmix_en = 1,
75 .mpllb_word_div2_en = 0,
76 .mpllb_ana_v2i = 2,
77 .mpllb_ana_freq_vco = 2,
78 .mpllb_ana_cp_int = 7,
79 .mpllb_ana_cp_prop = 18,
80 .hdmi_pixel_clk_div = 0,
82 // HBR
84 .hdmimode_enable = 1,
85 .ref_range = 3,
86 .ref_clk_mpllb_div = 2,
87 .mpllb_ssc_en = 1,
88 .mpllb_div5_clk_en = 1,
89 .mpllb_multiplier = 184,
90 .mpllb_fracn_en = 0,
91 .mpllb_fracn_quot = 0,
92 .mpllb_fracn_rem = 0,
93 .mpllb_fracn_den = 1,
94 .mpllb_ssc_up_spread = 0,
95 .mpllb_ssc_peak = 31850,
96 .mpllb_ssc_stepsize = 41095,
97 .mpllb_div_clk_en = 0,
98 .mpllb_div_multiplier = 0,
99 .mpllb_hdmi_div = 0,
100 .mpllb_tx_clk_div = 1,
101 .tx_vboost_lvl = 4,
102 .mpllb_pmix_en = 1,
103 .mpllb_word_div2_en = 0,
104 .mpllb_ana_v2i = 2,
105 .mpllb_ana_freq_vco = 3,
106 .mpllb_ana_cp_int = 7,
107 .mpllb_ana_cp_prop = 18,
108 .hdmi_pixel_clk_div = 0,
110 //HBR2
112 .hdmimode_enable = 1,
113 .ref_range = 3,
114 .ref_clk_mpllb_div = 2,
115 .mpllb_ssc_en = 1,
116 .mpllb_div5_clk_en = 1,
117 .mpllb_multiplier = 184,
118 .mpllb_fracn_en = 0,
119 .mpllb_fracn_quot = 0,
120 .mpllb_fracn_rem = 0,
121 .mpllb_fracn_den = 1,
122 .mpllb_ssc_up_spread = 0,
123 .mpllb_ssc_peak = 31850,
124 .mpllb_ssc_stepsize = 41095,
125 .mpllb_div_clk_en = 0,
126 .mpllb_div_multiplier = 0,
127 .mpllb_hdmi_div = 0,
128 .mpllb_tx_clk_div = 0,
129 .tx_vboost_lvl = 4,
130 .mpllb_pmix_en = 1,
131 .mpllb_word_div2_en = 0,
132 .mpllb_ana_v2i = 2,
133 .mpllb_ana_freq_vco = 3,
134 .mpllb_ana_cp_int = 7,
135 .mpllb_ana_cp_prop = 18,
136 .hdmi_pixel_clk_div = 0,
138 //HBR3
140 .hdmimode_enable = 1,
141 .ref_range = 3,
142 .ref_clk_mpllb_div = 2,
143 .mpllb_ssc_en = 1,
144 .mpllb_div5_clk_en = 1,
145 .mpllb_multiplier = 292,
146 .mpllb_fracn_en = 0,
147 .mpllb_fracn_quot = 0,
148 .mpllb_fracn_rem = 0,
149 .mpllb_fracn_den = 1,
150 .mpllb_ssc_up_spread = 0,
151 .mpllb_ssc_peak = 47776,
152 .mpllb_ssc_stepsize = 61642,
153 .mpllb_div_clk_en = 0,
154 .mpllb_div_multiplier = 0,
155 .mpllb_hdmi_div = 0,
156 .mpllb_tx_clk_div = 0,
157 .tx_vboost_lvl = 4,
158 .mpllb_pmix_en = 1,
159 .mpllb_word_div2_en = 0,
160 .mpllb_ana_v2i = 2,
161 .mpllb_ana_freq_vco = 0,
162 .mpllb_ana_cp_int = 7,
163 .mpllb_ana_cp_prop = 18,
164 .hdmi_pixel_clk_div = 0,
168 void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
170 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
171 DC_LOG_DSC("%s FEC at link encoder inst %d",
172 enable ? "Enabling" : "Disabling", enc->id.enum_id);
173 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
176 void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
178 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
180 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
183 bool enc2_fec_is_active(struct link_encoder *enc)
185 uint32_t active = 0;
186 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
188 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
190 return (active != 0);
193 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
194 * into a dcn_dsc_state struct.
196 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
198 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
200 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
201 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
202 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
203 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
206 static bool update_cfg_data(
207 struct dcn10_link_encoder *enc10,
208 const struct dc_link_settings *link_settings,
209 struct dpcssys_phy_seq_cfg *cfg)
211 int i;
213 cfg->load_sram_fw = false;
215 for (i = 0; i < link_settings->lane_count; i++)
216 cfg->lane_en[i] = true;
218 switch (link_settings->link_rate) {
219 case LINK_RATE_LOW:
220 cfg->mpll_cfg = dcn2_mpll_cfg[0];
221 break;
222 case LINK_RATE_HIGH:
223 cfg->mpll_cfg = dcn2_mpll_cfg[1];
224 break;
225 case LINK_RATE_HIGH2:
226 cfg->mpll_cfg = dcn2_mpll_cfg[2];
227 break;
228 case LINK_RATE_HIGH3:
229 cfg->mpll_cfg = dcn2_mpll_cfg[3];
230 break;
231 default:
232 DC_LOG_ERROR("%s: No supported link rate found %X!\n",
233 __func__, link_settings->link_rate);
234 return false;
237 return true;
240 void dcn20_link_encoder_enable_dp_output(
241 struct link_encoder *enc,
242 const struct dc_link_settings *link_settings,
243 enum clock_source_id clock_source)
245 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
246 struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10;
247 struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg;
249 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
250 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
251 return;
254 if (!update_cfg_data(enc10, link_settings, cfg))
255 return;
257 enc1_configure_encoder(enc10, link_settings);
259 dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
263 #define AUX_REG(reg)\
264 (enc10->aux_regs->reg)
266 #define AUX_REG_READ(reg_name) \
267 dm_read_reg(CTX, AUX_REG(reg_name))
269 #define AUX_REG_WRITE(reg_name, val) \
270 dm_write_reg(CTX, AUX_REG(reg_name), val)
271 void enc2_hw_init(struct link_encoder *enc)
273 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
276 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
277 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
278 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
279 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
280 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
281 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
282 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
283 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
287 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
288 AUX_RX_START_WINDOW = 1 [6:4]
289 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
290 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
291 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
292 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
293 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
294 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
295 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
296 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
298 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
300 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
302 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
303 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
304 // 27MHz -> 0xd
305 // 100MHz -> 0x32
306 // 48MHz -> 0x18
308 // Set TMDS_CTL0 to 1. This is a legacy setting.
309 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
311 dcn10_aux_initialize(enc10);
314 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
315 .read_state = link_enc2_read_state,
316 .validate_output_with_stream =
317 dcn10_link_encoder_validate_output_with_stream,
318 .hw_init = enc2_hw_init,
319 .setup = dcn10_link_encoder_setup,
320 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
321 .enable_dp_output = dcn20_link_encoder_enable_dp_output,
322 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
323 .disable_output = dcn10_link_encoder_disable_output,
324 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
325 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
326 .update_mst_stream_allocation_table =
327 dcn10_link_encoder_update_mst_stream_allocation_table,
328 .psr_program_dp_dphy_fast_training =
329 dcn10_psr_program_dp_dphy_fast_training,
330 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
331 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
332 .enable_hpd = dcn10_link_encoder_enable_hpd,
333 .disable_hpd = dcn10_link_encoder_disable_hpd,
334 .is_dig_enabled = dcn10_is_dig_enabled,
335 .destroy = dcn10_link_encoder_destroy,
336 .fec_set_enable = enc2_fec_set_enable,
337 .fec_set_ready = enc2_fec_set_ready,
338 .fec_is_active = enc2_fec_is_active,
339 .get_dig_mode = dcn10_get_dig_mode,
340 .get_dig_frontend = dcn10_get_dig_frontend,
343 void dcn20_link_encoder_construct(
344 struct dcn20_link_encoder *enc20,
345 const struct encoder_init_data *init_data,
346 const struct encoder_feature_support *enc_features,
347 const struct dcn10_link_enc_registers *link_regs,
348 const struct dcn10_link_enc_aux_registers *aux_regs,
349 const struct dcn10_link_enc_hpd_registers *hpd_regs,
350 const struct dcn10_link_enc_shift *link_shift,
351 const struct dcn10_link_enc_mask *link_mask)
353 struct bp_encoder_cap_info bp_cap_info = {0};
354 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
355 enum bp_result result = BP_RESULT_OK;
356 struct dcn10_link_encoder *enc10 = &enc20->enc10;
358 enc10->base.funcs = &dcn20_link_enc_funcs;
359 enc10->base.ctx = init_data->ctx;
360 enc10->base.id = init_data->encoder;
362 enc10->base.hpd_source = init_data->hpd_source;
363 enc10->base.connector = init_data->connector;
365 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
367 enc10->base.features = *enc_features;
369 enc10->base.transmitter = init_data->transmitter;
371 /* set the flag to indicate whether driver poll the I2C data pin
372 * while doing the DP sink detect
375 /* if (dal_adapter_service_is_feature_supported(as,
376 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
377 enc10->base.features.flags.bits.
378 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
380 enc10->base.output_signals =
381 SIGNAL_TYPE_DVI_SINGLE_LINK |
382 SIGNAL_TYPE_DVI_DUAL_LINK |
383 SIGNAL_TYPE_LVDS |
384 SIGNAL_TYPE_DISPLAY_PORT |
385 SIGNAL_TYPE_DISPLAY_PORT_MST |
386 SIGNAL_TYPE_EDP |
387 SIGNAL_TYPE_HDMI_TYPE_A;
389 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
390 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
391 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
392 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
393 * Prefer DIG assignment is decided by board design.
394 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
395 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
396 * By this, adding DIGG should not hurt DCE 8.0.
397 * This will let DCE 8.1 share DCE 8.0 as much as possible
400 enc10->link_regs = link_regs;
401 enc10->aux_regs = aux_regs;
402 enc10->hpd_regs = hpd_regs;
403 enc10->link_shift = link_shift;
404 enc10->link_mask = link_mask;
406 switch (enc10->base.transmitter) {
407 case TRANSMITTER_UNIPHY_A:
408 enc10->base.preferred_engine = ENGINE_ID_DIGA;
409 break;
410 case TRANSMITTER_UNIPHY_B:
411 enc10->base.preferred_engine = ENGINE_ID_DIGB;
412 break;
413 case TRANSMITTER_UNIPHY_C:
414 enc10->base.preferred_engine = ENGINE_ID_DIGC;
415 break;
416 case TRANSMITTER_UNIPHY_D:
417 enc10->base.preferred_engine = ENGINE_ID_DIGD;
418 break;
419 case TRANSMITTER_UNIPHY_E:
420 enc10->base.preferred_engine = ENGINE_ID_DIGE;
421 break;
422 case TRANSMITTER_UNIPHY_F:
423 enc10->base.preferred_engine = ENGINE_ID_DIGF;
424 break;
425 case TRANSMITTER_UNIPHY_G:
426 enc10->base.preferred_engine = ENGINE_ID_DIGG;
427 break;
428 default:
429 ASSERT_CRITICAL(false);
430 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
433 /* default to one to mirror Windows behavior */
434 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
436 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
437 enc10->base.id, &bp_cap_info);
439 /* Override features with DCE-specific values */
440 if (result == BP_RESULT_OK) {
441 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
442 bp_cap_info.DP_HBR2_EN;
443 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
444 bp_cap_info.DP_HBR3_EN;
445 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
446 enc10->base.features.flags.bits.DP_IS_USB_C =
447 bp_cap_info.DP_IS_USB_C;
448 } else {
449 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
450 __func__,
451 result);
453 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
454 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;