drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_LINK_ENCODER__DCN20_H__
  27 #define __DC_LINK_ENCODER__DCN20_H__
  28
  29 #include "dcn10/dcn10_link_encoder.h"
  30
  31 #define DCN2_AUX_REG_LIST(id)\
  32         AUX_REG_LIST(id), \
  33         SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
  34
  35 #define UNIPHY_MASK_SH_LIST(mask_sh)\
  36         LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
  37         LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
  38         LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
  39         LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
  40         LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
  41         LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
  42
  43 #define DPCS_MASK_SH_LIST(mask_sh)\
  44         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
  45         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
  46         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
  47         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
  48         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
  49         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
  50         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
  51         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
  52         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
  53         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
  54         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
  55         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
  56         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
  57         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
  58         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
  59         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
  60         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
  61         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
  62         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
  63         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
  64         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
  65         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
  66         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
  67         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
  68         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
  69         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
  70         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
  71         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
  72         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
  73         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
  74         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
  75         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
  76         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
  77         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
  78         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
  79         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
  80         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
  81         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
  82         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
  83         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
  84         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
  85         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
  86         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
  87         LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
  88         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
  89         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
  90         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
  91         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
  92         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
  93         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
  94         LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
  95         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
  96         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
  97         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
  98         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
  99         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
 100         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
 101         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
 102         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
 103         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
 104         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
 105         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
 106         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
 107         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
 108         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
 109         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
 110         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
 111         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
 112         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
 113         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
 114         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
 115         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
 116         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
 117         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
 118         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
 119         LE_SF(RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA, RDPCS_PLL_UPDATE_DATA, mask_sh),\
 120         LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
 121         LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
 122         LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
 123         LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
 124         LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
 125         LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
 126         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
 127         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
 128         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
 129         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
 130         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
 131         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
 132         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
 133         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
 134         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
 135         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
 136         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
 137         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
 138         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
 139         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
 140         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
 141         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
 142         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
 143         LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
 144         LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_CLOCK_ON, mask_sh),\
 145         LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_GATE_DIS, mask_sh),\
 146         LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_EN, mask_sh),\
 147         LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\
 148         LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\
 149         LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\
 150         LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
 151         LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)
 152
 153 #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\
 154         DPCS_MASK_SH_LIST(mask_sh),\
 155         LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_REF_LD_VAL, mask_sh),\
 156         LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_VCO_LD_VAL, mask_sh),\
 157         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
 158         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
 159         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
 160         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
 161         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
 162         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, mask_sh),\
 163         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
 164         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
 165         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
 166         LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
 167         LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
 168         LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
 169         LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
 170         LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
 171         LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh)
 172
 173 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\
 174         LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
 175         LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
 176         LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
 177         LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
 178         LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
 179         LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\
 180         LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\
 181         LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\
 182         LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
 183         LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
 184         UNIPHY_MASK_SH_LIST(mask_sh),\
 185         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
 186         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
 187         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
 188         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
 189         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
 190         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
 191         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
 192         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
 193         LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
 194         LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
 195         LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh)
 196
 197 #define UNIPHY_DCN2_REG_LIST(id) \
 198         SRI(CLOCK_ENABLE, SYMCLK, id), \
 199         SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
 200
 201 #define DPCS_DCN2_CMN_REG_LIST(id) \
 202         SRI(DIG_LANE_ENABLE, DIG, id), \
 203         SRI(TMDS_CTL_BITS, DIG, id), \
 204         SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
 205         SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
 206         SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
 207         SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
 208         SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
 209         SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
 210         SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
 211         SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
 212         SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
 213         SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
 214         SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
 215         SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
 216         SRI(RDPCSTX_CNTL, RDPCSTX, id), \
 217         SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
 218         SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
 219         SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
 220         SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
 221         SRI(RDPCSTX_PLL_UPDATE_DATA, RDPCSTX, id), \
 222         SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
 223         SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
 224         SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
 225         SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
 226         SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
 227         SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
 228         SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \
 229         SRI(DPCSTX_TX_CNTL, DPCSTX, id), \
 230         SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \
 231         SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \
 232         SR(RDPCSTX0_RDPCSTX_SCRATCH)
 233
 234
 235 #define DPCS_DCN2_REG_LIST(id) \
 236         DPCS_DCN2_CMN_REG_LIST(id), \
 237         SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
 238         SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
 239
 240 #define LE_DCN2_REG_LIST(id) \
 241                 LE_DCN10_REG_LIST(id), \
 242                 SR(DCIO_SOFT_RESET)
 243
 244 struct mpll_cfg {
 245         uint32_t mpllb_ana_v2i;
 246         uint32_t mpllb_ana_freq_vco;
 247         uint32_t mpllb_ana_cp_int;
 248         uint32_t mpllb_ana_cp_prop;
 249         uint32_t mpllb_multiplier;
 250         uint32_t ref_clk_mpllb_div;
 251         bool mpllb_word_div2_en;
 252         bool mpllb_ssc_en;
 253         bool mpllb_div5_clk_en;
 254         bool mpllb_div_clk_en;
 255         bool mpllb_fracn_en;
 256         bool mpllb_pmix_en;
 257         uint32_t mpllb_div_multiplier;
 258         uint32_t mpllb_tx_clk_div;
 259         uint32_t mpllb_fracn_quot;
 260         uint32_t mpllb_fracn_den;
 261         uint32_t mpllb_ssc_peak;
 262         uint32_t mpllb_ssc_stepsize;
 263         uint32_t mpllb_ssc_up_spread;
 264         uint32_t mpllb_fracn_rem;
 265         uint32_t mpllb_hdmi_div;
 266         // TODO: May not mpll params, need to figure out.
 267         uint32_t tx_vboost_lvl;
 268         uint32_t hdmi_pixel_clk_div;
 269         uint32_t ref_range;
 270         uint32_t ref_clk;
 271         bool hdmimode_enable;
 272         bool sup_pre_hp;
 273         bool dp_tx0_vergdrv_byp;
 274         bool dp_tx1_vergdrv_byp;
 275         bool dp_tx2_vergdrv_byp;
 276         bool dp_tx3_vergdrv_byp;
 277
 278
 279 };
 280
 281 struct dpcssys_phy_seq_cfg {
 282         bool program_fuse;
 283         bool bypass_sram;
 284         bool lane_en[4];
 285         bool use_calibration_setting;
 286         struct mpll_cfg mpll_cfg;
 287         bool load_sram_fw;
 288 #if 0
 289
 290         bool hdmimode_enable;
 291         bool silver2;
 292         bool ext_refclk_en;
 293         uint32_t dp_tx0_term_ctrl;
 294         uint32_t dp_tx1_term_ctrl;
 295         uint32_t dp_tx2_term_ctrl;
 296         uint32_t dp_tx3_term_ctrl;
 297         uint32_t fw_data[0x1000];
 298         uint32_t dp_tx0_width;
 299         uint32_t dp_tx1_width;
 300         uint32_t dp_tx2_width;
 301         uint32_t dp_tx3_width;
 302         uint32_t dp_tx0_rate;
 303         uint32_t dp_tx1_rate;
 304         uint32_t dp_tx2_rate;
 305         uint32_t dp_tx3_rate;
 306         uint32_t dp_tx0_eq_main;
 307         uint32_t dp_tx0_eq_pre;
 308         uint32_t dp_tx0_eq_post;
 309         uint32_t dp_tx1_eq_main;
 310         uint32_t dp_tx1_eq_pre;
 311         uint32_t dp_tx1_eq_post;
 312         uint32_t dp_tx2_eq_main;
 313         uint32_t dp_tx2_eq_pre;
 314         uint32_t dp_tx2_eq_post;
 315         uint32_t dp_tx3_eq_main;
 316         uint32_t dp_tx3_eq_pre;
 317         uint32_t dp_tx3_eq_post;
 318         bool data_swap_en;
 319         bool data_order_invert_en;
 320         uint32_t ldpcs_fifo_start_delay;
 321         uint32_t rdpcs_fifo_start_delay;
 322         bool rdpcs_reg_fifo_error_mask;
 323         bool rdpcs_tx_fifo_error_mask;
 324         bool rdpcs_dpalt_disable_mask;
 325         bool rdpcs_dpalt_4lane_mask;
 326 #endif
 327 };
 328
 329 struct dcn20_link_encoder {
 330         struct dcn10_link_encoder enc10;
 331         struct dpcssys_phy_seq_cfg phy_seq_cfg;
 332 };
 333
 334 void enc2_fec_set_enable(struct link_encoder *enc, bool enable);
 335 void enc2_fec_set_ready(struct link_encoder *enc, bool ready);
 336 bool enc2_fec_is_active(struct link_encoder *enc);
 337 void enc2_hw_init(struct link_encoder *enc);
 338
 339 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s);
 340
 341 void dcn20_link_encoder_enable_dp_output(
 342         struct link_encoder *enc,
 343         const struct dc_link_settings *link_settings,
 344         enum clock_source_id clock_source);
 345
 346 void dcn20_link_encoder_construct(
 347         struct dcn20_link_encoder *enc20,
 348         const struct encoder_init_data *init_data,
 349         const struct encoder_feature_support *enc_features,
 350         const struct dcn10_link_enc_registers *link_regs,
 351         const struct dcn10_link_enc_aux_registers *aux_regs,
 352         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 353         const struct dcn10_link_enc_shift *link_shift,
 354         const struct dcn10_link_enc_mask *link_mask);
 355
 356 #endif /* __DC_LINK_ENCODER__DCN20_H__ */