drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h

   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24
  25 #ifndef __DC_MPCC_DCN20_H__
  26 #define __DC_MPCC_DCN20_H__
  27
  28 #include "dcn10/dcn10_mpc.h"
  29
  30 #define TO_DCN20_MPC(mpc_base) \
  31         container_of(mpc_base, struct dcn20_mpc, base)
  32
  33 #define MPC_REG_LIST_DCN2_0(inst)\
  34         MPC_COMMON_REG_LIST_DCN1_0(inst),\
  35         SRII(MPCC_TOP_GAIN, MPCC, inst),\
  36         SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
  37         SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
  38         SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
  39         SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
  40         SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
  41         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
  42         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
  43         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
  44         SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
  45         SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
  46         SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
  47         SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
  48         SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
  49         SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
  50         SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
  51         SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
  52         SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
  53         SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
  54         SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
  55         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
  56         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
  57         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
  58         SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
  59         SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
  60         SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
  61         SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
  62         SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
  63         SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
  64         SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
  65         SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
  66         SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
  67         SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
  68         SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
  69         SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
  70         SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
  71
  72 #define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
  73         MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
  74         SRII(CSC_MODE, MPC_OUT, inst),\
  75         SRII(CSC_C11_C12_A, MPC_OUT, inst),\
  76         SRII(CSC_C33_C34_A, MPC_OUT, inst),\
  77         SRII(CSC_C11_C12_B, MPC_OUT, inst),\
  78         SRII(CSC_C33_C34_B, MPC_OUT, inst),\
  79         SRII(DENORM_CONTROL, MPC_OUT, inst),\
  80         SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
  81         SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
  82
  83 #define MPC_DBG_REG_LIST_DCN2_0() \
  84         SR(MPC_OCSC_TEST_DEBUG_DATA),\
  85         SR(MPC_OCSC_TEST_DEBUG_INDEX)
  86
  87 #define MPC_REG_VARIABLE_LIST_DCN2_0 \
  88         MPC_COMMON_REG_VARIABLE_LIST \
  89         uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
  90         uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
  91         uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
  92         uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
  93         uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
  94         uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
  95         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
  96         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
  97         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
  98         uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
  99         uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \
 100         uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \
 101         uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \
 102         uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \
 103         uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \
 104         uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
 105         uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \
 106         uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \
 107         uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \
 108         uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \
 109         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \
 110         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \
 111         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \
 112         uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \
 113         uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \
 114         uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \
 115         uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \
 116         uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \
 117         uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \
 118         uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
 119         uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\
 120         uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
 121         uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
 122         uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
 123         uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
 124         uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
 125         uint32_t MPC_OCSC_TEST_DEBUG_DATA;\
 126         uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\
 127         uint32_t CSC_MODE[MAX_OPP]; \
 128         uint32_t CSC_C11_C12_A[MAX_OPP]; \
 129         uint32_t CSC_C33_C34_A[MAX_OPP]; \
 130         uint32_t CSC_C11_C12_B[MAX_OPP]; \
 131         uint32_t CSC_C33_C34_B[MAX_OPP]; \
 132         uint32_t DENORM_CONTROL[MAX_OPP]; \
 133         uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
 134         uint32_t DENORM_CLAMP_B_CB[MAX_OPP];
 135
 136 #define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
 137         MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 138         SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
 139         SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
 140         SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
 141         SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
 142         SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
 143         SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
 144         SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
 145         SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
 146         SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
 147         SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
 148         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
 149         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
 150         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
 151         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
 152         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
 153         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
 154         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
 155         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
 156         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
 157         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
 158         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
 159         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
 160         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
 161         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
 162         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
 163         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
 164         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
 165         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
 166         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
 167         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
 168         SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
 169         SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
 170         SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
 171         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
 172         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
 173         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
 174         SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
 175         SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
 176         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
 177         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
 178         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
 179         SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
 180         SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
 181         SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
 182         SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
 183
 184 /*
 185  *      DCN2 MPC_OCSC debug status register:
 186  *
 187  *              Status index including current OCSC Mode is 1
 188  *                      OCSC Mode: [1..0]
 189  */
 190 #define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1
 191
 192 #define MPC_DEBUG_REG_LIST_SH_DCN20 \
 193         .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0
 194
 195 #define MPC_DEBUG_REG_LIST_MASK_DCN20 \
 196         .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3
 197
 198 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
 199         MPC_REG_FIELD_LIST(type)\
 200         type MPCC_BG_BPC;\
 201         type MPCC_BOT_GAIN_MODE;\
 202         type MPCC_TOP_GAIN;\
 203         type MPCC_BOT_GAIN_INSIDE;\
 204         type MPCC_BOT_GAIN_OUTSIDE;\
 205         type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\
 206         type MPC_OCSC_TEST_DEBUG_INDEX;\
 207         type MPC_OCSC_MODE;\
 208         type MPC_OCSC_C11_A;\
 209         type MPC_OCSC_C12_A;\
 210         type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
 211         type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
 212         type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
 213         type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
 214         type MPCC_OGAM_RAMA_EXP_REGION_END_B;\
 215         type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
 216         type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\
 217         type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\
 218         type MPCC_OGAM_RAMA_EXP_REGION_START_B;\
 219         type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
 220         type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
 221         type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
 222         type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
 223         type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
 224         type MPCC_OGAM_RAMB_EXP_REGION_END_B;\
 225         type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
 226         type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\
 227         type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\
 228         type MPCC_OGAM_RAMB_EXP_REGION_START_B;\
 229         type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
 230         type MPCC_OGAM_MEM_PWR_FORCE;\
 231         type MPCC_OGAM_LUT_INDEX;\
 232         type MPCC_OGAM_LUT_WRITE_EN_MASK;\
 233         type MPCC_OGAM_LUT_RAM_SEL;\
 234         type MPCC_OGAM_CONFIG_STATUS;\
 235         type MPCC_OGAM_LUT_DATA;\
 236         type MPCC_OGAM_MODE;\
 237         type MPC_OUT_DENORM_MODE;\
 238         type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\
 239         type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\
 240         type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\
 241         type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
 242         type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
 243         type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
 244         type MPCC_DISABLED;\
 245         type MPCC_OGAM_MEM_PWR_DIS;
 246
 247 struct dcn20_mpc_registers {
 248         MPC_REG_VARIABLE_LIST_DCN2_0
 249 };
 250
 251 struct dcn20_mpc_shift {
 252         MPC_REG_FIELD_LIST_DCN2_0(uint8_t)
 253 };
 254
 255 struct dcn20_mpc_mask {
 256         MPC_REG_FIELD_LIST_DCN2_0(uint32_t)
 257 };
 258
 259 struct dcn20_mpc {
 260         struct mpc base;
 261
 262         int mpcc_in_use_mask;
 263         int num_mpcc;
 264         const struct dcn20_mpc_registers *mpc_regs;
 265         const struct dcn20_mpc_shift *mpc_shift;
 266         const struct dcn20_mpc_mask *mpc_mask;
 267 };
 268
 269 void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
 270         struct dc_context *ctx,
 271         const struct dcn20_mpc_registers *mpc_regs,
 272         const struct dcn20_mpc_shift *mpc_shift,
 273         const struct dcn20_mpc_mask *mpc_mask,
 274         int num_mpcc);
 275
 276 void mpc2_update_blending(
 277         struct mpc *mpc,
 278         struct mpcc_blnd_cfg *blnd_cfg,
 279         int mpcc_id);
 280
 281 void mpc2_set_denorm(
 282         struct mpc *mpc,
 283         int opp_id,
 284         enum dc_color_depth output_depth);
 285
 286 void mpc2_set_denorm_clamp(
 287         struct mpc *mpc,
 288         int opp_id,
 289         struct mpc_denorm_clamp denorm_clamp);
 290
 291 void mpc2_set_output_csc(
 292         struct mpc *mpc,
 293         int opp_id,
 294         const uint16_t *regval,
 295         enum mpc_output_csc_mode ocsc_mode);
 296
 297 void mpc2_set_ocsc_default(
 298         struct mpc *mpc,
 299         int opp_id,
 300         enum dc_color_space color_space,
 301         enum mpc_output_csc_mode ocsc_mode);
 302
 303 void mpc2_set_output_gamma(
 304         struct mpc *mpc,
 305         int mpcc_id,
 306         const struct pwl_params *params);
 307
 308 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
 309 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
 310 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
 311 #endif