drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27 #include "dcn20_optc.h"
  28 #include "dc.h"
  29
  30 #define REG(reg)\
  31         optc1->tg_regs->reg
  32
  33 #define CTX \
  34         optc1->base.ctx
  35
  36 #undef FN
  37 #define FN(reg_name, field_name) \
  38         optc1->tg_shift->field_name, optc1->tg_mask->field_name
  39
  40 /**
  41  * Enable CRTC
  42  * Enable CRTC - call ASIC Control Object to enable Timing generator.
  43  */
  44 bool optc2_enable_crtc(struct timing_generator *optc)
  45 {
  46         /* TODO FPGA wait for answer
  47          * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
  48          * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
  49          */
  50         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  51
  52         /* opp instance for OTG. For DCN1.0, ODM is remoed.
  53          * OPP and OPTC should 1:1 mapping
  54          */
  55         REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
  56                         OPTC_SEG0_SRC_SEL, optc->inst);
  57
  58         /* VTG enable first is for HW workaround */
  59         REG_UPDATE(CONTROL,
  60                         VTG0_ENABLE, 1);
  61
  62         REG_SEQ_START();
  63
  64         /* Enable CRTC */
  65         REG_UPDATE_2(OTG_CONTROL,
  66                         OTG_DISABLE_POINT_CNTL, 3,
  67                         OTG_MASTER_EN, 1);
  68
  69         REG_SEQ_SUBMIT();
  70         REG_SEQ_WAIT_DONE();
  71
  72         return true;
  73 }
  74
  75 /**
  76  * DRR double buffering control to select buffer point
  77  * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
  78  * Options: anytime, start of frame, dp start of frame (range timing)
  79  */
  80 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
  81 {
  82         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  83
  84         uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
  85
  86         REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
  87                 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
  88 }
  89
  90 /**
  91  *For the below, I'm not sure how your GSL parameters are stored in your env,
  92  * so I will assume a gsl_params struct for now
  93  */
  94 void optc2_set_gsl(struct timing_generator *optc,
  95                    const struct gsl_params *params)
  96 {
  97         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  98
  99 /**
 100  * There are (MAX_OPTC+1)/2 gsl groups available for use.
 101  * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
 102  * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
 103  */
 104         REG_UPDATE_5(OTG_GSL_CONTROL,
 105                 OTG_GSL0_EN, params->gsl0_en,
 106                 OTG_GSL1_EN, params->gsl1_en,
 107                 OTG_GSL2_EN, params->gsl2_en,
 108                 OTG_GSL_MASTER_EN, params->gsl_master_en,
 109                 OTG_GSL_MASTER_MODE, params->gsl_master_mode);
 110 }
 111
 112
 113 /* Use the gsl allow flip as the master update lock */
 114 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
 115                    const struct gsl_params *params)
 116 {
 117         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 118
 119         REG_UPDATE(OTG_GSL_CONTROL,
 120                 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
 121 }
 122
 123 /* You can control the GSL timing by limiting GSL to a window (X,Y) */
 124 void optc2_set_gsl_window(struct timing_generator *optc,
 125                    const struct gsl_params *params)
 126 {
 127         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 128
 129         REG_SET_2(OTG_GSL_WINDOW_X, 0,
 130                 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
 131                 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
 132         REG_SET_2(OTG_GSL_WINDOW_Y, 0,
 133                 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
 134                 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
 135 }
 136
 137 /**
 138  * Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
 139  * Start offset begins with vstartup and goes for x number of clocks,
 140  * end offset starts from end of vupdate to x number of clocks.
 141  */
 142 void optc2_set_vupdate_keepout(struct timing_generator *optc,
 143                    const struct vupdate_keepout_params *params)
 144 {
 145         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 146
 147         REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
 148                 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
 149                 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
 150                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
 151 }
 152
 153 void optc2_set_gsl_source_select(
 154                 struct timing_generator *optc,
 155                 int group_idx,
 156                 uint32_t gsl_ready_signal)
 157 {
 158         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 159
 160         switch (group_idx) {
 161         case 1:
 162                 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
 163                 break;
 164         case 2:
 165                 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
 166                 break;
 167         case 3:
 168                 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
 169                 break;
 170         default:
 171                 break;
 172         }
 173 }
 174
 175 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
 176 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
 177                                         int x_position,
 178                                         int line_num)
 179 {
 180         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 181
 182         REG_SET_2(OTG_DSC_START_POSITION, 0,
 183                         OTG_DSC_START_POSITION_X, x_position,
 184                         OTG_DSC_START_POSITION_LINE_NUM, line_num);
 185 }
 186
 187 /* Set DSC-related configuration.
 188  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
 189  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
 190  *   dsc_slice_width: Slice width in pixels
 191  */
 192 void optc2_set_dsc_config(struct timing_generator *optc,
 193                                         enum optc_dsc_mode dsc_mode,
 194                                         uint32_t dsc_bytes_per_pixel,
 195                                         uint32_t dsc_slice_width)
 196 {
 197         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 198
 199         REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
 200                 OPTC_DSC_MODE, dsc_mode);
 201
 202         REG_SET(OPTC_BYTES_PER_PIXEL, 0,
 203                 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
 204
 205         REG_UPDATE(OPTC_WIDTH_CONTROL,
 206                 OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
 207 }
 208
 209 /*TEMP: Need to figure out inheritance model here.*/
 210 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
 211 {
 212         return optc1_is_two_pixels_per_containter(timing);
 213 }
 214
 215 void optc2_set_odm_bypass(struct timing_generator *optc,
 216                 const struct dc_crtc_timing *dc_crtc_timing)
 217 {
 218         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 219         uint32_t h_div_2 = 0;
 220
 221         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 222                         OPTC_NUM_OF_INPUT_SEGMENT, 0,
 223                         OPTC_SEG0_SRC_SEL, optc->inst,
 224                         OPTC_SEG1_SRC_SEL, 0xf);
 225         REG_WRITE(OTG_H_TIMING_CNTL, 0);
 226
 227         h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
 228         REG_UPDATE(OTG_H_TIMING_CNTL,
 229                         OTG_H_TIMING_DIV_BY2, h_div_2);
 230         REG_SET(OPTC_MEMORY_CONFIG, 0,
 231                         OPTC_MEM_SEL, 0);
 232         optc1->opp_count = 1;
 233 }
 234
 235 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 236                 struct dc_crtc_timing *timing)
 237 {
 238         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 239         int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
 240                         / opp_cnt;
 241         uint32_t memory_mask;
 242         uint32_t data_fmt = 0;
 243
 244         ASSERT(opp_cnt == 2);
 245
 246         /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
 247          * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
 248          * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
 249          * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
 250          *              MASTER_UPDATE_LOCK_DB_X, 160,
 251          *              MASTER_UPDATE_LOCK_DB_Y, 240);
 252          */
 253
 254         /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
 255          * however, for ODM combine we can simplify by always using 4.
 256          * To make sure there's no overlap, each instance "reserves" 2 memories and
 257          * they are uniquely combined here.
 258          */
 259         memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 260
 261         if (REG(OPTC_MEMORY_CONFIG))
 262                 REG_SET(OPTC_MEMORY_CONFIG, 0,
 263                         OPTC_MEM_SEL, memory_mask);
 264
 265         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 266                 data_fmt = 1;
 267         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 268                 data_fmt = 2;
 269
 270         REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 271
 272         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 273                         OPTC_NUM_OF_INPUT_SEGMENT, 1,
 274                         OPTC_SEG0_SRC_SEL, opp_id[0],
 275                         OPTC_SEG1_SRC_SEL, opp_id[1]);
 276
 277         REG_UPDATE(OPTC_WIDTH_CONTROL,
 278                         OPTC_SEGMENT_WIDTH, mpcc_hactive);
 279
 280         REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
 281         optc1->opp_count = opp_cnt;
 282 }
 283
 284 void optc2_get_optc_source(struct timing_generator *optc,
 285                 uint32_t *num_of_src_opp,
 286                 uint32_t *src_opp_id_0,
 287                 uint32_t *src_opp_id_1)
 288 {
 289         uint32_t num_of_input_segments;
 290         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 291
 292         REG_GET_3(OPTC_DATA_SOURCE_SELECT,
 293                         OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
 294                         OPTC_SEG0_SRC_SEL, src_opp_id_0,
 295                         OPTC_SEG1_SRC_SEL, src_opp_id_1);
 296
 297         if (num_of_input_segments == 1)
 298                 *num_of_src_opp = 2;
 299         else
 300                 *num_of_src_opp = 1;
 301
 302         /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
 303         if (*src_opp_id_1 == 0xf)
 304                 *num_of_src_opp = 1;
 305 }
 306
 307 void optc2_set_dwb_source(struct timing_generator *optc,
 308                 uint32_t dwb_pipe_inst)
 309 {
 310         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 311
 312         if (dwb_pipe_inst == 0)
 313                 REG_UPDATE(DWB_SOURCE_SELECT,
 314                                 OPTC_DWB0_SOURCE_SELECT, optc->inst);
 315         else if (dwb_pipe_inst == 1)
 316                 REG_UPDATE(DWB_SOURCE_SELECT,
 317                                 OPTC_DWB1_SOURCE_SELECT, optc->inst);
 318 }
 319
 320 void optc2_triplebuffer_lock(struct timing_generator *optc)
 321 {
 322         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 323
 324         REG_SET(OTG_GLOBAL_CONTROL0, 0,
 325                 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 326
 327         REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 328                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
 329
 330         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 331                 OTG_MASTER_UPDATE_LOCK, 1);
 332
 333         if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 334                 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 335                                 UPDATE_LOCK_STATUS, 1,
 336                                 1, 10);
 337 }
 338
 339 void optc2_triplebuffer_unlock(struct timing_generator *optc)
 340 {
 341         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 342
 343         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 344                 OTG_MASTER_UPDATE_LOCK, 0);
 345
 346         REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 347                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
 348
 349 }
 350
 351 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 352 {
 353         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 354         uint32_t v_blank_start = 0;
 355         uint32_t h_blank_start = 0;
 356
 357         REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
 358
 359         REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
 360                         DIG_UPDATE_LOCATION, 20);
 361
 362         REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
 363
 364         REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
 365
 366         REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 367                         MASTER_UPDATE_LOCK_DB_X,
 368                         h_blank_start - 200 - 1,
 369                         MASTER_UPDATE_LOCK_DB_Y,
 370                         v_blank_start - 1);
 371 }
 372
 373 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
 374 {
 375         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 376
 377         REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 378                                 MASTER_UPDATE_LOCK_DB_X,
 379                                 0,
 380                                 MASTER_UPDATE_LOCK_DB_Y,
 381                                 0);
 382
 383         REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
 384                                 DIG_UPDATE_LOCATION, 0);
 385
 386         REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
 387 }
 388
 389 void optc2_setup_manual_trigger(struct timing_generator *optc)
 390 {
 391         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 392
 393         REG_SET_8(OTG_TRIGA_CNTL, 0,
 394                         OTG_TRIGA_SOURCE_SELECT, 21,
 395                         OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 396                         OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 397                         OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 398                         OTG_TRIGA_POLARITY_SELECT, 0,
 399                         OTG_TRIGA_FREQUENCY_SELECT, 0,
 400                         OTG_TRIGA_DELAY, 0,
 401                         OTG_TRIGA_CLEAR, 1);
 402 }
 403
 404 void optc2_program_manual_trigger(struct timing_generator *optc)
 405 {
 406         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 407
 408         REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
 409                         OTG_TRIGA_MANUAL_TRIG, 1);
 410 }
 411
 412 static struct timing_generator_funcs dcn20_tg_funcs = {
 413                 .validate_timing = optc1_validate_timing,
 414                 .program_timing = optc1_program_timing,
 415                 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
 416                 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
 417                 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
 418                 .program_global_sync = optc1_program_global_sync,
 419                 .enable_crtc = optc2_enable_crtc,
 420                 .disable_crtc = optc1_disable_crtc,
 421                 /* used by enable_timing_synchronization. Not need for FPGA */
 422                 .is_counter_moving = optc1_is_counter_moving,
 423                 .get_position = optc1_get_position,
 424                 .get_frame_count = optc1_get_vblank_counter,
 425                 .get_scanoutpos = optc1_get_crtc_scanoutpos,
 426                 .get_otg_active_size = optc1_get_otg_active_size,
 427                 .set_early_control = optc1_set_early_control,
 428                 /* used by enable_timing_synchronization. Not need for FPGA */
 429                 .wait_for_state = optc1_wait_for_state,
 430                 .set_blank = optc1_set_blank,
 431                 .is_blanked = optc1_is_blanked,
 432                 .set_blank_color = optc1_program_blank_color,
 433                 .enable_reset_trigger = optc1_enable_reset_trigger,
 434                 .enable_crtc_reset = optc1_enable_crtc_reset,
 435                 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
 436                 .triplebuffer_lock = optc2_triplebuffer_lock,
 437                 .triplebuffer_unlock = optc2_triplebuffer_unlock,
 438                 .disable_reset_trigger = optc1_disable_reset_trigger,
 439                 .lock = optc1_lock,
 440                 .unlock = optc1_unlock,
 441                 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
 442                 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 443                 .enable_optc_clock = optc1_enable_optc_clock,
 444                 .set_drr = optc1_set_drr,
 445                 .set_static_screen_control = optc1_set_static_screen_control,
 446                 .program_stereo = optc1_program_stereo,
 447                 .is_stereo_left_eye = optc1_is_stereo_left_eye,
 448                 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
 449                 .tg_init = optc1_tg_init,
 450                 .is_tg_enabled = optc1_is_tg_enabled,
 451                 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
 452                 .clear_optc_underflow = optc1_clear_optc_underflow,
 453                 .setup_global_swap_lock = NULL,
 454                 .get_crc = optc1_get_crc,
 455                 .configure_crc = optc1_configure_crc,
 456                 .set_dsc_config = optc2_set_dsc_config,
 457                 .set_dwb_source = optc2_set_dwb_source,
 458                 .set_odm_bypass = optc2_set_odm_bypass,
 459                 .set_odm_combine = optc2_set_odm_combine,
 460                 .get_optc_source = optc2_get_optc_source,
 461                 .set_gsl = optc2_set_gsl,
 462                 .set_gsl_source_select = optc2_set_gsl_source_select,
 463                 .set_vtg_params = optc1_set_vtg_params,
 464                 .program_manual_trigger = optc2_program_manual_trigger,
 465                 .setup_manual_trigger = optc2_setup_manual_trigger,
 466                 .get_hw_timing = optc1_get_hw_timing,
 467 };
 468
 469 void dcn20_timing_generator_init(struct optc *optc1)
 470 {
 471         optc1->base.funcs = &dcn20_tg_funcs;
 472
 473         optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
 474         optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
 475
 476         optc1->min_h_blank = 32;
 477         optc1->min_v_blank = 3;
 478         optc1->min_v_blank_interlace = 5;
 479         optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
 480         optc1->min_v_sync_width = 1;
 481 }
 482