drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

   1 /*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_RESOURCE_DCN20_H__
  27 #define __DC_RESOURCE_DCN20_H__
  28
  29 #include "core_types.h"
  30
  31 #define TO_DCN20_RES_POOL(pool)\
  32         container_of(pool, struct dcn20_resource_pool, base)
  33
  34 struct dc;
  35 struct resource_pool;
  36 struct _vcs_dpi_display_pipe_params_st;
  37
  38 struct dcn20_resource_pool {
  39         struct resource_pool base;
  40 };
  41 struct resource_pool *dcn20_create_resource_pool(
  42                 const struct dc_init_data *init_data,
  43                 struct dc *dc);
  44
  45 struct link_encoder *dcn20_link_encoder_create(
  46         const struct encoder_init_data *enc_init_data);
  47
  48 unsigned int dcn20_calc_max_scaled_time(
  49                 unsigned int time_per_pixel,
  50                 enum mmhubbub_wbif_mode mode,
  51                 unsigned int urgent_watermark);
  52 int dcn20_populate_dml_pipes_from_context(
  53                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
  54 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
  55                 struct dc_state *state,
  56                 const struct resource_pool *pool,
  57                 struct dc_stream_state *stream);
  58 void dcn20_populate_dml_writeback_from_context(
  59                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
  60
  61 struct stream_encoder *dcn20_stream_encoder_create(
  62         enum engine_id eng_id,
  63         struct dc_context *ctx);
  64
  65 struct dce_hwseq *dcn20_hwseq_create(
  66         struct dc_context *ctx);
  67
  68 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
  69                 const struct dc_dcc_surface_param *input,
  70                 struct dc_surface_dcc_cap *output);
  71
  72 void dcn20_dpp_destroy(struct dpp **dpp);
  73
  74 struct dpp *dcn20_dpp_create(
  75         struct dc_context *ctx,
  76         uint32_t inst);
  77
  78 struct input_pixel_processor *dcn20_ipp_create(
  79         struct dc_context *ctx, uint32_t inst);
  80
  81
  82 struct output_pixel_processor *dcn20_opp_create(
  83         struct dc_context *ctx, uint32_t inst);
  84
  85 struct dce_aux *dcn20_aux_engine_create(
  86         struct dc_context *ctx, uint32_t inst);
  87
  88 struct dce_i2c_hw *dcn20_i2c_hw_create(
  89         struct dc_context *ctx,
  90         uint32_t inst);
  91
  92 void dcn20_clock_source_destroy(struct clock_source **clk_src);
  93
  94 struct display_stream_compressor *dcn20_dsc_create(
  95         struct dc_context *ctx, uint32_t inst);
  96 void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
  97
  98 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
  99 void dcn20_cap_soc_clocks(
 100                 struct _vcs_dpi_soc_bounding_box_st *bb,
 101                 struct pp_smu_nv_clock_table max_clocks);
 102 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
 103                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
 104 struct hubp *dcn20_hubp_create(
 105         struct dc_context *ctx,
 106         uint32_t inst);
 107 struct timing_generator *dcn20_timing_generator_create(
 108                 struct dc_context *ctx,
 109                 uint32_t instance);
 110 struct mpc *dcn20_mpc_create(struct dc_context *ctx);
 111 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx);
 112
 113 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
 114 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);
 115
 116 void dcn20_set_mcif_arb_params(
 117                 struct dc *dc,
 118                 struct dc_state *context,
 119                 display_e2e_pipe_params_st *pipes,
 120                 int pipe_cnt);
 121 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
 122 void dcn20_merge_pipes_for_validate(
 123                 struct dc *dc,
 124                 struct dc_state *context);
 125 int dcn20_validate_apply_pipe_split_flags(
 126                 struct dc *dc,
 127                 struct dc_state *context,
 128                 int vlevel,
 129                 bool *split);
 130 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
 131 void dcn20_split_stream_for_mpc(
 132                 struct resource_context *res_ctx,
 133                 const struct resource_pool *pool,
 134                 struct pipe_ctx *primary_pipe,
 135                 struct pipe_ctx *secondary_pipe);
 136 bool dcn20_split_stream_for_odm(
 137                 struct resource_context *res_ctx,
 138                 const struct resource_pool *pool,
 139                 struct pipe_ctx *prev_odm_pipe,
 140                 struct pipe_ctx *next_odm_pipe);
 141 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 142                 struct resource_context *res_ctx,
 143                 const struct resource_pool *pool,
 144                 const struct pipe_ctx *primary_pipe);
 145 bool dcn20_fast_validate_bw(
 146                 struct dc *dc,
 147                 struct dc_state *context,
 148                 display_e2e_pipe_params_st *pipes,
 149                 int *pipe_cnt_out,
 150                 int *pipe_split_from,
 151                 int *vlevel_out);
 152 void dcn20_calculate_dlg_params(
 153                 struct dc *dc, struct dc_state *context,
 154                 display_e2e_pipe_params_st *pipes,
 155                 int pipe_cnt,
 156                 int vlevel);
 157
 158 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
 159 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
 160 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
 161 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
 162 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
 163
 164 void dcn20_patch_bounding_box(
 165                 struct dc *dc,
 166                 struct _vcs_dpi_soc_bounding_box_st *bb);
 167 void dcn20_cap_soc_clocks(
 168                 struct _vcs_dpi_soc_bounding_box_st *bb,
 169                 struct pp_smu_nv_clock_table max_clocks);
 170
 171 #endif /* __DC_RESOURCE_DCN20_H__ */
 172