drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DISPLAY_MODE_STRUCTS_H__
  26 #define __DISPLAY_MODE_STRUCTS_H__
  27
  28 #define MAX_CLOCK_LIMIT_STATES 8
  29
  30 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
  31 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
  32 typedef struct _vcs_dpi_ip_params_st ip_params_st;
  33 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
  34 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
  35 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
  36 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
  37 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
  38 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
  39 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
  40 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
  41 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
  42 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
  43 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
  44 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
  45 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
  46 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
  47 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
  48 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
  49 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
  50 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
  51 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
  52 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
  53 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
  54
  55 struct _vcs_dpi_voltage_scaling_st {
  56         int state;
  57         double dscclk_mhz;
  58         double dcfclk_mhz;
  59         double socclk_mhz;
  60         double phyclk_d18_mhz;
  61         double dram_speed_mts;
  62         double fabricclk_mhz;
  63         double dispclk_mhz;
  64         double phyclk_mhz;
  65         double dppclk_mhz;
  66         double dtbclk_mhz;
  67 };
  68
  69 struct _vcs_dpi_soc_bounding_box_st {
  70         double sr_exit_time_us;
  71         double sr_enter_plus_exit_time_us;
  72         double urgent_latency_us;
  73         double urgent_latency_pixel_data_only_us;
  74         double urgent_latency_pixel_mixed_with_vm_data_us;
  75         double urgent_latency_vm_data_only_us;
  76         double writeback_latency_us;
  77         double ideal_dram_bw_after_urgent_percent;
  78         double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
  79         double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
  80         double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
  81         double max_avg_sdp_bw_use_normal_percent;
  82         double max_avg_dram_bw_use_normal_percent;
  83         unsigned int max_request_size_bytes;
  84         double downspread_percent;
  85         double dram_page_open_time_ns;
  86         double dram_rw_turnaround_time_ns;
  87         double dram_return_buffer_per_channel_bytes;
  88         double dram_channel_width_bytes;
  89         double fabric_datapath_to_dcn_data_return_bytes;
  90         double dcn_downspread_percent;
  91         double dispclk_dppclk_vco_speed_mhz;
  92         double dfs_vco_period_ps;
  93         unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
  94         unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
  95         unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
  96         unsigned int round_trip_ping_latency_dcfclk_cycles;
  97         unsigned int urgent_out_of_order_return_per_channel_bytes;
  98         unsigned int channel_interleave_bytes;
  99         unsigned int num_banks;
 100         unsigned int num_chans;
 101         unsigned int vmm_page_size_bytes;
 102         unsigned int hostvm_min_page_size_bytes;
 103         unsigned int gpuvm_min_page_size_bytes;
 104         double dram_clock_change_latency_us;
 105         double dummy_pstate_latency_us;
 106         double writeback_dram_clock_change_latency_us;
 107         unsigned int return_bus_width_bytes;
 108         unsigned int voltage_override;
 109         double xfc_bus_transport_time_us;
 110         double xfc_xbuf_latency_tolerance_us;
 111         int use_urgent_burst_bw;
 112         unsigned int num_states;
 113         struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
 114         bool do_urgent_latency_adjustment;
 115         double urgent_latency_adjustment_fabric_clock_component_us;
 116         double urgent_latency_adjustment_fabric_clock_reference_mhz;
 117         bool disable_dram_clock_change_vactive_support;
 118 };
 119
 120 struct _vcs_dpi_ip_params_st {
 121         bool gpuvm_enable;
 122         bool hostvm_enable;
 123         unsigned int gpuvm_max_page_table_levels;
 124         unsigned int hostvm_max_page_table_levels;
 125         unsigned int hostvm_cached_page_table_levels;
 126         unsigned int pte_group_size_bytes;
 127         unsigned int max_inter_dcn_tile_repeaters;
 128         unsigned int num_dsc;
 129         unsigned int odm_capable;
 130         unsigned int rob_buffer_size_kbytes;
 131         unsigned int det_buffer_size_kbytes;
 132         unsigned int dpte_buffer_size_in_pte_reqs_luma;
 133         unsigned int dpte_buffer_size_in_pte_reqs_chroma;
 134         unsigned int pde_proc_buffer_size_64k_reqs;
 135         unsigned int dpp_output_buffer_pixels;
 136         unsigned int opp_output_buffer_lines;
 137         unsigned int pixel_chunk_size_kbytes;
 138         unsigned char pte_enable;
 139         unsigned int pte_chunk_size_kbytes;
 140         unsigned int meta_chunk_size_kbytes;
 141         unsigned int writeback_chunk_size_kbytes;
 142         unsigned int line_buffer_size_bits;
 143         unsigned int max_line_buffer_lines;
 144         unsigned int writeback_luma_buffer_size_kbytes;
 145         unsigned int writeback_chroma_buffer_size_kbytes;
 146         unsigned int writeback_chroma_line_buffer_width_pixels;
 147
 148         unsigned int writeback_interface_buffer_size_kbytes;
 149         unsigned int writeback_line_buffer_buffer_size;
 150
 151         unsigned int writeback_10bpc420_supported;
 152         double writeback_max_hscl_ratio;
 153         double writeback_max_vscl_ratio;
 154         double writeback_min_hscl_ratio;
 155         double writeback_min_vscl_ratio;
 156         unsigned int writeback_max_hscl_taps;
 157         unsigned int writeback_max_vscl_taps;
 158         unsigned int writeback_line_buffer_luma_buffer_size;
 159         unsigned int writeback_line_buffer_chroma_buffer_size;
 160
 161         unsigned int max_page_table_levels;
 162         unsigned int max_num_dpp;
 163         unsigned int max_num_otg;
 164         unsigned int cursor_chunk_size;
 165         unsigned int cursor_buffer_size;
 166         unsigned int max_num_wb;
 167         unsigned int max_dchub_pscl_bw_pix_per_clk;
 168         unsigned int max_pscl_lb_bw_pix_per_clk;
 169         unsigned int max_lb_vscl_bw_pix_per_clk;
 170         unsigned int max_vscl_hscl_bw_pix_per_clk;
 171         double max_hscl_ratio;
 172         double max_vscl_ratio;
 173         unsigned int hscl_mults;
 174         unsigned int vscl_mults;
 175         unsigned int max_hscl_taps;
 176         unsigned int max_vscl_taps;
 177         unsigned int xfc_supported;
 178         unsigned int ptoi_supported;
 179         unsigned int gfx7_compat_tiling_supported;
 180
 181         bool odm_combine_4to1_supported;
 182         bool dynamic_metadata_vm_enabled;
 183         unsigned int max_num_hdmi_frl_outputs;
 184
 185         unsigned int xfc_fill_constant_bytes;
 186         double dispclk_ramp_margin_percent;
 187         double xfc_fill_bw_overhead_percent;
 188         double underscan_factor;
 189         unsigned int min_vblank_lines;
 190         unsigned int dppclk_delay_subtotal;
 191         unsigned int dispclk_delay_subtotal;
 192         unsigned int dcfclk_cstate_latency;
 193         unsigned int dppclk_delay_scl;
 194         unsigned int dppclk_delay_scl_lb_only;
 195         unsigned int dppclk_delay_cnvc_formatter;
 196         unsigned int dppclk_delay_cnvc_cursor;
 197         unsigned int is_line_buffer_bpp_fixed;
 198         unsigned int line_buffer_fixed_bpp;
 199         unsigned int dcc_supported;
 200
 201         unsigned int IsLineBufferBppFixed;
 202         unsigned int LineBufferFixedBpp;
 203         unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 204         unsigned int bug_forcing_LC_req_same_size_fixed;
 205 };
 206
 207 struct _vcs_dpi_display_xfc_params_st {
 208         double xfc_tslv_vready_offset_us;
 209         double xfc_tslv_vupdate_width_us;
 210         double xfc_tslv_vupdate_offset_us;
 211         int xfc_slv_chunk_size_bytes;
 212 };
 213
 214 struct _vcs_dpi_display_pipe_source_params_st {
 215         int source_format;
 216         unsigned char dcc;
 217         unsigned int dcc_rate;
 218         unsigned int dcc_rate_chroma;
 219         unsigned char dcc_use_global;
 220         unsigned char vm;
 221         bool gpuvm;    // gpuvm enabled
 222         bool hostvm;    // hostvm enabled
 223         bool gpuvm_levels_force_en;
 224         unsigned int gpuvm_levels_force;
 225         bool hostvm_levels_force_en;
 226         unsigned int hostvm_levels_force;
 227         int source_scan;
 228         int sw_mode;
 229         int macro_tile_size;
 230         unsigned int surface_width_y;
 231         unsigned int surface_height_y;
 232         unsigned int surface_width_c;
 233         unsigned int surface_height_c;
 234         unsigned int viewport_width;
 235         unsigned int viewport_height;
 236         unsigned int viewport_y_y;
 237         unsigned int viewport_y_c;
 238         unsigned int viewport_width_c;
 239         unsigned int viewport_height_c;
 240         unsigned int data_pitch;
 241         unsigned int data_pitch_c;
 242         unsigned int meta_pitch;
 243         unsigned int meta_pitch_c;
 244         unsigned int cur0_src_width;
 245         int cur0_bpp;
 246         unsigned int cur1_src_width;
 247         int cur1_bpp;
 248         int num_cursors;
 249         unsigned char is_hsplit;
 250         unsigned char dynamic_metadata_enable;
 251         unsigned int dynamic_metadata_lines_before_active;
 252         unsigned int dynamic_metadata_xmit_bytes;
 253         unsigned int hsplit_grp;
 254         unsigned char xfc_enable;
 255         unsigned char xfc_slave;
 256         unsigned char immediate_flip;
 257         struct _vcs_dpi_display_xfc_params_st xfc_params;
 258         //for vstartuplines calculation freesync
 259         unsigned char v_total_min;
 260         unsigned char v_total_max;
 261 };
 262 struct writeback_st {
 263         int wb_src_height;
 264         int wb_src_width;
 265         int wb_dst_width;
 266         int wb_dst_height;
 267         int wb_pixel_format;
 268         int wb_htaps_luma;
 269         int wb_vtaps_luma;
 270         int wb_htaps_chroma;
 271         int wb_vtaps_chroma;
 272         double wb_hratio;
 273         double wb_vratio;
 274 };
 275
 276 struct _vcs_dpi_display_output_params_st {
 277         int dp_lanes;
 278         double output_bpp;
 279         int dsc_enable;
 280         int wb_enable;
 281         int num_active_wb;
 282         int output_bpc;
 283         int output_type;
 284         int output_format;
 285         int dsc_slices;
 286         int max_audio_sample_rate;
 287         struct writeback_st wb;
 288 };
 289
 290 struct _vcs_dpi_scaler_ratio_depth_st {
 291         double hscl_ratio;
 292         double vscl_ratio;
 293         double hscl_ratio_c;
 294         double vscl_ratio_c;
 295         double vinit;
 296         double vinit_c;
 297         double vinit_bot;
 298         double vinit_bot_c;
 299         int lb_depth;
 300         int scl_enable;
 301 };
 302
 303 struct _vcs_dpi_scaler_taps_st {
 304         unsigned int htaps;
 305         unsigned int vtaps;
 306         unsigned int htaps_c;
 307         unsigned int vtaps_c;
 308 };
 309
 310 struct _vcs_dpi_display_pipe_dest_params_st {
 311         unsigned int recout_width;
 312         unsigned int recout_height;
 313         unsigned int full_recout_width;
 314         unsigned int full_recout_height;
 315         unsigned int hblank_start;
 316         unsigned int hblank_end;
 317         unsigned int vblank_start;
 318         unsigned int vblank_end;
 319         unsigned int htotal;
 320         unsigned int vtotal;
 321         unsigned int vactive;
 322         unsigned int hactive;
 323         unsigned int vstartup_start;
 324         unsigned int vupdate_offset;
 325         unsigned int vupdate_width;
 326         unsigned int vready_offset;
 327         unsigned char interlaced;
 328         unsigned char embedded;
 329         double pixel_rate_mhz;
 330         unsigned char synchronized_vblank_all_planes;
 331         unsigned char otg_inst;
 332         unsigned int odm_combine;
 333         unsigned char use_maximum_vstartup;
 334         unsigned int vtotal_max;
 335         unsigned int vtotal_min;
 336 };
 337
 338 struct _vcs_dpi_display_pipe_params_st {
 339         display_pipe_source_params_st src;
 340         display_pipe_dest_params_st dest;
 341         scaler_ratio_depth_st scale_ratio_depth;
 342         scaler_taps_st scale_taps;
 343 };
 344
 345 struct _vcs_dpi_display_clocks_and_cfg_st {
 346         int voltage;
 347         double dppclk_mhz;
 348         double refclk_mhz;
 349         double dispclk_mhz;
 350         double dcfclk_mhz;
 351         double socclk_mhz;
 352 };
 353
 354 struct _vcs_dpi_display_e2e_pipe_params_st {
 355         display_pipe_params_st pipe;
 356         display_output_params_st dout;
 357         display_clocks_and_cfg_st clks_cfg;
 358 };
 359
 360 struct _vcs_dpi_display_data_rq_misc_params_st {
 361         unsigned int full_swath_bytes;
 362         unsigned int stored_swath_bytes;
 363         unsigned int blk256_height;
 364         unsigned int blk256_width;
 365         unsigned int req_height;
 366         unsigned int req_width;
 367 };
 368
 369 struct _vcs_dpi_display_data_rq_sizing_params_st {
 370         unsigned int chunk_bytes;
 371         unsigned int min_chunk_bytes;
 372         unsigned int meta_chunk_bytes;
 373         unsigned int min_meta_chunk_bytes;
 374         unsigned int mpte_group_bytes;
 375         unsigned int dpte_group_bytes;
 376 };
 377
 378 struct _vcs_dpi_display_data_rq_dlg_params_st {
 379         unsigned int swath_width_ub;
 380         unsigned int swath_height;
 381         unsigned int req_per_swath_ub;
 382         unsigned int meta_pte_bytes_per_frame_ub;
 383         unsigned int dpte_req_per_row_ub;
 384         unsigned int dpte_groups_per_row_ub;
 385         unsigned int dpte_row_height;
 386         unsigned int dpte_bytes_per_row_ub;
 387         unsigned int meta_chunks_per_row_ub;
 388         unsigned int meta_req_per_row_ub;
 389         unsigned int meta_row_height;
 390         unsigned int meta_bytes_per_row_ub;
 391 };
 392
 393 struct _vcs_dpi_display_rq_dlg_params_st {
 394         display_data_rq_dlg_params_st rq_l;
 395         display_data_rq_dlg_params_st rq_c;
 396 };
 397
 398 struct _vcs_dpi_display_rq_sizing_params_st {
 399         display_data_rq_sizing_params_st rq_l;
 400         display_data_rq_sizing_params_st rq_c;
 401 };
 402
 403 struct _vcs_dpi_display_rq_misc_params_st {
 404         display_data_rq_misc_params_st rq_l;
 405         display_data_rq_misc_params_st rq_c;
 406 };
 407
 408 struct _vcs_dpi_display_rq_params_st {
 409         unsigned char yuv420;
 410         unsigned char yuv420_10bpc;
 411         unsigned char rgbe_alpha;
 412         display_rq_misc_params_st misc;
 413         display_rq_sizing_params_st sizing;
 414         display_rq_dlg_params_st dlg;
 415 };
 416
 417 struct _vcs_dpi_display_dlg_regs_st {
 418         unsigned int refcyc_h_blank_end;
 419         unsigned int dlg_vblank_end;
 420         unsigned int min_dst_y_next_start;
 421         unsigned int refcyc_per_htotal;
 422         unsigned int refcyc_x_after_scaler;
 423         unsigned int dst_y_after_scaler;
 424         unsigned int dst_y_prefetch;
 425         unsigned int dst_y_per_vm_vblank;
 426         unsigned int dst_y_per_row_vblank;
 427         unsigned int dst_y_per_vm_flip;
 428         unsigned int dst_y_per_row_flip;
 429         unsigned int ref_freq_to_pix_freq;
 430         unsigned int vratio_prefetch;
 431         unsigned int vratio_prefetch_c;
 432         unsigned int refcyc_per_pte_group_vblank_l;
 433         unsigned int refcyc_per_pte_group_vblank_c;
 434         unsigned int refcyc_per_meta_chunk_vblank_l;
 435         unsigned int refcyc_per_meta_chunk_vblank_c;
 436         unsigned int refcyc_per_pte_group_flip_l;
 437         unsigned int refcyc_per_pte_group_flip_c;
 438         unsigned int refcyc_per_meta_chunk_flip_l;
 439         unsigned int refcyc_per_meta_chunk_flip_c;
 440         unsigned int dst_y_per_pte_row_nom_l;
 441         unsigned int dst_y_per_pte_row_nom_c;
 442         unsigned int refcyc_per_pte_group_nom_l;
 443         unsigned int refcyc_per_pte_group_nom_c;
 444         unsigned int dst_y_per_meta_row_nom_l;
 445         unsigned int dst_y_per_meta_row_nom_c;
 446         unsigned int refcyc_per_meta_chunk_nom_l;
 447         unsigned int refcyc_per_meta_chunk_nom_c;
 448         unsigned int refcyc_per_line_delivery_pre_l;
 449         unsigned int refcyc_per_line_delivery_pre_c;
 450         unsigned int refcyc_per_line_delivery_l;
 451         unsigned int refcyc_per_line_delivery_c;
 452         unsigned int chunk_hdl_adjust_cur0;
 453         unsigned int chunk_hdl_adjust_cur1;
 454         unsigned int vready_after_vcount0;
 455         unsigned int dst_y_offset_cur0;
 456         unsigned int dst_y_offset_cur1;
 457         unsigned int xfc_reg_transfer_delay;
 458         unsigned int xfc_reg_precharge_delay;
 459         unsigned int xfc_reg_remote_surface_flip_latency;
 460         unsigned int xfc_reg_prefetch_margin;
 461         unsigned int dst_y_delta_drq_limit;
 462         unsigned int refcyc_per_vm_group_vblank;
 463         unsigned int refcyc_per_vm_group_flip;
 464         unsigned int refcyc_per_vm_req_vblank;
 465         unsigned int refcyc_per_vm_req_flip;
 466         unsigned int refcyc_per_vm_dmdata;
 467 };
 468
 469 struct _vcs_dpi_display_ttu_regs_st {
 470         unsigned int qos_level_low_wm;
 471         unsigned int qos_level_high_wm;
 472         unsigned int min_ttu_vblank;
 473         unsigned int qos_level_flip;
 474         unsigned int refcyc_per_req_delivery_l;
 475         unsigned int refcyc_per_req_delivery_c;
 476         unsigned int refcyc_per_req_delivery_cur0;
 477         unsigned int refcyc_per_req_delivery_cur1;
 478         unsigned int refcyc_per_req_delivery_pre_l;
 479         unsigned int refcyc_per_req_delivery_pre_c;
 480         unsigned int refcyc_per_req_delivery_pre_cur0;
 481         unsigned int refcyc_per_req_delivery_pre_cur1;
 482         unsigned int qos_level_fixed_l;
 483         unsigned int qos_level_fixed_c;
 484         unsigned int qos_level_fixed_cur0;
 485         unsigned int qos_level_fixed_cur1;
 486         unsigned int qos_ramp_disable_l;
 487         unsigned int qos_ramp_disable_c;
 488         unsigned int qos_ramp_disable_cur0;
 489         unsigned int qos_ramp_disable_cur1;
 490 };
 491
 492 struct _vcs_dpi_display_data_rq_regs_st {
 493         unsigned int chunk_size;
 494         unsigned int min_chunk_size;
 495         unsigned int meta_chunk_size;
 496         unsigned int min_meta_chunk_size;
 497         unsigned int dpte_group_size;
 498         unsigned int mpte_group_size;
 499         unsigned int swath_height;
 500         unsigned int pte_row_height_linear;
 501 };
 502
 503 struct _vcs_dpi_display_rq_regs_st {
 504         display_data_rq_regs_st rq_regs_l;
 505         display_data_rq_regs_st rq_regs_c;
 506         unsigned int drq_expansion_mode;
 507         unsigned int prq_expansion_mode;
 508         unsigned int mrq_expansion_mode;
 509         unsigned int crq_expansion_mode;
 510         unsigned int plane1_base_address;
 511 };
 512
 513 struct _vcs_dpi_display_dlg_sys_params_st {
 514         double t_mclk_wm_us;
 515         double t_urg_wm_us;
 516         double t_sr_wm_us;
 517         double t_extra_us;
 518         double mem_trip_us;
 519         double t_srx_delay_us;
 520         double deepsleep_dcfclk_mhz;
 521         double total_flip_bw;
 522         unsigned int total_flip_bytes;
 523 };
 524
 525 struct _vcs_dpi_display_arb_params_st {
 526         int max_req_outstanding;
 527         int min_req_outstanding;
 528         int sat_level_us;
 529 };
 530
 531 #endif /*__DISPLAY_MODE_STRUCTS_H__*/