drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 /*
  29  * Pre-requisites: headers required by header of this unit
  30  */
  31 #include "include/gpio_types.h"
  32
  33 /*
  34  * Header of this unit
  35  */
  36
  37 #include "hw_translate.h"
  38
  39 /*
  40  * Post-requisites: headers required by this unit
  41  */
  42
  43 #include "dce80/hw_translate_dce80.h"
  44 #include "dce110/hw_translate_dce110.h"
  45 #include "dce120/hw_translate_dce120.h"
  46 #if defined(CONFIG_DRM_AMD_DC_DCN)
  47 #include "dcn10/hw_translate_dcn10.h"
  48 #endif
  49 #include "dcn20/hw_translate_dcn20.h"
  50 #include "dcn21/hw_translate_dcn21.h"
  51
  52 #include "diagnostics/hw_translate_diag.h"
  53
  54 /*
  55  * This unit
  56  */
  57
  58 bool dal_hw_translate_init(
  59         struct hw_translate *translate,
  60         enum dce_version dce_version,
  61         enum dce_environment dce_environment)
  62 {
  63         if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
  64                 dal_hw_translate_diag_fpga_init(translate);
  65                 return true;
  66         }
  67
  68         switch (dce_version) {
  69         case DCE_VERSION_8_0:
  70         case DCE_VERSION_8_1:
  71         case DCE_VERSION_8_3:
  72                 dal_hw_translate_dce80_init(translate);
  73                 return true;
  74         case DCE_VERSION_10_0:
  75         case DCE_VERSION_11_0:
  76         case DCE_VERSION_11_2:
  77         case DCE_VERSION_11_22:
  78                 dal_hw_translate_dce110_init(translate);
  79                 return true;
  80         case DCE_VERSION_12_0:
  81         case DCE_VERSION_12_1:
  82                 dal_hw_translate_dce120_init(translate);
  83                 return true;
  84 #if defined(CONFIG_DRM_AMD_DC_DCN)
  85         case DCN_VERSION_1_0:
  86         case DCN_VERSION_1_01:
  87                 dal_hw_translate_dcn10_init(translate);
  88                 return true;
  89
  90         case DCN_VERSION_2_0:
  91                 dal_hw_translate_dcn20_init(translate);
  92                 return true;
  93         case DCN_VERSION_2_1:
  94                 dal_hw_translate_dcn21_init(translate);
  95                 return true;
  96 #endif
  97
  98         default:
  99                 BREAK_TO_DEBUGGER();
 100                 return false;
 101         }
 102 }