drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../inc/dmub_srv.h"
  27 #include "dmub_reg.h"
  28 #include "dmub_dcn20.h"
  29
  30 #include "dcn/dcn_2_0_0_offset.h"
  31 #include "dcn/dcn_2_0_0_sh_mask.h"
  32 #include "soc15_hw_ip.h"
  33 #include "vega10_ip_offset.h"
  34
  35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
  36 #define CTX dmub
  37 #define REGS dmub->regs
  38
  39 /* Registers. */
  40
  41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
  42 #define DMUB_SR(reg) REG_OFFSET(reg),
  43         { DMUB_COMMON_REGS() },
  44 #undef DMUB_SR
  45
  46 #define DMUB_SF(reg, field) FD_MASK(reg, field),
  47         { DMUB_COMMON_FIELDS() },
  48 #undef DMUB_SF
  49
  50 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
  51         { DMUB_COMMON_FIELDS() },
  52 #undef DMUB_SF
  53 };
  54
  55 /* Shared functions. */
  56
  57 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
  58                                              uint64_t fb_base,
  59                                              uint64_t fb_offset,
  60                                              union dmub_addr *addr_out)
  61 {
  62         addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
  63 }
  64
  65 void dmub_dcn20_reset(struct dmub_srv *dmub)
  66 {
  67         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
  68         REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
  69         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
  70 }
  71
  72 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
  73 {
  74         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
  75         REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
  76         REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
  77         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
  78 }
  79
  80 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
  81                               const struct dmub_window *cw0,
  82                               const struct dmub_window *cw1)
  83 {
  84         union dmub_addr offset;
  85         uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
  86
  87         REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
  88         REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
  89                      DMCUB_MEM_WRITE_SPACE, 0x3);
  90
  91         dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
  92
  93         REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
  94         REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
  95         REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
  96         REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
  97                   DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
  98                   DMCUB_REGION3_CW0_ENABLE, 1);
  99
 100         dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
 101
 102         REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
 103         REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
 104         REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
 105         REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
 106                   DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
 107                   DMCUB_REGION3_CW1_ENABLE, 1);
 108
 109         REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
 110                      0x20);
 111 }
 112
 113 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
 114                               const struct dmub_window *cw2,
 115                               const struct dmub_window *cw3,
 116                               const struct dmub_window *cw4,
 117                               const struct dmub_window *cw5,
 118                               const struct dmub_window *cw6)
 119 {
 120         union dmub_addr offset;
 121         uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
 122
 123         dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
 124
 125         REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
 126         REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
 127         REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
 128         REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
 129                   DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
 130                   DMCUB_REGION3_CW2_ENABLE, 1);
 131
 132         dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
 133
 134         REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
 135         REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
 136         REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
 137         REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
 138                   DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
 139                   DMCUB_REGION3_CW3_ENABLE, 1);
 140
 141         /* TODO: Move this to CW4. */
 142         dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
 143
 144         REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
 145         REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
 146         REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
 147                   cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
 148                   1);
 149
 150         dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
 151
 152         REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
 153         REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
 154         REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
 155         REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
 156                   DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
 157                   DMCUB_REGION3_CW5_ENABLE, 1);
 158
 159         dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
 160
 161         REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
 162         REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
 163         REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
 164         REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
 165                   DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
 166                   DMCUB_REGION3_CW6_ENABLE, 1);
 167 }
 168
 169 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
 170                               const struct dmub_region *inbox1)
 171 {
 172         /* TODO: Use CW4 instead of region 4. */
 173
 174         REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
 175         REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
 176         REG_WRITE(DMCUB_INBOX1_RPTR, 0);
 177         REG_WRITE(DMCUB_INBOX1_WPTR, 0);
 178 }
 179
 180 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
 181 {
 182         return REG_READ(DMCUB_INBOX1_RPTR);
 183 }
 184
 185 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
 186 {
 187         REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
 188 }
 189
 190 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
 191 {
 192         return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
 193 }
 194
 195 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
 196 {
 197         uint32_t supported = 0;
 198
 199         REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
 200
 201         return supported;
 202 }