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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / include / arct_ip_offset.h
bloba7791a9e1f90596e52476945092a877ba5d21206
1 /*
2 * Copyright (C) 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21 #ifndef _arct_ip_offset_HEADER
22 #define _arct_ip_offset_HEADER
23
24 #define MAX_INSTANCE 8
25 #define MAX_SEGMENT 6
26
27
28 struct IP_BASE_INSTANCE
29 {
30 unsigned int segment[MAX_SEGMENT];
31 };
32
33 struct IP_BASE
34 {
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36 };
37
38
39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0, 0 } } } };
47 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
48 { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },
49 { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },
50 { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },
51 { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },
52 { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },
53 { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0, 0 } } } };
55 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0, 0 } } } };
63 static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0, 0 } },
68 { { 0, 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0, 0 } } } };
71 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },
72 { { 0, 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0, 0 } },
75 { { 0, 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0, 0 } } } };
79 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0, 0 } },
81 { { 0, 0, 0, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0, 0 } } } };
87 static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
88 { { 0, 0, 0, 0, 0, 0 } },
89 { { 0, 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0, 0 } } } };
95 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0, 0 } } } };
103 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0, 0 } } } };
111 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },
112 { { 0, 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0, 0 } },
116 { { 0, 0, 0, 0, 0, 0 } },
117 { { 0, 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0, 0 } } } };
119 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0, 0 } },
123 { { 0, 0, 0, 0, 0, 0 } },
124 { { 0, 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0, 0 } } } };
127 static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0, 0 } } } };
135 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0, 0 } },
137 { { 0, 0, 0, 0, 0, 0 } },
138 { { 0, 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0, 0 } } } };
143 static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
144 { { 0, 0, 0, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0, 0 } } } };
151 static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
152 { { 0, 0, 0, 0, 0, 0 } },
153 { { 0, 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0, 0 } },
158 { { 0, 0, 0, 0, 0, 0 } } } };
159 static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0, 0 } },
165 { { 0, 0, 0, 0, 0, 0 } },
166 { { 0, 0, 0, 0, 0, 0 } } } };
167 static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0, 0 } },
172 { { 0, 0, 0, 0, 0, 0 } },
173 { { 0, 0, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0, 0 } } } };
175 static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0, 0 } },
181 { { 0, 0, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0, 0 } } } };
183 static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0, 0 } },
186 { { 0, 0, 0, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0, 0 } } } };
191 static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0, 0 } },
193 { { 0, 0, 0, 0, 0, 0 } },
194 { { 0, 0, 0, 0, 0, 0 } },
195 { { 0, 0, 0, 0, 0, 0 } },
196 { { 0, 0, 0, 0, 0, 0 } },
197 { { 0, 0, 0, 0, 0, 0 } },
198 { { 0, 0, 0, 0, 0, 0 } } } };
199 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
200 { { 0, 0, 0, 0, 0, 0 } },
201 { { 0, 0, 0, 0, 0, 0 } },
202 { { 0, 0, 0, 0, 0, 0 } },
203 { { 0, 0, 0, 0, 0, 0 } },
204 { { 0, 0, 0, 0, 0, 0 } } } };
205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
206 { { 0, 0, 0, 0, 0, 0 } },
207 { { 0, 0, 0, 0, 0, 0 } },
208 { { 0, 0, 0, 0, 0, 0 } },
209 { { 0, 0, 0, 0, 0, 0 } },
210 { { 0, 0, 0, 0, 0, 0 } } } };
211 static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },
212 { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },
213 { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },
214 { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },
215 { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },
216 { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },
217 { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },
218 { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };
219 static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },
220 { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },
221 { { 0, 0, 0, 0, 0, 0 } },
222 { { 0, 0, 0, 0, 0, 0 } },
223 { { 0, 0, 0, 0, 0, 0 } },
224 { { 0, 0, 0, 0, 0, 0 } },
225 { { 0, 0, 0, 0, 0, 0 } },
226 { { 0, 0, 0, 0, 0, 0 } } } };
227 static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },
228 { { 0, 0, 0, 0, 0, 0 } },
229 { { 0, 0, 0, 0, 0, 0 } },
230 { { 0, 0, 0, 0, 0, 0 } },
231 { { 0, 0, 0, 0, 0, 0 } },
232 { { 0, 0, 0, 0, 0, 0 } },
233 { { 0, 0, 0, 0, 0, 0 } },
234 { { 0, 0, 0, 0, 0, 0 } } } };
235 static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
236 { { 0, 0, 0, 0, 0, 0 } },
237 { { 0, 0, 0, 0, 0, 0 } },
238 { { 0, 0, 0, 0, 0, 0 } },
239 { { 0, 0, 0, 0, 0, 0 } },
240 { { 0, 0, 0, 0, 0, 0 } },
241 { { 0, 0, 0, 0, 0, 0 } },
242 { { 0, 0, 0, 0, 0, 0 } } } };
243
244
245
246 #define ATHUB_BASE__INST0_SEG0 0x00000C20
247 #define ATHUB_BASE__INST0_SEG1 0x00012460
248 #define ATHUB_BASE__INST0_SEG2 0x00408C00
249 #define ATHUB_BASE__INST0_SEG3 0
250 #define ATHUB_BASE__INST0_SEG4 0
251 #define ATHUB_BASE__INST0_SEG5 0
252
253 #define ATHUB_BASE__INST1_SEG0 0
254 #define ATHUB_BASE__INST1_SEG1 0
255 #define ATHUB_BASE__INST1_SEG2 0
256 #define ATHUB_BASE__INST1_SEG3 0
257 #define ATHUB_BASE__INST1_SEG4 0
258 #define ATHUB_BASE__INST1_SEG5 0
259
260 #define ATHUB_BASE__INST2_SEG0 0
261 #define ATHUB_BASE__INST2_SEG1 0
262 #define ATHUB_BASE__INST2_SEG2 0
263 #define ATHUB_BASE__INST2_SEG3 0
264 #define ATHUB_BASE__INST2_SEG4 0
265 #define ATHUB_BASE__INST2_SEG5 0
266
267 #define ATHUB_BASE__INST3_SEG0 0
268 #define ATHUB_BASE__INST3_SEG1 0
269 #define ATHUB_BASE__INST3_SEG2 0
270 #define ATHUB_BASE__INST3_SEG3 0
271 #define ATHUB_BASE__INST3_SEG4 0
272 #define ATHUB_BASE__INST3_SEG5 0
273
274 #define ATHUB_BASE__INST4_SEG0 0
275 #define ATHUB_BASE__INST4_SEG1 0
276 #define ATHUB_BASE__INST4_SEG2 0
277 #define ATHUB_BASE__INST4_SEG3 0
278 #define ATHUB_BASE__INST4_SEG4 0
279 #define ATHUB_BASE__INST4_SEG5 0
280
281 #define ATHUB_BASE__INST5_SEG0 0
282 #define ATHUB_BASE__INST5_SEG1 0
283 #define ATHUB_BASE__INST5_SEG2 0
284 #define ATHUB_BASE__INST5_SEG3 0
285 #define ATHUB_BASE__INST5_SEG4 0
286 #define ATHUB_BASE__INST5_SEG5 0
287
288 #define ATHUB_BASE__INST6_SEG0 0
289 #define ATHUB_BASE__INST6_SEG1 0
290 #define ATHUB_BASE__INST6_SEG2 0
291 #define ATHUB_BASE__INST6_SEG3 0
292 #define ATHUB_BASE__INST6_SEG4 0
293 #define ATHUB_BASE__INST6_SEG5 0
294
295 #define ATHUB_BASE__INST7_SEG0 0
296 #define ATHUB_BASE__INST7_SEG1 0
297 #define ATHUB_BASE__INST7_SEG2 0
298 #define ATHUB_BASE__INST7_SEG3 0
299 #define ATHUB_BASE__INST7_SEG4 0
300 #define ATHUB_BASE__INST7_SEG5 0
301
302 #define CLK_BASE__INST0_SEG0 0x000120C0
303 #define CLK_BASE__INST0_SEG1 0x00016C00
304 #define CLK_BASE__INST0_SEG2 0x00401800
305 #define CLK_BASE__INST0_SEG3 0
306 #define CLK_BASE__INST0_SEG4 0
307 #define CLK_BASE__INST0_SEG5 0
308
309 #define CLK_BASE__INST1_SEG0 0x000120E0
310 #define CLK_BASE__INST1_SEG1 0x00016E00
311 #define CLK_BASE__INST1_SEG2 0x00401C00
312 #define CLK_BASE__INST1_SEG3 0
313 #define CLK_BASE__INST1_SEG4 0
314 #define CLK_BASE__INST1_SEG5 0
315
316 #define CLK_BASE__INST2_SEG0 0x00012100
317 #define CLK_BASE__INST2_SEG1 0x00017000
318 #define CLK_BASE__INST2_SEG2 0x00402000
319 #define CLK_BASE__INST2_SEG3 0
320 #define CLK_BASE__INST2_SEG4 0
321 #define CLK_BASE__INST2_SEG5 0
322
323 #define CLK_BASE__INST3_SEG0 0x00012120
324 #define CLK_BASE__INST3_SEG1 0x00017200
325 #define CLK_BASE__INST3_SEG2 0x00402400
326 #define CLK_BASE__INST3_SEG3 0
327 #define CLK_BASE__INST3_SEG4 0
328 #define CLK_BASE__INST3_SEG5 0
329
330 #define CLK_BASE__INST4_SEG0 0x000136C0
331 #define CLK_BASE__INST4_SEG1 0x0001B000
332 #define CLK_BASE__INST4_SEG2 0x0042D800
333 #define CLK_BASE__INST4_SEG3 0
334 #define CLK_BASE__INST4_SEG4 0
335 #define CLK_BASE__INST4_SEG5 0
336
337 #define CLK_BASE__INST5_SEG0 0x00013720
338 #define CLK_BASE__INST5_SEG1 0x0001B200
339 #define CLK_BASE__INST5_SEG2 0x0042E400
340 #define CLK_BASE__INST5_SEG3 0
341 #define CLK_BASE__INST5_SEG4 0
342 #define CLK_BASE__INST5_SEG5 0
343
344 #define CLK_BASE__INST6_SEG0 0x000125E0
345 #define CLK_BASE__INST6_SEG1 0x00017E00
346 #define CLK_BASE__INST6_SEG2 0x0040BC00
347 #define CLK_BASE__INST6_SEG3 0
348 #define CLK_BASE__INST6_SEG4 0
349 #define CLK_BASE__INST6_SEG5 0
350
351 #define CLK_BASE__INST7_SEG0 0
352 #define CLK_BASE__INST7_SEG1 0
353 #define CLK_BASE__INST7_SEG2 0
354 #define CLK_BASE__INST7_SEG3 0
355 #define CLK_BASE__INST7_SEG4 0
356 #define CLK_BASE__INST7_SEG5 0
357
358 #define DF_BASE__INST0_SEG0 0x00007000
359 #define DF_BASE__INST0_SEG1 0x000125C0
360 #define DF_BASE__INST0_SEG2 0x0040B800
361 #define DF_BASE__INST0_SEG3 0
362 #define DF_BASE__INST0_SEG4 0
363 #define DF_BASE__INST0_SEG5 0
364
365 #define DF_BASE__INST1_SEG0 0
366 #define DF_BASE__INST1_SEG1 0
367 #define DF_BASE__INST1_SEG2 0
368 #define DF_BASE__INST1_SEG3 0
369 #define DF_BASE__INST1_SEG4 0
370 #define DF_BASE__INST1_SEG5 0
371
372 #define DF_BASE__INST2_SEG0 0
373 #define DF_BASE__INST2_SEG1 0
374 #define DF_BASE__INST2_SEG2 0
375 #define DF_BASE__INST2_SEG3 0
376 #define DF_BASE__INST2_SEG4 0
377 #define DF_BASE__INST2_SEG5 0
378
379 #define DF_BASE__INST3_SEG0 0
380 #define DF_BASE__INST3_SEG1 0
381 #define DF_BASE__INST3_SEG2 0
382 #define DF_BASE__INST3_SEG3 0
383 #define DF_BASE__INST3_SEG4 0
384 #define DF_BASE__INST3_SEG5 0
385
386 #define DF_BASE__INST4_SEG0 0
387 #define DF_BASE__INST4_SEG1 0
388 #define DF_BASE__INST4_SEG2 0
389 #define DF_BASE__INST4_SEG3 0
390 #define DF_BASE__INST4_SEG4 0
391 #define DF_BASE__INST4_SEG5 0
392
393 #define DF_BASE__INST5_SEG0 0
394 #define DF_BASE__INST5_SEG1 0
395 #define DF_BASE__INST5_SEG2 0
396 #define DF_BASE__INST5_SEG3 0
397 #define DF_BASE__INST5_SEG4 0
398 #define DF_BASE__INST5_SEG5 0
399
400 #define DF_BASE__INST6_SEG0 0
401 #define DF_BASE__INST6_SEG1 0
402 #define DF_BASE__INST6_SEG2 0
403 #define DF_BASE__INST6_SEG3 0
404 #define DF_BASE__INST6_SEG4 0
405 #define DF_BASE__INST6_SEG5 0
406
407 #define DF_BASE__INST7_SEG0 0
408 #define DF_BASE__INST7_SEG1 0
409 #define DF_BASE__INST7_SEG2 0
410 #define DF_BASE__INST7_SEG3 0
411 #define DF_BASE__INST7_SEG4 0
412 #define DF_BASE__INST7_SEG5 0
413
414 #define FUSE_BASE__INST0_SEG0 0x000120A0
415 #define FUSE_BASE__INST0_SEG1 0x00017400
416 #define FUSE_BASE__INST0_SEG2 0x00401400
417 #define FUSE_BASE__INST0_SEG3 0
418 #define FUSE_BASE__INST0_SEG4 0
419 #define FUSE_BASE__INST0_SEG5 0
420
421 #define FUSE_BASE__INST1_SEG0 0
422 #define FUSE_BASE__INST1_SEG1 0
423 #define FUSE_BASE__INST1_SEG2 0
424 #define FUSE_BASE__INST1_SEG3 0
425 #define FUSE_BASE__INST1_SEG4 0
426 #define FUSE_BASE__INST1_SEG5 0
427
428 #define FUSE_BASE__INST2_SEG0 0
429 #define FUSE_BASE__INST2_SEG1 0
430 #define FUSE_BASE__INST2_SEG2 0
431 #define FUSE_BASE__INST2_SEG3 0
432 #define FUSE_BASE__INST2_SEG4 0
433 #define FUSE_BASE__INST2_SEG5 0
434
435 #define FUSE_BASE__INST3_SEG0 0
436 #define FUSE_BASE__INST3_SEG1 0
437 #define FUSE_BASE__INST3_SEG2 0
438 #define FUSE_BASE__INST3_SEG3 0
439 #define FUSE_BASE__INST3_SEG4 0
440 #define FUSE_BASE__INST3_SEG5 0
441
442 #define FUSE_BASE__INST4_SEG0 0
443 #define FUSE_BASE__INST4_SEG1 0
444 #define FUSE_BASE__INST4_SEG2 0
445 #define FUSE_BASE__INST4_SEG3 0
446 #define FUSE_BASE__INST4_SEG4 0
447 #define FUSE_BASE__INST4_SEG5 0
448
449 #define FUSE_BASE__INST5_SEG0 0
450 #define FUSE_BASE__INST5_SEG1 0
451 #define FUSE_BASE__INST5_SEG2 0
452 #define FUSE_BASE__INST5_SEG3 0
453 #define FUSE_BASE__INST5_SEG4 0
454 #define FUSE_BASE__INST5_SEG5 0
455
456 #define FUSE_BASE__INST6_SEG0 0
457 #define FUSE_BASE__INST6_SEG1 0
458 #define FUSE_BASE__INST6_SEG2 0
459 #define FUSE_BASE__INST6_SEG3 0
460 #define FUSE_BASE__INST6_SEG4 0
461 #define FUSE_BASE__INST6_SEG5 0
462
463 #define FUSE_BASE__INST7_SEG0 0
464 #define FUSE_BASE__INST7_SEG1 0
465 #define FUSE_BASE__INST7_SEG2 0
466 #define FUSE_BASE__INST7_SEG3 0
467 #define FUSE_BASE__INST7_SEG4 0
468 #define FUSE_BASE__INST7_SEG5 0
469
470 #define GC_BASE__INST0_SEG0 0x00002000
471 #define GC_BASE__INST0_SEG1 0x0000A000
472 #define GC_BASE__INST0_SEG2 0x00012160
473 #define GC_BASE__INST0_SEG3 0x00402C00
474 #define GC_BASE__INST0_SEG4 0
475 #define GC_BASE__INST0_SEG5 0
476
477 #define GC_BASE__INST1_SEG0 0
478 #define GC_BASE__INST1_SEG1 0
479 #define GC_BASE__INST1_SEG2 0
480 #define GC_BASE__INST1_SEG3 0
481 #define GC_BASE__INST1_SEG4 0
482 #define GC_BASE__INST1_SEG5 0
483
484 #define GC_BASE__INST2_SEG0 0
485 #define GC_BASE__INST2_SEG1 0
486 #define GC_BASE__INST2_SEG2 0
487 #define GC_BASE__INST2_SEG3 0
488 #define GC_BASE__INST2_SEG4 0
489 #define GC_BASE__INST2_SEG5 0
490
491 #define GC_BASE__INST3_SEG0 0
492 #define GC_BASE__INST3_SEG1 0
493 #define GC_BASE__INST3_SEG2 0
494 #define GC_BASE__INST3_SEG3 0
495 #define GC_BASE__INST3_SEG4 0
496 #define GC_BASE__INST3_SEG5 0
497
498 #define GC_BASE__INST4_SEG0 0
499 #define GC_BASE__INST4_SEG1 0
500 #define GC_BASE__INST4_SEG2 0
501 #define GC_BASE__INST4_SEG3 0
502 #define GC_BASE__INST4_SEG4 0
503 #define GC_BASE__INST4_SEG5 0
504
505 #define GC_BASE__INST5_SEG0 0
506 #define GC_BASE__INST5_SEG1 0
507 #define GC_BASE__INST5_SEG2 0
508 #define GC_BASE__INST5_SEG3 0
509 #define GC_BASE__INST5_SEG4 0
510 #define GC_BASE__INST5_SEG5 0
511
512 #define GC_BASE__INST6_SEG0 0
513 #define GC_BASE__INST6_SEG1 0
514 #define GC_BASE__INST6_SEG2 0
515 #define GC_BASE__INST6_SEG3 0
516 #define GC_BASE__INST6_SEG4 0
517 #define GC_BASE__INST6_SEG5 0
518
519 #define GC_BASE__INST7_SEG0 0
520 #define GC_BASE__INST7_SEG1 0
521 #define GC_BASE__INST7_SEG2 0
522 #define GC_BASE__INST7_SEG3 0
523 #define GC_BASE__INST7_SEG4 0
524 #define GC_BASE__INST7_SEG5 0
525
526 #define HDP_BASE__INST0_SEG0 0x00000F20
527 #define HDP_BASE__INST0_SEG1 0x00012520
528 #define HDP_BASE__INST0_SEG2 0x0040A400
529 #define HDP_BASE__INST0_SEG3 0
530 #define HDP_BASE__INST0_SEG4 0
531 #define HDP_BASE__INST0_SEG5 0
532
533 #define HDP_BASE__INST1_SEG0 0
534 #define HDP_BASE__INST1_SEG1 0
535 #define HDP_BASE__INST1_SEG2 0
536 #define HDP_BASE__INST1_SEG3 0
537 #define HDP_BASE__INST1_SEG4 0
538 #define HDP_BASE__INST1_SEG5 0
539
540 #define HDP_BASE__INST2_SEG0 0
541 #define HDP_BASE__INST2_SEG1 0
542 #define HDP_BASE__INST2_SEG2 0
543 #define HDP_BASE__INST2_SEG3 0
544 #define HDP_BASE__INST2_SEG4 0
545 #define HDP_BASE__INST2_SEG5 0
546
547 #define HDP_BASE__INST3_SEG0 0
548 #define HDP_BASE__INST3_SEG1 0
549 #define HDP_BASE__INST3_SEG2 0
550 #define HDP_BASE__INST3_SEG3 0
551 #define HDP_BASE__INST3_SEG4 0
552 #define HDP_BASE__INST3_SEG5 0
553
554 #define HDP_BASE__INST4_SEG0 0
555 #define HDP_BASE__INST4_SEG1 0
556 #define HDP_BASE__INST4_SEG2 0
557 #define HDP_BASE__INST4_SEG3 0
558 #define HDP_BASE__INST4_SEG4 0
559 #define HDP_BASE__INST4_SEG5 0
560
561 #define HDP_BASE__INST5_SEG0 0
562 #define HDP_BASE__INST5_SEG1 0
563 #define HDP_BASE__INST5_SEG2 0
564 #define HDP_BASE__INST5_SEG3 0
565 #define HDP_BASE__INST5_SEG4 0
566 #define HDP_BASE__INST5_SEG5 0
567
568 #define HDP_BASE__INST6_SEG0 0
569 #define HDP_BASE__INST6_SEG1 0
570 #define HDP_BASE__INST6_SEG2 0
571 #define HDP_BASE__INST6_SEG3 0
572 #define HDP_BASE__INST6_SEG4 0
573 #define HDP_BASE__INST6_SEG5 0
574
575 #define HDP_BASE__INST7_SEG0 0
576 #define HDP_BASE__INST7_SEG1 0
577 #define HDP_BASE__INST7_SEG2 0
578 #define HDP_BASE__INST7_SEG3 0
579 #define HDP_BASE__INST7_SEG4 0
580 #define HDP_BASE__INST7_SEG5 0
581
582 #define MMHUB_BASE__INST0_SEG0 0x00012440
583 #define MMHUB_BASE__INST0_SEG1 0x0001A000
584 #define MMHUB_BASE__INST0_SEG2 0x00408800
585 #define MMHUB_BASE__INST0_SEG3 0
586 #define MMHUB_BASE__INST0_SEG4 0
587 #define MMHUB_BASE__INST0_SEG5 0
588
589 #define MMHUB_BASE__INST1_SEG0 0
590 #define MMHUB_BASE__INST1_SEG1 0
591 #define MMHUB_BASE__INST1_SEG2 0
592 #define MMHUB_BASE__INST1_SEG3 0
593 #define MMHUB_BASE__INST1_SEG4 0
594 #define MMHUB_BASE__INST1_SEG5 0
595
596 #define MMHUB_BASE__INST2_SEG0 0
597 #define MMHUB_BASE__INST2_SEG1 0
598 #define MMHUB_BASE__INST2_SEG2 0
599 #define MMHUB_BASE__INST2_SEG3 0
600 #define MMHUB_BASE__INST2_SEG4 0
601 #define MMHUB_BASE__INST2_SEG5 0
602
603 #define MMHUB_BASE__INST3_SEG0 0
604 #define MMHUB_BASE__INST3_SEG1 0
605 #define MMHUB_BASE__INST3_SEG2 0
606 #define MMHUB_BASE__INST3_SEG3 0
607 #define MMHUB_BASE__INST3_SEG4 0
608 #define MMHUB_BASE__INST3_SEG5 0
609
610 #define MMHUB_BASE__INST4_SEG0 0
611 #define MMHUB_BASE__INST4_SEG1 0
612 #define MMHUB_BASE__INST4_SEG2 0
613 #define MMHUB_BASE__INST4_SEG3 0
614 #define MMHUB_BASE__INST4_SEG4 0
615 #define MMHUB_BASE__INST4_SEG5 0
616
617 #define MMHUB_BASE__INST5_SEG0 0
618 #define MMHUB_BASE__INST5_SEG1 0
619 #define MMHUB_BASE__INST5_SEG2 0
620 #define MMHUB_BASE__INST5_SEG3 0
621 #define MMHUB_BASE__INST5_SEG4 0
622 #define MMHUB_BASE__INST5_SEG5 0
623
624 #define MMHUB_BASE__INST6_SEG0 0
625 #define MMHUB_BASE__INST6_SEG1 0
626 #define MMHUB_BASE__INST6_SEG2 0
627 #define MMHUB_BASE__INST6_SEG3 0
628 #define MMHUB_BASE__INST6_SEG4 0
629 #define MMHUB_BASE__INST6_SEG5 0
630
631 #define MMHUB_BASE__INST7_SEG0 0
632 #define MMHUB_BASE__INST7_SEG1 0
633 #define MMHUB_BASE__INST7_SEG2 0
634 #define MMHUB_BASE__INST7_SEG3 0
635 #define MMHUB_BASE__INST7_SEG4 0
636 #define MMHUB_BASE__INST7_SEG5 0
637
638 #define MP0_BASE__INST0_SEG0 0x00013FE0
639 #define MP0_BASE__INST0_SEG1 0x00016000
640 #define MP0_BASE__INST0_SEG2 0x0043FC00
641 #define MP0_BASE__INST0_SEG3 0x00DC0000
642 #define MP0_BASE__INST0_SEG4 0x00E00000
643 #define MP0_BASE__INST0_SEG5 0x00E40000
644
645 #define MP0_BASE__INST1_SEG0 0
646 #define MP0_BASE__INST1_SEG1 0
647 #define MP0_BASE__INST1_SEG2 0
648 #define MP0_BASE__INST1_SEG3 0
649 #define MP0_BASE__INST1_SEG4 0
650 #define MP0_BASE__INST1_SEG5 0
651
652 #define MP0_BASE__INST2_SEG0 0
653 #define MP0_BASE__INST2_SEG1 0
654 #define MP0_BASE__INST2_SEG2 0
655 #define MP0_BASE__INST2_SEG3 0
656 #define MP0_BASE__INST2_SEG4 0
657 #define MP0_BASE__INST2_SEG5 0
658
659 #define MP0_BASE__INST3_SEG0 0
660 #define MP0_BASE__INST3_SEG1 0
661 #define MP0_BASE__INST3_SEG2 0
662 #define MP0_BASE__INST3_SEG3 0
663 #define MP0_BASE__INST3_SEG4 0
664 #define MP0_BASE__INST3_SEG5 0
665
666 #define MP0_BASE__INST4_SEG0 0
667 #define MP0_BASE__INST4_SEG1 0
668 #define MP0_BASE__INST4_SEG2 0
669 #define MP0_BASE__INST4_SEG3 0
670 #define MP0_BASE__INST4_SEG4 0
671 #define MP0_BASE__INST4_SEG5 0
672
673 #define MP0_BASE__INST5_SEG0 0
674 #define MP0_BASE__INST5_SEG1 0
675 #define MP0_BASE__INST5_SEG2 0
676 #define MP0_BASE__INST5_SEG3 0
677 #define MP0_BASE__INST5_SEG4 0
678 #define MP0_BASE__INST5_SEG5 0
679
680 #define MP0_BASE__INST6_SEG0 0
681 #define MP0_BASE__INST6_SEG1 0
682 #define MP0_BASE__INST6_SEG2 0
683 #define MP0_BASE__INST6_SEG3 0
684 #define MP0_BASE__INST6_SEG4 0
685 #define MP0_BASE__INST6_SEG5 0
686
687 #define MP0_BASE__INST7_SEG0 0
688 #define MP0_BASE__INST7_SEG1 0
689 #define MP0_BASE__INST7_SEG2 0
690 #define MP0_BASE__INST7_SEG3 0
691 #define MP0_BASE__INST7_SEG4 0
692 #define MP0_BASE__INST7_SEG5 0
693
694 #define MP1_BASE__INST0_SEG0 0x00012020
695 #define MP1_BASE__INST0_SEG1 0x00016200
696 #define MP1_BASE__INST0_SEG2 0x00400400
697 #define MP1_BASE__INST0_SEG3 0x00E80000
698 #define MP1_BASE__INST0_SEG4 0x00EC0000
699 #define MP1_BASE__INST0_SEG5 0x00F00000
700
701 #define MP1_BASE__INST1_SEG0 0
702 #define MP1_BASE__INST1_SEG1 0
703 #define MP1_BASE__INST1_SEG2 0
704 #define MP1_BASE__INST1_SEG3 0
705 #define MP1_BASE__INST1_SEG4 0
706 #define MP1_BASE__INST1_SEG5 0
707
708 #define MP1_BASE__INST2_SEG0 0
709 #define MP1_BASE__INST2_SEG1 0
710 #define MP1_BASE__INST2_SEG2 0
711 #define MP1_BASE__INST2_SEG3 0
712 #define MP1_BASE__INST2_SEG4 0
713 #define MP1_BASE__INST2_SEG5 0
714
715 #define MP1_BASE__INST3_SEG0 0
716 #define MP1_BASE__INST3_SEG1 0
717 #define MP1_BASE__INST3_SEG2 0
718 #define MP1_BASE__INST3_SEG3 0
719 #define MP1_BASE__INST3_SEG4 0
720 #define MP1_BASE__INST3_SEG5 0
721
722 #define MP1_BASE__INST4_SEG0 0
723 #define MP1_BASE__INST4_SEG1 0
724 #define MP1_BASE__INST4_SEG2 0
725 #define MP1_BASE__INST4_SEG3 0
726 #define MP1_BASE__INST4_SEG4 0
727 #define MP1_BASE__INST4_SEG5 0
728
729 #define MP1_BASE__INST5_SEG0 0
730 #define MP1_BASE__INST5_SEG1 0
731 #define MP1_BASE__INST5_SEG2 0
732 #define MP1_BASE__INST5_SEG3 0
733 #define MP1_BASE__INST5_SEG4 0
734 #define MP1_BASE__INST5_SEG5 0
735
736 #define MP1_BASE__INST6_SEG0 0
737 #define MP1_BASE__INST6_SEG1 0
738 #define MP1_BASE__INST6_SEG2 0
739 #define MP1_BASE__INST6_SEG3 0
740 #define MP1_BASE__INST6_SEG4 0
741 #define MP1_BASE__INST6_SEG5 0
742
743 #define MP1_BASE__INST7_SEG0 0
744 #define MP1_BASE__INST7_SEG1 0
745 #define MP1_BASE__INST7_SEG2 0
746 #define MP1_BASE__INST7_SEG3 0
747 #define MP1_BASE__INST7_SEG4 0
748 #define MP1_BASE__INST7_SEG5 0
749
750 #define NBIF0_BASE__INST0_SEG0 0x00000000
751 #define NBIF0_BASE__INST0_SEG1 0x00000014
752 #define NBIF0_BASE__INST0_SEG2 0x00000D20
753 #define NBIF0_BASE__INST0_SEG3 0x00010400
754 #define NBIF0_BASE__INST0_SEG4 0x00012D80
755 #define NBIF0_BASE__INST0_SEG5 0x0041B000
756
757 #define NBIF0_BASE__INST1_SEG0 0
758 #define NBIF0_BASE__INST1_SEG1 0
759 #define NBIF0_BASE__INST1_SEG2 0
760 #define NBIF0_BASE__INST1_SEG3 0
761 #define NBIF0_BASE__INST1_SEG4 0
762 #define NBIF0_BASE__INST1_SEG5 0
763
764 #define NBIF0_BASE__INST2_SEG0 0
765 #define NBIF0_BASE__INST2_SEG1 0
766 #define NBIF0_BASE__INST2_SEG2 0
767 #define NBIF0_BASE__INST2_SEG3 0
768 #define NBIF0_BASE__INST2_SEG4 0
769 #define NBIF0_BASE__INST2_SEG5 0
770
771 #define NBIF0_BASE__INST3_SEG0 0
772 #define NBIF0_BASE__INST3_SEG1 0
773 #define NBIF0_BASE__INST3_SEG2 0
774 #define NBIF0_BASE__INST3_SEG3 0
775 #define NBIF0_BASE__INST3_SEG4 0
776 #define NBIF0_BASE__INST3_SEG5 0
777
778 #define NBIF0_BASE__INST4_SEG0 0
779 #define NBIF0_BASE__INST4_SEG1 0
780 #define NBIF0_BASE__INST4_SEG2 0
781 #define NBIF0_BASE__INST4_SEG3 0
782 #define NBIF0_BASE__INST4_SEG4 0
783 #define NBIF0_BASE__INST4_SEG5 0
784
785 #define NBIF0_BASE__INST5_SEG0 0
786 #define NBIF0_BASE__INST5_SEG1 0
787 #define NBIF0_BASE__INST5_SEG2 0
788 #define NBIF0_BASE__INST5_SEG3 0
789 #define NBIF0_BASE__INST5_SEG4 0
790 #define NBIF0_BASE__INST5_SEG5 0
791
792 #define NBIF0_BASE__INST6_SEG0 0
793 #define NBIF0_BASE__INST6_SEG1 0
794 #define NBIF0_BASE__INST6_SEG2 0
795 #define NBIF0_BASE__INST6_SEG3 0
796 #define NBIF0_BASE__INST6_SEG4 0
797 #define NBIF0_BASE__INST6_SEG5 0
798
799 #define NBIF0_BASE__INST7_SEG0 0
800 #define NBIF0_BASE__INST7_SEG1 0
801 #define NBIF0_BASE__INST7_SEG2 0
802 #define NBIF0_BASE__INST7_SEG3 0
803 #define NBIF0_BASE__INST7_SEG4 0
804 #define NBIF0_BASE__INST7_SEG5 0
805
806 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
807 #define OSSSYS_BASE__INST0_SEG1 0x00012500
808 #define OSSSYS_BASE__INST0_SEG2 0x0040A000
809 #define OSSSYS_BASE__INST0_SEG3 0
810 #define OSSSYS_BASE__INST0_SEG4 0
811 #define OSSSYS_BASE__INST0_SEG5 0
812
813 #define OSSSYS_BASE__INST1_SEG0 0
814 #define OSSSYS_BASE__INST1_SEG1 0
815 #define OSSSYS_BASE__INST1_SEG2 0
816 #define OSSSYS_BASE__INST1_SEG3 0
817 #define OSSSYS_BASE__INST1_SEG4 0
818 #define OSSSYS_BASE__INST1_SEG5 0
819
820 #define OSSSYS_BASE__INST2_SEG0 0
821 #define OSSSYS_BASE__INST2_SEG1 0
822 #define OSSSYS_BASE__INST2_SEG2 0
823 #define OSSSYS_BASE__INST2_SEG3 0
824 #define OSSSYS_BASE__INST2_SEG4 0
825 #define OSSSYS_BASE__INST2_SEG5 0
826
827 #define OSSSYS_BASE__INST3_SEG0 0
828 #define OSSSYS_BASE__INST3_SEG1 0
829 #define OSSSYS_BASE__INST3_SEG2 0
830 #define OSSSYS_BASE__INST3_SEG3 0
831 #define OSSSYS_BASE__INST3_SEG4 0
832 #define OSSSYS_BASE__INST3_SEG5 0
833
834 #define OSSSYS_BASE__INST4_SEG0 0
835 #define OSSSYS_BASE__INST4_SEG1 0
836 #define OSSSYS_BASE__INST4_SEG2 0
837 #define OSSSYS_BASE__INST4_SEG3 0
838 #define OSSSYS_BASE__INST4_SEG4 0
839 #define OSSSYS_BASE__INST4_SEG5 0
840
841 #define OSSSYS_BASE__INST5_SEG0 0
842 #define OSSSYS_BASE__INST5_SEG1 0
843 #define OSSSYS_BASE__INST5_SEG2 0
844 #define OSSSYS_BASE__INST5_SEG3 0
845 #define OSSSYS_BASE__INST5_SEG4 0
846 #define OSSSYS_BASE__INST5_SEG5 0
847
848 #define OSSSYS_BASE__INST6_SEG0 0
849 #define OSSSYS_BASE__INST6_SEG1 0
850 #define OSSSYS_BASE__INST6_SEG2 0
851 #define OSSSYS_BASE__INST6_SEG3 0
852 #define OSSSYS_BASE__INST6_SEG4 0
853 #define OSSSYS_BASE__INST6_SEG5 0
854
855 #define OSSSYS_BASE__INST7_SEG0 0
856 #define OSSSYS_BASE__INST7_SEG1 0
857 #define OSSSYS_BASE__INST7_SEG2 0
858 #define OSSSYS_BASE__INST7_SEG3 0
859 #define OSSSYS_BASE__INST7_SEG4 0
860 #define OSSSYS_BASE__INST7_SEG5 0
861
862 #define PCIE0_BASE__INST0_SEG0 0x000128C0
863 #define PCIE0_BASE__INST0_SEG1 0x00411800
864 #define PCIE0_BASE__INST0_SEG2 0x04440000
865 #define PCIE0_BASE__INST0_SEG3 0
866 #define PCIE0_BASE__INST0_SEG4 0
867 #define PCIE0_BASE__INST0_SEG5 0
868
869 #define PCIE0_BASE__INST1_SEG0 0
870 #define PCIE0_BASE__INST1_SEG1 0
871 #define PCIE0_BASE__INST1_SEG2 0
872 #define PCIE0_BASE__INST1_SEG3 0
873 #define PCIE0_BASE__INST1_SEG4 0
874 #define PCIE0_BASE__INST1_SEG5 0
875
876 #define PCIE0_BASE__INST2_SEG0 0
877 #define PCIE0_BASE__INST2_SEG1 0
878 #define PCIE0_BASE__INST2_SEG2 0
879 #define PCIE0_BASE__INST2_SEG3 0
880 #define PCIE0_BASE__INST2_SEG4 0
881 #define PCIE0_BASE__INST2_SEG5 0
882
883 #define PCIE0_BASE__INST3_SEG0 0
884 #define PCIE0_BASE__INST3_SEG1 0
885 #define PCIE0_BASE__INST3_SEG2 0
886 #define PCIE0_BASE__INST3_SEG3 0
887 #define PCIE0_BASE__INST3_SEG4 0
888 #define PCIE0_BASE__INST3_SEG5 0
889
890 #define PCIE0_BASE__INST4_SEG0 0
891 #define PCIE0_BASE__INST4_SEG1 0
892 #define PCIE0_BASE__INST4_SEG2 0
893 #define PCIE0_BASE__INST4_SEG3 0
894 #define PCIE0_BASE__INST4_SEG4 0
895 #define PCIE0_BASE__INST4_SEG5 0
896
897 #define PCIE0_BASE__INST5_SEG0 0
898 #define PCIE0_BASE__INST5_SEG1 0
899 #define PCIE0_BASE__INST5_SEG2 0
900 #define PCIE0_BASE__INST5_SEG3 0
901 #define PCIE0_BASE__INST5_SEG4 0
902 #define PCIE0_BASE__INST5_SEG5 0
903
904 #define PCIE0_BASE__INST6_SEG0 0
905 #define PCIE0_BASE__INST6_SEG1 0
906 #define PCIE0_BASE__INST6_SEG2 0
907 #define PCIE0_BASE__INST6_SEG3 0
908 #define PCIE0_BASE__INST6_SEG4 0
909 #define PCIE0_BASE__INST6_SEG5 0
910
911 #define PCIE0_BASE__INST7_SEG0 0
912 #define PCIE0_BASE__INST7_SEG1 0
913 #define PCIE0_BASE__INST7_SEG2 0
914 #define PCIE0_BASE__INST7_SEG3 0
915 #define PCIE0_BASE__INST7_SEG4 0
916 #define PCIE0_BASE__INST7_SEG5 0
917
918 #define SDMA0_BASE__INST0_SEG0 0x00001260
919 #define SDMA0_BASE__INST0_SEG1 0x00012540
920 #define SDMA0_BASE__INST0_SEG2 0x0040A800
921 #define SDMA0_BASE__INST0_SEG3 0
922 #define SDMA0_BASE__INST0_SEG4 0
923 #define SDMA0_BASE__INST0_SEG5 0
924
925 #define SDMA0_BASE__INST1_SEG0 0
926 #define SDMA0_BASE__INST1_SEG1 0
927 #define SDMA0_BASE__INST1_SEG2 0
928 #define SDMA0_BASE__INST1_SEG3 0
929 #define SDMA0_BASE__INST1_SEG4 0
930 #define SDMA0_BASE__INST1_SEG5 0
931
932 #define SDMA0_BASE__INST2_SEG0 0
933 #define SDMA0_BASE__INST2_SEG1 0
934 #define SDMA0_BASE__INST2_SEG2 0
935 #define SDMA0_BASE__INST2_SEG3 0
936 #define SDMA0_BASE__INST2_SEG4 0
937 #define SDMA0_BASE__INST2_SEG5 0
938
939 #define SDMA0_BASE__INST3_SEG0 0
940 #define SDMA0_BASE__INST3_SEG1 0
941 #define SDMA0_BASE__INST3_SEG2 0
942 #define SDMA0_BASE__INST3_SEG3 0
943 #define SDMA0_BASE__INST3_SEG4 0
944 #define SDMA0_BASE__INST3_SEG5 0
945
946 #define SDMA0_BASE__INST4_SEG0 0
947 #define SDMA0_BASE__INST4_SEG1 0
948 #define SDMA0_BASE__INST4_SEG2 0
949 #define SDMA0_BASE__INST4_SEG3 0
950 #define SDMA0_BASE__INST4_SEG4 0
951 #define SDMA0_BASE__INST4_SEG5 0
952
953 #define SDMA0_BASE__INST5_SEG0 0
954 #define SDMA0_BASE__INST5_SEG1 0
955 #define SDMA0_BASE__INST5_SEG2 0
956 #define SDMA0_BASE__INST5_SEG3 0
957 #define SDMA0_BASE__INST5_SEG4 0
958 #define SDMA0_BASE__INST5_SEG5 0
959
960 #define SDMA0_BASE__INST6_SEG0 0
961 #define SDMA0_BASE__INST6_SEG1 0
962 #define SDMA0_BASE__INST6_SEG2 0
963 #define SDMA0_BASE__INST6_SEG3 0
964 #define SDMA0_BASE__INST6_SEG4 0
965 #define SDMA0_BASE__INST6_SEG5 0
966
967 #define SDMA1_BASE__INST0_SEG0 0x00001860
968 #define SDMA1_BASE__INST0_SEG1 0x00012560
969 #define SDMA1_BASE__INST0_SEG2 0x0040AC00
970 #define SDMA1_BASE__INST0_SEG3 0
971 #define SDMA1_BASE__INST0_SEG4 0
972 #define SDMA1_BASE__INST0_SEG5 0
973
974 #define SDMA1_BASE__INST1_SEG0 0
975 #define SDMA1_BASE__INST1_SEG1 0
976 #define SDMA1_BASE__INST1_SEG2 0
977 #define SDMA1_BASE__INST1_SEG3 0
978 #define SDMA1_BASE__INST1_SEG4 0
979 #define SDMA1_BASE__INST1_SEG5 0
980
981 #define SDMA1_BASE__INST2_SEG0 0
982 #define SDMA1_BASE__INST2_SEG1 0
983 #define SDMA1_BASE__INST2_SEG2 0
984 #define SDMA1_BASE__INST2_SEG3 0
985 #define SDMA1_BASE__INST2_SEG4 0
986 #define SDMA1_BASE__INST2_SEG5 0
987
988 #define SDMA1_BASE__INST3_SEG0 0
989 #define SDMA1_BASE__INST3_SEG1 0
990 #define SDMA1_BASE__INST3_SEG2 0
991 #define SDMA1_BASE__INST3_SEG3 0
992 #define SDMA1_BASE__INST3_SEG4 0
993 #define SDMA1_BASE__INST3_SEG5 0
994
995 #define SDMA1_BASE__INST4_SEG0 0
996 #define SDMA1_BASE__INST4_SEG1 0
997 #define SDMA1_BASE__INST4_SEG2 0
998 #define SDMA1_BASE__INST4_SEG3 0
999 #define SDMA1_BASE__INST4_SEG4 0
1000 #define SDMA1_BASE__INST4_SEG5 0
1001
1002 #define SDMA1_BASE__INST5_SEG0 0
1003 #define SDMA1_BASE__INST5_SEG1 0
1004 #define SDMA1_BASE__INST5_SEG2 0
1005 #define SDMA1_BASE__INST5_SEG3 0
1006 #define SDMA1_BASE__INST5_SEG4 0
1007 #define SDMA1_BASE__INST5_SEG5 0
1008
1009
1010 #define SDMA1_BASE__INST6_SEG0 0
1011 #define SDMA1_BASE__INST6_SEG1 0
1012 #define SDMA1_BASE__INST6_SEG2 0
1013 #define SDMA1_BASE__INST6_SEG3 0
1014 #define SDMA1_BASE__INST6_SEG4 0
1015 #define SDMA1_BASE__INST6_SEG5 0
1016
1017
1018 #define SDMA2_BASE__INST0_SEG0 0x00013760
1019 #define SDMA2_BASE__INST0_SEG1 0x0001E000
1020 #define SDMA2_BASE__INST0_SEG2 0x0042EC00
1021 #define SDMA2_BASE__INST0_SEG3 0
1022 #define SDMA2_BASE__INST0_SEG4 0
1023 #define SDMA2_BASE__INST0_SEG5 0
1024
1025
1026 #define SDMA2_BASE__INST1_SEG0 0
1027 #define SDMA2_BASE__INST1_SEG1 0
1028 #define SDMA2_BASE__INST1_SEG2 0
1029 #define SDMA2_BASE__INST1_SEG3 0
1030 #define SDMA2_BASE__INST1_SEG4 0
1031 #define SDMA2_BASE__INST1_SEG5 0
1032
1033 #define SDMA2_BASE__INST2_SEG0 0
1034 #define SDMA2_BASE__INST2_SEG1 0
1035 #define SDMA2_BASE__INST2_SEG2 0
1036 #define SDMA2_BASE__INST2_SEG3 0
1037 #define SDMA2_BASE__INST2_SEG4 0
1038 #define SDMA2_BASE__INST2_SEG5 0
1039
1040 #define SDMA2_BASE__INST3_SEG0 0
1041 #define SDMA2_BASE__INST3_SEG1 0
1042 #define SDMA2_BASE__INST3_SEG2 0
1043 #define SDMA2_BASE__INST3_SEG3 0
1044 #define SDMA2_BASE__INST3_SEG4 0
1045 #define SDMA2_BASE__INST3_SEG5 0
1046
1047 #define SDMA2_BASE__INST4_SEG0 0
1048 #define SDMA2_BASE__INST4_SEG1 0
1049 #define SDMA2_BASE__INST4_SEG2 0
1050 #define SDMA2_BASE__INST4_SEG3 0
1051 #define SDMA2_BASE__INST4_SEG4 0
1052 #define SDMA2_BASE__INST4_SEG5 0
1053
1054 #define SDMA2_BASE__INST5_SEG0 0
1055 #define SDMA2_BASE__INST5_SEG1 0
1056 #define SDMA2_BASE__INST5_SEG2 0
1057 #define SDMA2_BASE__INST5_SEG3 0
1058 #define SDMA2_BASE__INST5_SEG4 0
1059 #define SDMA2_BASE__INST5_SEG5 0
1060
1061 #define SDMA2_BASE__INST6_SEG0 0
1062 #define SDMA2_BASE__INST6_SEG1 0
1063 #define SDMA2_BASE__INST6_SEG2 0
1064 #define SDMA2_BASE__INST6_SEG3 0
1065 #define SDMA2_BASE__INST6_SEG4 0
1066 #define SDMA2_BASE__INST6_SEG5 0
1067
1068 #define SDMA3_BASE__INST0_SEG0 0x00013780
1069 #define SDMA3_BASE__INST0_SEG1 0x0001E400
1070 #define SDMA3_BASE__INST0_SEG2 0x0042F000
1071 #define SDMA3_BASE__INST0_SEG3 0
1072 #define SDMA3_BASE__INST0_SEG4 0
1073 #define SDMA3_BASE__INST0_SEG5 0
1074
1075 #define SDMA3_BASE__INST1_SEG0 0
1076 #define SDMA3_BASE__INST1_SEG1 0
1077 #define SDMA3_BASE__INST1_SEG2 0
1078 #define SDMA3_BASE__INST1_SEG3 0
1079 #define SDMA3_BASE__INST1_SEG4 0
1080 #define SDMA3_BASE__INST1_SEG5 0
1081
1082 #define SDMA3_BASE__INST2_SEG0 0
1083 #define SDMA3_BASE__INST2_SEG1 0
1084 #define SDMA3_BASE__INST2_SEG2 0
1085 #define SDMA3_BASE__INST2_SEG3 0
1086 #define SDMA3_BASE__INST2_SEG4 0
1087 #define SDMA3_BASE__INST2_SEG5 0
1088
1089 #define SDMA3_BASE__INST3_SEG0 0
1090 #define SDMA3_BASE__INST3_SEG1 0
1091 #define SDMA3_BASE__INST3_SEG2 0
1092 #define SDMA3_BASE__INST3_SEG3 0
1093 #define SDMA3_BASE__INST3_SEG4 0
1094 #define SDMA3_BASE__INST3_SEG5 0
1095
1096 #define SDMA3_BASE__INST4_SEG0 0
1097 #define SDMA3_BASE__INST4_SEG1 0
1098 #define SDMA3_BASE__INST4_SEG2 0
1099 #define SDMA3_BASE__INST4_SEG3 0
1100 #define SDMA3_BASE__INST4_SEG4 0
1101 #define SDMA3_BASE__INST4_SEG5 0
1102
1103 #define SDMA3_BASE__INST5_SEG0 0
1104 #define SDMA3_BASE__INST5_SEG1 0
1105 #define SDMA3_BASE__INST5_SEG2 0
1106 #define SDMA3_BASE__INST5_SEG3 0
1107 #define SDMA3_BASE__INST5_SEG4 0
1108 #define SDMA3_BASE__INST5_SEG5 0
1109
1110 #define SDMA3_BASE__INST6_SEG0 0
1111 #define SDMA3_BASE__INST6_SEG1 0
1112 #define SDMA3_BASE__INST6_SEG2 0
1113 #define SDMA3_BASE__INST6_SEG3 0
1114 #define SDMA3_BASE__INST6_SEG4 0
1115 #define SDMA3_BASE__INST6_SEG5 0
1116
1117 #define SDMA4_BASE__INST0_SEG0 0x000137A0
1118 #define SDMA4_BASE__INST0_SEG1 0x0001E800
1119 #define SDMA4_BASE__INST0_SEG2 0x0042F400
1120 #define SDMA4_BASE__INST0_SEG3 0
1121 #define SDMA4_BASE__INST0_SEG4 0
1122 #define SDMA4_BASE__INST0_SEG5 0
1123
1124 #define SDMA4_BASE__INST1_SEG0 0
1125 #define SDMA4_BASE__INST1_SEG1 0
1126 #define SDMA4_BASE__INST1_SEG2 0
1127 #define SDMA4_BASE__INST1_SEG3 0
1128 #define SDMA4_BASE__INST1_SEG4 0
1129 #define SDMA4_BASE__INST1_SEG5 0
1130
1131 #define SDMA4_BASE__INST2_SEG0 0
1132 #define SDMA4_BASE__INST2_SEG1 0
1133 #define SDMA4_BASE__INST2_SEG2 0
1134 #define SDMA4_BASE__INST2_SEG3 0
1135 #define SDMA4_BASE__INST2_SEG4 0
1136 #define SDMA4_BASE__INST2_SEG5 0
1137
1138 #define SDMA4_BASE__INST3_SEG0 0
1139 #define SDMA4_BASE__INST3_SEG1 0
1140 #define SDMA4_BASE__INST3_SEG2 0
1141 #define SDMA4_BASE__INST3_SEG3 0
1142 #define SDMA4_BASE__INST3_SEG4 0
1143 #define SDMA4_BASE__INST3_SEG5 0
1144
1145 #define SDMA4_BASE__INST4_SEG0 0
1146 #define SDMA4_BASE__INST4_SEG1 0
1147 #define SDMA4_BASE__INST4_SEG2 0
1148 #define SDMA4_BASE__INST4_SEG3 0
1149 #define SDMA4_BASE__INST4_SEG4 0
1150 #define SDMA4_BASE__INST4_SEG5 0
1151
1152 #define SDMA4_BASE__INST5_SEG0 0
1153 #define SDMA4_BASE__INST5_SEG1 0
1154 #define SDMA4_BASE__INST5_SEG2 0
1155 #define SDMA4_BASE__INST5_SEG3 0
1156 #define SDMA4_BASE__INST5_SEG4 0
1157 #define SDMA4_BASE__INST5_SEG5 0
1158
1159 #define SDMA4_BASE__INST6_SEG0 0
1160 #define SDMA4_BASE__INST6_SEG1 0
1161 #define SDMA4_BASE__INST6_SEG2 0
1162 #define SDMA4_BASE__INST6_SEG3 0
1163 #define SDMA4_BASE__INST6_SEG4 0
1164 #define SDMA4_BASE__INST6_SEG5 0
1165
1166 #define SDMA5_BASE__INST0_SEG0 0x000137C0
1167 #define SDMA5_BASE__INST0_SEG1 0x0001EC00
1168 #define SDMA5_BASE__INST0_SEG2 0x0042F800
1169 #define SDMA5_BASE__INST0_SEG3 0
1170 #define SDMA5_BASE__INST0_SEG4 0
1171 #define SDMA5_BASE__INST0_SEG5 0
1172
1173 #define SDMA5_BASE__INST1_SEG0 0
1174 #define SDMA5_BASE__INST1_SEG1 0
1175 #define SDMA5_BASE__INST1_SEG2 0
1176 #define SDMA5_BASE__INST1_SEG3 0
1177 #define SDMA5_BASE__INST1_SEG4 0
1178 #define SDMA5_BASE__INST1_SEG5 0
1179
1180 #define SDMA5_BASE__INST2_SEG0 0
1181 #define SDMA5_BASE__INST2_SEG1 0
1182 #define SDMA5_BASE__INST2_SEG2 0
1183 #define SDMA5_BASE__INST2_SEG3 0
1184 #define SDMA5_BASE__INST2_SEG4 0
1185 #define SDMA5_BASE__INST2_SEG5 0
1186
1187 #define SDMA5_BASE__INST3_SEG0 0
1188 #define SDMA5_BASE__INST3_SEG1 0
1189 #define SDMA5_BASE__INST3_SEG2 0
1190 #define SDMA5_BASE__INST3_SEG3 0
1191 #define SDMA5_BASE__INST3_SEG4 0
1192 #define SDMA5_BASE__INST3_SEG5 0
1193
1194 #define SDMA5_BASE__INST4_SEG0 0
1195 #define SDMA5_BASE__INST4_SEG1 0
1196 #define SDMA5_BASE__INST4_SEG2 0
1197 #define SDMA5_BASE__INST4_SEG3 0
1198 #define SDMA5_BASE__INST4_SEG4 0
1199 #define SDMA5_BASE__INST4_SEG5 0
1200
1201 #define SDMA5_BASE__INST5_SEG0 0
1202 #define SDMA5_BASE__INST5_SEG1 0
1203 #define SDMA5_BASE__INST5_SEG2 0
1204 #define SDMA5_BASE__INST5_SEG3 0
1205 #define SDMA5_BASE__INST5_SEG4 0
1206 #define SDMA5_BASE__INST5_SEG5 0
1207
1208 #define SDMA5_BASE__INST6_SEG0 0
1209 #define SDMA5_BASE__INST6_SEG1 0
1210 #define SDMA5_BASE__INST6_SEG2 0
1211 #define SDMA5_BASE__INST6_SEG3 0
1212 #define SDMA5_BASE__INST6_SEG4 0
1213 #define SDMA5_BASE__INST6_SEG5 0
1214
1215 #define SDMA6_BASE__INST0_SEG0 0x000137E0
1216 #define SDMA6_BASE__INST0_SEG1 0x0001F000
1217 #define SDMA6_BASE__INST0_SEG2 0x0042FC00
1218 #define SDMA6_BASE__INST0_SEG3 0
1219 #define SDMA6_BASE__INST0_SEG4 0
1220 #define SDMA6_BASE__INST0_SEG5 0
1221
1222 #define SDMA6_BASE__INST1_SEG0 0
1223 #define SDMA6_BASE__INST1_SEG1 0
1224 #define SDMA6_BASE__INST1_SEG2 0
1225 #define SDMA6_BASE__INST1_SEG3 0
1226 #define SDMA6_BASE__INST1_SEG4 0
1227 #define SDMA6_BASE__INST1_SEG5 0
1228
1229 #define SDMA6_BASE__INST2_SEG0 0
1230 #define SDMA6_BASE__INST2_SEG1 0
1231 #define SDMA6_BASE__INST2_SEG2 0
1232 #define SDMA6_BASE__INST2_SEG3 0
1233 #define SDMA6_BASE__INST2_SEG4 0
1234 #define SDMA6_BASE__INST2_SEG5 0
1235
1236 #define SDMA6_BASE__INST3_SEG0 0
1237 #define SDMA6_BASE__INST3_SEG1 0
1238 #define SDMA6_BASE__INST3_SEG2 0
1239 #define SDMA6_BASE__INST3_SEG3 0
1240 #define SDMA6_BASE__INST3_SEG4 0
1241 #define SDMA6_BASE__INST3_SEG5 0
1242
1243 #define SDMA6_BASE__INST4_SEG0 0
1244 #define SDMA6_BASE__INST4_SEG1 0
1245 #define SDMA6_BASE__INST4_SEG2 0
1246 #define SDMA6_BASE__INST4_SEG3 0
1247 #define SDMA6_BASE__INST4_SEG4 0
1248 #define SDMA6_BASE__INST4_SEG5 0
1249
1250 #define SDMA6_BASE__INST5_SEG0 0
1251 #define SDMA6_BASE__INST5_SEG1 0
1252 #define SDMA6_BASE__INST5_SEG2 0
1253 #define SDMA6_BASE__INST5_SEG3 0
1254 #define SDMA6_BASE__INST5_SEG4 0
1255 #define SDMA6_BASE__INST5_SEG5 0
1256
1257 #define SDMA6_BASE__INST6_SEG0 0
1258 #define SDMA6_BASE__INST6_SEG1 0
1259 #define SDMA6_BASE__INST6_SEG2 0
1260 #define SDMA6_BASE__INST6_SEG3 0
1261 #define SDMA6_BASE__INST6_SEG4 0
1262 #define SDMA6_BASE__INST6_SEG5 0
1263
1264 #define SDMA7_BASE__INST0_SEG0 0x00013800
1265 #define SDMA7_BASE__INST0_SEG1 0x0001F400
1266 #define SDMA7_BASE__INST0_SEG2 0x00430000
1267 #define SDMA7_BASE__INST0_SEG3 0
1268 #define SDMA7_BASE__INST0_SEG4 0
1269 #define SDMA7_BASE__INST0_SEG5 0
1270
1271 #define SDMA7_BASE__INST1_SEG0 0
1272 #define SDMA7_BASE__INST1_SEG1 0
1273 #define SDMA7_BASE__INST1_SEG2 0
1274 #define SDMA7_BASE__INST1_SEG3 0
1275 #define SDMA7_BASE__INST1_SEG4 0
1276 #define SDMA7_BASE__INST1_SEG5 0
1277
1278 #define SDMA7_BASE__INST2_SEG0 0
1279 #define SDMA7_BASE__INST2_SEG1 0
1280 #define SDMA7_BASE__INST2_SEG2 0
1281 #define SDMA7_BASE__INST2_SEG3 0
1282 #define SDMA7_BASE__INST2_SEG4 0
1283 #define SDMA7_BASE__INST2_SEG5 0
1284
1285 #define SDMA7_BASE__INST3_SEG0 0
1286 #define SDMA7_BASE__INST3_SEG1 0
1287 #define SDMA7_BASE__INST3_SEG2 0
1288 #define SDMA7_BASE__INST3_SEG3 0
1289 #define SDMA7_BASE__INST3_SEG4 0
1290 #define SDMA7_BASE__INST3_SEG5 0
1291
1292 #define SDMA7_BASE__INST4_SEG0 0
1293 #define SDMA7_BASE__INST4_SEG1 0
1294 #define SDMA7_BASE__INST4_SEG2 0
1295 #define SDMA7_BASE__INST4_SEG3 0
1296 #define SDMA7_BASE__INST4_SEG4 0
1297 #define SDMA7_BASE__INST4_SEG5 0
1298
1299 #define SDMA7_BASE__INST5_SEG0 0
1300 #define SDMA7_BASE__INST5_SEG1 0
1301 #define SDMA7_BASE__INST5_SEG2 0
1302 #define SDMA7_BASE__INST5_SEG3 0
1303 #define SDMA7_BASE__INST5_SEG4 0
1304 #define SDMA7_BASE__INST5_SEG5 0
1305
1306 #define SDMA7_BASE__INST6_SEG0 0
1307 #define SDMA7_BASE__INST6_SEG1 0
1308 #define SDMA7_BASE__INST6_SEG2 0
1309 #define SDMA7_BASE__INST6_SEG3 0
1310 #define SDMA7_BASE__INST6_SEG4 0
1311 #define SDMA7_BASE__INST6_SEG5 0
1312
1313 #define SMUIO_BASE__INST0_SEG0 0x00012080
1314 #define SMUIO_BASE__INST0_SEG1 0x00016800
1315 #define SMUIO_BASE__INST0_SEG2 0x00016A00
1316 #define SMUIO_BASE__INST0_SEG3 0x00401000
1317 #define SMUIO_BASE__INST0_SEG4 0x00440000
1318 #define SMUIO_BASE__INST0_SEG5 0
1319
1320 #define SMUIO_BASE__INST1_SEG0 0
1321 #define SMUIO_BASE__INST1_SEG1 0
1322 #define SMUIO_BASE__INST1_SEG2 0
1323 #define SMUIO_BASE__INST1_SEG3 0
1324 #define SMUIO_BASE__INST1_SEG4 0
1325 #define SMUIO_BASE__INST1_SEG5 0
1326
1327 #define SMUIO_BASE__INST2_SEG0 0
1328 #define SMUIO_BASE__INST2_SEG1 0
1329 #define SMUIO_BASE__INST2_SEG2 0
1330 #define SMUIO_BASE__INST2_SEG3 0
1331 #define SMUIO_BASE__INST2_SEG4 0
1332 #define SMUIO_BASE__INST2_SEG5 0
1333
1334 #define SMUIO_BASE__INST3_SEG0 0
1335 #define SMUIO_BASE__INST3_SEG1 0
1336 #define SMUIO_BASE__INST3_SEG2 0
1337 #define SMUIO_BASE__INST3_SEG3 0
1338 #define SMUIO_BASE__INST3_SEG4 0
1339 #define SMUIO_BASE__INST3_SEG5 0
1340
1341 #define SMUIO_BASE__INST4_SEG0 0
1342 #define SMUIO_BASE__INST4_SEG1 0
1343 #define SMUIO_BASE__INST4_SEG2 0
1344 #define SMUIO_BASE__INST4_SEG3 0
1345 #define SMUIO_BASE__INST4_SEG4 0
1346 #define SMUIO_BASE__INST4_SEG5 0
1347
1348 #define SMUIO_BASE__INST5_SEG0 0
1349 #define SMUIO_BASE__INST5_SEG1 0
1350 #define SMUIO_BASE__INST5_SEG2 0
1351 #define SMUIO_BASE__INST5_SEG3 0
1352 #define SMUIO_BASE__INST5_SEG4 0
1353 #define SMUIO_BASE__INST5_SEG5 0
1354
1355 #define SMUIO_BASE__INST6_SEG0 0
1356 #define SMUIO_BASE__INST6_SEG1 0
1357 #define SMUIO_BASE__INST6_SEG2 0
1358 #define SMUIO_BASE__INST6_SEG3 0
1359 #define SMUIO_BASE__INST6_SEG4 0
1360 #define SMUIO_BASE__INST6_SEG5 0
1361
1362 #define SMUIO_BASE__INST7_SEG0 0
1363 #define SMUIO_BASE__INST7_SEG1 0
1364 #define SMUIO_BASE__INST7_SEG2 0
1365 #define SMUIO_BASE__INST7_SEG3 0
1366 #define SMUIO_BASE__INST7_SEG4 0
1367 #define SMUIO_BASE__INST7_SEG5 0
1368
1369 #define THM_BASE__INST0_SEG0 0x00012060
1370 #define THM_BASE__INST0_SEG1 0x00016600
1371 #define THM_BASE__INST0_SEG2 0x00400C00
1372 #define THM_BASE__INST0_SEG3 0
1373 #define THM_BASE__INST0_SEG4 0
1374 #define THM_BASE__INST0_SEG5 0
1375
1376 #define THM_BASE__INST1_SEG0 0
1377 #define THM_BASE__INST1_SEG1 0
1378 #define THM_BASE__INST1_SEG2 0
1379 #define THM_BASE__INST1_SEG3 0
1380 #define THM_BASE__INST1_SEG4 0
1381 #define THM_BASE__INST1_SEG5 0
1382
1383 #define THM_BASE__INST2_SEG0 0
1384 #define THM_BASE__INST2_SEG1 0
1385 #define THM_BASE__INST2_SEG2 0
1386 #define THM_BASE__INST2_SEG3 0
1387 #define THM_BASE__INST2_SEG4 0
1388 #define THM_BASE__INST2_SEG5 0
1389
1390 #define THM_BASE__INST3_SEG0 0
1391 #define THM_BASE__INST3_SEG1 0
1392 #define THM_BASE__INST3_SEG2 0
1393 #define THM_BASE__INST3_SEG3 0
1394 #define THM_BASE__INST3_SEG4 0
1395 #define THM_BASE__INST3_SEG5 0
1396
1397 #define THM_BASE__INST4_SEG0 0
1398 #define THM_BASE__INST4_SEG1 0
1399 #define THM_BASE__INST4_SEG2 0
1400 #define THM_BASE__INST4_SEG3 0
1401 #define THM_BASE__INST4_SEG4 0
1402 #define THM_BASE__INST4_SEG5 0
1403
1404 #define THM_BASE__INST5_SEG0 0
1405 #define THM_BASE__INST5_SEG1 0
1406 #define THM_BASE__INST5_SEG2 0
1407 #define THM_BASE__INST5_SEG3 0
1408 #define THM_BASE__INST5_SEG4 0
1409 #define THM_BASE__INST5_SEG5 0
1410
1411 #define THM_BASE__INST6_SEG0 0
1412 #define THM_BASE__INST6_SEG1 0
1413 #define THM_BASE__INST6_SEG2 0
1414 #define THM_BASE__INST6_SEG3 0
1415 #define THM_BASE__INST6_SEG4 0
1416 #define THM_BASE__INST6_SEG5 0
1417
1418 #define THM_BASE__INST7_SEG0 0
1419 #define THM_BASE__INST7_SEG1 0
1420 #define THM_BASE__INST7_SEG2 0
1421 #define THM_BASE__INST7_SEG3 0
1422 #define THM_BASE__INST7_SEG4 0
1423 #define THM_BASE__INST7_SEG5 0
1424
1425 #define UMC_BASE__INST0_SEG0 0x000132C0
1426 #define UMC_BASE__INST0_SEG1 0x00014000
1427 #define UMC_BASE__INST0_SEG2 0x00425800
1428 #define UMC_BASE__INST0_SEG3 0
1429 #define UMC_BASE__INST0_SEG4 0
1430 #define UMC_BASE__INST0_SEG5 0
1431
1432 #define UMC_BASE__INST1_SEG0 0x000132E0
1433 #define UMC_BASE__INST1_SEG1 0x00054000
1434 #define UMC_BASE__INST1_SEG2 0x00425C00
1435 #define UMC_BASE__INST1_SEG3 0
1436 #define UMC_BASE__INST1_SEG4 0
1437 #define UMC_BASE__INST1_SEG5 0
1438
1439 #define UMC_BASE__INST2_SEG0 0x00013300
1440 #define UMC_BASE__INST2_SEG1 0x00094000
1441 #define UMC_BASE__INST2_SEG2 0x00426000
1442 #define UMC_BASE__INST2_SEG3 0
1443 #define UMC_BASE__INST2_SEG4 0
1444 #define UMC_BASE__INST2_SEG5 0
1445
1446 #define UMC_BASE__INST3_SEG0 0x00013320
1447 #define UMC_BASE__INST3_SEG1 0x000D4000
1448 #define UMC_BASE__INST3_SEG2 0x00426400
1449 #define UMC_BASE__INST3_SEG3 0
1450 #define UMC_BASE__INST3_SEG4 0
1451 #define UMC_BASE__INST3_SEG5 0
1452
1453 #define UMC_BASE__INST4_SEG0 0x00013340
1454 #define UMC_BASE__INST4_SEG1 0x00114000
1455 #define UMC_BASE__INST4_SEG2 0x00426800
1456 #define UMC_BASE__INST4_SEG3 0
1457 #define UMC_BASE__INST4_SEG4 0
1458 #define UMC_BASE__INST4_SEG5 0
1459
1460 #define UMC_BASE__INST5_SEG0 0x00013360
1461 #define UMC_BASE__INST5_SEG1 0x00154000
1462 #define UMC_BASE__INST5_SEG2 0x00426C00
1463 #define UMC_BASE__INST5_SEG3 0
1464 #define UMC_BASE__INST5_SEG4 0
1465 #define UMC_BASE__INST5_SEG5 0
1466
1467 #define UMC_BASE__INST6_SEG0 0x00013380
1468 #define UMC_BASE__INST6_SEG1 0x00194000
1469 #define UMC_BASE__INST6_SEG2 0x00427000
1470 #define UMC_BASE__INST6_SEG3 0
1471 #define UMC_BASE__INST6_SEG4 0
1472 #define UMC_BASE__INST6_SEG5 0
1473
1474 #define UMC_BASE__INST7_SEG0 0x000133A0
1475 #define UMC_BASE__INST7_SEG1 0x001D4000
1476 #define UMC_BASE__INST7_SEG2 0x00427400
1477 #define UMC_BASE__INST7_SEG3 0
1478 #define UMC_BASE__INST7_SEG4 0
1479 #define UMC_BASE__INST7_SEG5 0
1480
1481 #define UVD_BASE__INST0_SEG0 0x00007800
1482 #define UVD_BASE__INST0_SEG1 0x00007E00
1483 #define UVD_BASE__INST0_SEG2 0x00012180
1484 #define UVD_BASE__INST0_SEG3 0x00403000
1485 #define UVD_BASE__INST0_SEG4 0
1486 #define UVD_BASE__INST0_SEG5 0
1487
1488 #define UVD_BASE__INST1_SEG0 0x00007A00
1489 #define UVD_BASE__INST1_SEG1 0x00009000
1490 #define UVD_BASE__INST1_SEG2 0x000136E0
1491 #define UVD_BASE__INST1_SEG3 0x0042DC00
1492 #define UVD_BASE__INST1_SEG4 0
1493 #define UVD_BASE__INST1_SEG5 0
1494
1495 #define UVD_BASE__INST2_SEG0 0
1496 #define UVD_BASE__INST2_SEG1 0
1497 #define UVD_BASE__INST2_SEG2 0
1498 #define UVD_BASE__INST2_SEG3 0
1499 #define UVD_BASE__INST2_SEG4 0
1500 #define UVD_BASE__INST2_SEG5 0
1501
1502 #define UVD_BASE__INST3_SEG0 0
1503 #define UVD_BASE__INST3_SEG1 0
1504 #define UVD_BASE__INST3_SEG2 0
1505 #define UVD_BASE__INST3_SEG3 0
1506 #define UVD_BASE__INST3_SEG4 0
1507 #define UVD_BASE__INST3_SEG5 0
1508
1509 #define UVD_BASE__INST4_SEG0 0
1510 #define UVD_BASE__INST4_SEG1 0
1511 #define UVD_BASE__INST4_SEG2 0
1512 #define UVD_BASE__INST4_SEG3 0
1513 #define UVD_BASE__INST4_SEG4 0
1514 #define UVD_BASE__INST4_SEG5 0
1515
1516 #define UVD_BASE__INST5_SEG0 0
1517 #define UVD_BASE__INST5_SEG1 0
1518 #define UVD_BASE__INST5_SEG2 0
1519 #define UVD_BASE__INST5_SEG3 0
1520 #define UVD_BASE__INST5_SEG4 0
1521 #define UVD_BASE__INST5_SEG5 0
1522
1523 #define UVD_BASE__INST6_SEG0 0
1524 #define UVD_BASE__INST6_SEG1 0
1525 #define UVD_BASE__INST6_SEG2 0
1526 #define UVD_BASE__INST6_SEG3 0
1527 #define UVD_BASE__INST6_SEG4 0
1528 #define UVD_BASE__INST6_SEG5 0
1529
1530 #define UVD_BASE__INST7_SEG0 0
1531 #define UVD_BASE__INST7_SEG1 0
1532 #define UVD_BASE__INST7_SEG2 0
1533 #define UVD_BASE__INST7_SEG3 0
1534 #define UVD_BASE__INST7_SEG4 0
1535 #define UVD_BASE__INST7_SEG5 0
1536
1537 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0
1538 #define DBGU_IO_BASE__INST0_SEG1 0x000125A0
1539 #define DBGU_IO_BASE__INST0_SEG2 0x0040B400
1540 #define DBGU_IO_BASE__INST0_SEG3 0
1541 #define DBGU_IO_BASE__INST0_SEG4 0
1542 #define DBGU_IO_BASE__INST0_SEG5 0
1543
1544 #define DBGU_IO_BASE__INST1_SEG0 0
1545 #define DBGU_IO_BASE__INST1_SEG1 0
1546 #define DBGU_IO_BASE__INST1_SEG2 0
1547 #define DBGU_IO_BASE__INST1_SEG3 0
1548 #define DBGU_IO_BASE__INST1_SEG4 0
1549 #define DBGU_IO_BASE__INST1_SEG5 0
1550
1551 #define DBGU_IO_BASE__INST2_SEG0 0
1552 #define DBGU_IO_BASE__INST2_SEG1 0
1553 #define DBGU_IO_BASE__INST2_SEG2 0
1554 #define DBGU_IO_BASE__INST2_SEG3 0
1555 #define DBGU_IO_BASE__INST2_SEG4 0
1556 #define DBGU_IO_BASE__INST2_SEG5 0
1557
1558 #define DBGU_IO_BASE__INST3_SEG0 0
1559 #define DBGU_IO_BASE__INST3_SEG1 0
1560 #define DBGU_IO_BASE__INST3_SEG2 0
1561 #define DBGU_IO_BASE__INST3_SEG3 0
1562 #define DBGU_IO_BASE__INST3_SEG4 0
1563 #define DBGU_IO_BASE__INST3_SEG5 0
1564
1565 #define DBGU_IO_BASE__INST4_SEG0 0
1566 #define DBGU_IO_BASE__INST4_SEG1 0
1567 #define DBGU_IO_BASE__INST4_SEG2 0
1568 #define DBGU_IO_BASE__INST4_SEG3 0
1569 #define DBGU_IO_BASE__INST4_SEG4 0
1570 #define DBGU_IO_BASE__INST4_SEG5 0
1571
1572 #define DBGU_IO_BASE__INST5_SEG0 0
1573 #define DBGU_IO_BASE__INST5_SEG1 0
1574 #define DBGU_IO_BASE__INST5_SEG2 0
1575 #define DBGU_IO_BASE__INST5_SEG3 0
1576 #define DBGU_IO_BASE__INST5_SEG4 0
1577 #define DBGU_IO_BASE__INST5_SEG5 0
1578
1579 #define DBGU_IO_BASE__INST6_SEG0 0
1580 #define DBGU_IO_BASE__INST6_SEG1 0
1581 #define DBGU_IO_BASE__INST6_SEG2 0
1582 #define DBGU_IO_BASE__INST6_SEG3 0
1583 #define DBGU_IO_BASE__INST6_SEG4 0
1584 #define DBGU_IO_BASE__INST6_SEG5 0
1585
1586 #define DBGU_IO_BASE__INST7_SEG0 0
1587 #define DBGU_IO_BASE__INST7_SEG1 0
1588 #define DBGU_IO_BASE__INST7_SEG2 0
1589 #define DBGU_IO_BASE__INST7_SEG3 0
1590 #define DBGU_IO_BASE__INST7_SEG4 0
1591 #define DBGU_IO_BASE__INST7_SEG5 0
1592
1593 #define RSMU_BASE__INST0_SEG0 0x00012000
1594 #define RSMU_BASE__INST0_SEG1 0
1595 #define RSMU_BASE__INST0_SEG2 0
1596 #define RSMU_BASE__INST0_SEG3 0
1597 #define RSMU_BASE__INST0_SEG4 0
1598 #define RSMU_BASE__INST0_SEG5 0
1599
1600 #define RSMU_BASE__INST1_SEG0 0
1601 #define RSMU_BASE__INST1_SEG1 0
1602 #define RSMU_BASE__INST1_SEG2 0
1603 #define RSMU_BASE__INST1_SEG3 0
1604 #define RSMU_BASE__INST1_SEG4 0
1605 #define RSMU_BASE__INST1_SEG5 0
1606
1607 #define RSMU_BASE__INST2_SEG0 0
1608 #define RSMU_BASE__INST2_SEG1 0
1609 #define RSMU_BASE__INST2_SEG2 0
1610 #define RSMU_BASE__INST2_SEG3 0
1611 #define RSMU_BASE__INST2_SEG4 0
1612 #define RSMU_BASE__INST2_SEG5 0
1613
1614 #define RSMU_BASE__INST3_SEG0 0
1615 #define RSMU_BASE__INST3_SEG1 0
1616 #define RSMU_BASE__INST3_SEG2 0
1617 #define RSMU_BASE__INST3_SEG3 0
1618 #define RSMU_BASE__INST3_SEG4 0
1619 #define RSMU_BASE__INST3_SEG5 0
1620
1621 #define RSMU_BASE__INST4_SEG0 0
1622 #define RSMU_BASE__INST4_SEG1 0
1623 #define RSMU_BASE__INST4_SEG2 0
1624 #define RSMU_BASE__INST4_SEG3 0
1625 #define RSMU_BASE__INST4_SEG4 0
1626 #define RSMU_BASE__INST4_SEG5 0
1627
1628 #define RSMU_BASE__INST5_SEG0 0
1629 #define RSMU_BASE__INST5_SEG1 0
1630 #define RSMU_BASE__INST5_SEG2 0
1631 #define RSMU_BASE__INST5_SEG3 0
1632 #define RSMU_BASE__INST5_SEG4 0
1633 #define RSMU_BASE__INST5_SEG5 0
1634
1635 #define RSMU_BASE__INST6_SEG0 0
1636 #define RSMU_BASE__INST6_SEG1 0
1637 #define RSMU_BASE__INST6_SEG2 0
1638 #define RSMU_BASE__INST6_SEG3 0
1639 #define RSMU_BASE__INST6_SEG4 0
1640 #define RSMU_BASE__INST6_SEG5 0
1641
1642 #define RSMU_BASE__INST7_SEG0 0
1643 #define RSMU_BASE__INST7_SEG1 0
1644 #define RSMU_BASE__INST7_SEG2 0
1645 #define RSMU_BASE__INST7_SEG3 0
1646 #define RSMU_BASE__INST7_SEG4 0
1647 #define RSMU_BASE__INST7_SEG5 0
1648
1649
1650 #endif
Linux with added FPC-III support