drivers/gpu/drm/amd/include/kgd_kfd_interface.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /*
  24  * This file defines the private interface between the
  25  * AMD kernel graphics drivers and the AMD KFD.
  26  */
  27
  28 #ifndef KGD_KFD_INTERFACE_H_INCLUDED
  29 #define KGD_KFD_INTERFACE_H_INCLUDED
  30
  31 #include <linux/types.h>
  32 #include <linux/bitmap.h>
  33 #include <linux/dma-fence.h>
  34
  35 struct pci_dev;
  36
  37 #define KGD_MAX_QUEUES 128
  38
  39 struct kfd_dev;
  40 struct kgd_dev;
  41
  42 struct kgd_mem;
  43
  44 enum kfd_preempt_type {
  45         KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
  46         KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  47 };
  48
  49 struct kfd_vm_fault_info {
  50         uint64_t        page_addr;
  51         uint32_t        vmid;
  52         uint32_t        mc_id;
  53         uint32_t        status;
  54         bool            prot_valid;
  55         bool            prot_read;
  56         bool            prot_write;
  57         bool            prot_exec;
  58 };
  59
  60 struct kfd_cu_info {
  61         uint32_t num_shader_engines;
  62         uint32_t num_shader_arrays_per_engine;
  63         uint32_t num_cu_per_sh;
  64         uint32_t cu_active_number;
  65         uint32_t cu_ao_mask;
  66         uint32_t simd_per_cu;
  67         uint32_t max_waves_per_simd;
  68         uint32_t wave_front_size;
  69         uint32_t max_scratch_slots_per_cu;
  70         uint32_t lds_size;
  71         uint32_t cu_bitmap[4][4];
  72 };
  73
  74 /* For getting GPU local memory information from KGD */
  75 struct kfd_local_mem_info {
  76         uint64_t local_mem_size_private;
  77         uint64_t local_mem_size_public;
  78         uint32_t vram_width;
  79         uint32_t mem_clk_max;
  80 };
  81
  82 enum kgd_memory_pool {
  83         KGD_POOL_SYSTEM_CACHEABLE = 1,
  84         KGD_POOL_SYSTEM_WRITECOMBINE = 2,
  85         KGD_POOL_FRAMEBUFFER = 3,
  86 };
  87
  88 /**
  89  * enum kfd_sched_policy
  90  *
  91  * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
  92  * scheduling. In this scheduling mode we're using the firmware code to
  93  * schedule the user mode queues and kernel queues such as HIQ and DIQ.
  94  * the HIQ queue is used as a special queue that dispatches the configuration
  95  * to the cp and the user mode queues list that are currently running.
  96  * the DIQ queue is a debugging queue that dispatches debugging commands to the
  97  * firmware.
  98  * in this scheduling mode user mode queues over subscription feature is
  99  * enabled.
 100  *
 101  * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
 102  * subscription feature disabled.
 103  *
 104  * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
 105  * set the command processor registers and sets the queues "manually". This
 106  * mode is used *ONLY* for debugging proposes.
 107  *
 108  */
 109 enum kfd_sched_policy {
 110         KFD_SCHED_POLICY_HWS = 0,
 111         KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
 112         KFD_SCHED_POLICY_NO_HWS
 113 };
 114
 115 struct kgd2kfd_shared_resources {
 116         /* Bit n == 1 means VMID n is available for KFD. */
 117         unsigned int compute_vmid_bitmap;
 118
 119         /* number of pipes per mec */
 120         uint32_t num_pipe_per_mec;
 121
 122         /* number of queues per pipe */
 123         uint32_t num_queue_per_pipe;
 124
 125         /* Bit n == 1 means Queue n is available for KFD */
 126         DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
 127
 128         /* SDMA doorbell assignments (SOC15 and later chips only). Only
 129          * specific doorbells are routed to each SDMA engine. Others
 130          * are routed to IH and VCN. They are not usable by the CP.
 131          */
 132         uint32_t *sdma_doorbell_idx;
 133
 134         /* From SOC15 onward, the doorbell index range not usable for CP
 135          * queues.
 136          */
 137         uint32_t non_cp_doorbells_start;
 138         uint32_t non_cp_doorbells_end;
 139
 140         /* Base address of doorbell aperture. */
 141         phys_addr_t doorbell_physical_address;
 142
 143         /* Size in bytes of doorbell aperture. */
 144         size_t doorbell_aperture_size;
 145
 146         /* Number of bytes at start of aperture reserved for KGD. */
 147         size_t doorbell_start_offset;
 148
 149         /* GPUVM address space size in bytes */
 150         uint64_t gpuvm_size;
 151
 152         /* Minor device number of the render node */
 153         int drm_render_minor;
 154 };
 155
 156 struct tile_config {
 157         uint32_t *tile_config_ptr;
 158         uint32_t *macro_tile_config_ptr;
 159         uint32_t num_tile_configs;
 160         uint32_t num_macro_tile_configs;
 161
 162         uint32_t gb_addr_config;
 163         uint32_t num_banks;
 164         uint32_t num_ranks;
 165 };
 166
 167 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
 168
 169 /*
 170  * Allocation flag domains
 171  * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
 172  */
 173 #define ALLOC_MEM_FLAGS_VRAM            (1 << 0)
 174 #define ALLOC_MEM_FLAGS_GTT             (1 << 1)
 175 #define ALLOC_MEM_FLAGS_USERPTR         (1 << 2)
 176 #define ALLOC_MEM_FLAGS_DOORBELL        (1 << 3)
 177 #define ALLOC_MEM_FLAGS_MMIO_REMAP      (1 << 4)
 178
 179 /*
 180  * Allocation flags attributes/access options.
 181  * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
 182  */
 183 #define ALLOC_MEM_FLAGS_WRITABLE        (1 << 31)
 184 #define ALLOC_MEM_FLAGS_EXECUTABLE      (1 << 30)
 185 #define ALLOC_MEM_FLAGS_PUBLIC          (1 << 29)
 186 #define ALLOC_MEM_FLAGS_NO_SUBSTITUTE   (1 << 28) /* TODO */
 187 #define ALLOC_MEM_FLAGS_AQL_QUEUE_MEM   (1 << 27)
 188 #define ALLOC_MEM_FLAGS_COHERENT        (1 << 26) /* For GFXv9 or later */
 189
 190 /**
 191  * struct kfd2kgd_calls
 192  *
 193  * @program_sh_mem_settings: A function that should initiate the memory
 194  * properties such as main aperture memory type (cache / non cached) and
 195  * secondary aperture base address, size and memory type.
 196  * This function is used only for no cp scheduling mode.
 197  *
 198  * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
 199  * scheduling mode. Only used for no cp scheduling mode.
 200  *
 201  * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
 202  * sceduling mode.
 203  *
 204  * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
 205  * used only for no HWS mode.
 206  *
 207  * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
 208  * Array is allocated with kmalloc, needs to be freed with kfree by caller.
 209  *
 210  * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
 211  * Array is allocated with kmalloc, needs to be freed with kfree by caller.
 212  *
 213  * @hqd_is_occupies: Checks if a hqd slot is occupied.
 214  *
 215  * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
 216  *
 217  * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
 218  *
 219  * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
 220  * SDMA hqd slot.
 221  *
 222  * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
 223  * Only used for no cp scheduling mode
 224  *
 225  * @get_tile_config: Returns GPU-specific tiling mode information
 226  *
 227  * @set_vm_context_page_table_base: Program page table base for a VMID
 228  *
 229  * @invalidate_tlbs: Invalidate TLBs for a specific PASID
 230  *
 231  * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
 232  *
 233  * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
 234  * IH ring entry. This function allows the KFD ISR to get the VMID
 235  * from the fault status register as early as possible.
 236  *
 237  * @get_hive_id: Returns hive id of current  device,  0 if xgmi is not enabled
 238  *
 239  * This structure contains function pointers to services that the kgd driver
 240  * provides to amdkfd driver.
 241  *
 242  */
 243 struct kfd2kgd_calls {
 244         /* Register access functions */
 245         void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
 246                         uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
 247                         uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
 248
 249         int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
 250                                         unsigned int vmid);
 251
 252         int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
 253
 254         int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 255                         uint32_t queue_id, uint32_t __user *wptr,
 256                         uint32_t wptr_shift, uint32_t wptr_mask,
 257                         struct mm_struct *mm);
 258
 259         int (*hiq_mqd_load)(struct kgd_dev *kgd, void *mqd,
 260                             uint32_t pipe_id, uint32_t queue_id,
 261                             uint32_t doorbell_off);
 262
 263         int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
 264                              uint32_t __user *wptr, struct mm_struct *mm);
 265
 266         int (*hqd_dump)(struct kgd_dev *kgd,
 267                         uint32_t pipe_id, uint32_t queue_id,
 268                         uint32_t (**dump)[2], uint32_t *n_regs);
 269
 270         int (*hqd_sdma_dump)(struct kgd_dev *kgd,
 271                              uint32_t engine_id, uint32_t queue_id,
 272                              uint32_t (**dump)[2], uint32_t *n_regs);
 273
 274         bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
 275                                 uint32_t pipe_id, uint32_t queue_id);
 276
 277         int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
 278                                 unsigned int timeout, uint32_t pipe_id,
 279                                 uint32_t queue_id);
 280
 281         bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
 282
 283         int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
 284                                 unsigned int timeout);
 285
 286         int (*address_watch_disable)(struct kgd_dev *kgd);
 287         int (*address_watch_execute)(struct kgd_dev *kgd,
 288                                         unsigned int watch_point_id,
 289                                         uint32_t cntl_val,
 290                                         uint32_t addr_hi,
 291                                         uint32_t addr_lo);
 292         int (*wave_control_execute)(struct kgd_dev *kgd,
 293                                         uint32_t gfx_index_val,
 294                                         uint32_t sq_cmd);
 295         uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
 296                                         unsigned int watch_point_id,
 297                                         unsigned int reg_offset);
 298         bool (*get_atc_vmid_pasid_mapping_info)(
 299                                         struct kgd_dev *kgd,
 300                                         uint8_t vmid,
 301                                         uint16_t *p_pasid);
 302
 303         /* No longer needed from GFXv9 onward. The scratch base address is
 304          * passed to the shader by the CP. It's the user mode driver's
 305          * responsibility.
 306          */
 307         void (*set_scratch_backing_va)(struct kgd_dev *kgd,
 308                                 uint64_t va, uint32_t vmid);
 309
 310         int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
 311
 312         void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
 313                         uint32_t vmid, uint64_t page_table_base);
 314         uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
 315         uint64_t (*get_hive_id)(struct kgd_dev *kgd);
 316
 317 };
 318
 319 #endif  /* KGD_KFD_INTERFACE_H_INCLUDED */