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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / include / renoir_ip_offset.h
blob07633e22e99a15c15debf61b0b79a2ba3b82f266
1 /*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21 #ifndef _renoir_ip_offset_HEADER
22 #define _renoir_ip_offset_HEADER
23
24 #define MAX_INSTANCE 7
25 #define MAX_SEGMENT 5
26
27
28 struct IP_BASE_INSTANCE
29 {
30 unsigned int segment[MAX_SEGMENT];
31 };
32
33 struct IP_BASE
34 {
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36 };
37
38
39 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0 } },
51 { { 0, 0, 0, 0, 0 } },
52 { { 0, 0, 0, 0, 0 } } } };
53 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } } } };
60 static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } } } };
67 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
68 { { 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } } } };
74 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
75 { { 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } } } };
81 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0 } } } };
88 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } } } };
95 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } } } };
102 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } } } };
109 static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } } } };
116 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
117 { { 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } } } };
123 static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } } } };
130 static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0 } } } };
137 static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
138 { { 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0 } } } };
144 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0 } } } };
151 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
152 { { 0, 0, 0, 0, 0 } },
153 { { 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0 } } } };
158 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0 } } } };
165 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
166 { { 0, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0 } } } };
172 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
173 { { 0, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0 } },
175 { { 0, 0, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0 } } } };
177 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0 } },
181 { { 0, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0 } },
183 { { 0, 0, 0, 0, 0 } } } };
184 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0 } },
186 { { 0, 0, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } } } };
191 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } },
193 { { 0, 0, 0, 0, 0 } },
194 { { 0, 0, 0, 0, 0 } },
195 { { 0, 0, 0, 0, 0 } },
196 { { 0, 0, 0, 0, 0 } },
197 { { 0, 0, 0, 0, 0 } } } };
198 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
199 { { 0, 0, 0, 0, 0 } },
200 { { 0, 0, 0, 0, 0 } },
201 { { 0, 0, 0, 0, 0 } },
202 { { 0, 0, 0, 0, 0 } },
203 { { 0, 0, 0, 0, 0 } },
204 { { 0, 0, 0, 0, 0 } } } };
205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
206 { { 0, 0, 0, 0, 0 } },
207 { { 0, 0, 0, 0, 0 } },
208 { { 0, 0, 0, 0, 0 } },
209 { { 0, 0, 0, 0, 0 } },
210 { { 0, 0, 0, 0, 0 } },
211 { { 0, 0, 0, 0, 0 } } } };
212 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
213 { { 0x00054000, 0x02425C00, 0, 0, 0 } },
214 { { 0, 0, 0, 0, 0 } },
215 { { 0, 0, 0, 0, 0 } },
216 { { 0, 0, 0, 0, 0 } },
217 { { 0, 0, 0, 0, 0 } },
218 { { 0, 0, 0, 0, 0 } } } };
219 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
220 { { 0, 0, 0, 0, 0 } },
221 { { 0, 0, 0, 0, 0 } },
222 { { 0, 0, 0, 0, 0 } },
223 { { 0, 0, 0, 0, 0 } },
224 { { 0, 0, 0, 0, 0 } },
225 { { 0, 0, 0, 0, 0 } } } };
226 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
227 { { 0, 0, 0, 0, 0 } },
228 { { 0, 0, 0, 0, 0 } },
229 { { 0, 0, 0, 0, 0 } },
230 { { 0, 0, 0, 0, 0 } },
231 { { 0, 0, 0, 0, 0 } },
232 { { 0, 0, 0, 0, 0 } } } };
233
234
235 #define ACP_BASE__INST0_SEG0 0x02403800
236 #define ACP_BASE__INST0_SEG1 0x00480000
237 #define ACP_BASE__INST0_SEG2 0
238 #define ACP_BASE__INST0_SEG3 0
239 #define ACP_BASE__INST0_SEG4 0
240
241 #define ACP_BASE__INST1_SEG0 0
242 #define ACP_BASE__INST1_SEG1 0
243 #define ACP_BASE__INST1_SEG2 0
244 #define ACP_BASE__INST1_SEG3 0
245 #define ACP_BASE__INST1_SEG4 0
246
247 #define ACP_BASE__INST2_SEG0 0
248 #define ACP_BASE__INST2_SEG1 0
249 #define ACP_BASE__INST2_SEG2 0
250 #define ACP_BASE__INST2_SEG3 0
251 #define ACP_BASE__INST2_SEG4 0
252
253 #define ACP_BASE__INST3_SEG0 0
254 #define ACP_BASE__INST3_SEG1 0
255 #define ACP_BASE__INST3_SEG2 0
256 #define ACP_BASE__INST3_SEG3 0
257 #define ACP_BASE__INST3_SEG4 0
258
259 #define ACP_BASE__INST4_SEG0 0
260 #define ACP_BASE__INST4_SEG1 0
261 #define ACP_BASE__INST4_SEG2 0
262 #define ACP_BASE__INST4_SEG3 0
263 #define ACP_BASE__INST4_SEG4 0
264
265 #define ACP_BASE__INST5_SEG0 0
266 #define ACP_BASE__INST5_SEG1 0
267 #define ACP_BASE__INST5_SEG2 0
268 #define ACP_BASE__INST5_SEG3 0
269 #define ACP_BASE__INST5_SEG4 0
270
271 #define ACP_BASE__INST6_SEG0 0
272 #define ACP_BASE__INST6_SEG1 0
273 #define ACP_BASE__INST6_SEG2 0
274 #define ACP_BASE__INST6_SEG3 0
275 #define ACP_BASE__INST6_SEG4 0
276
277 #define ATHUB_BASE__INST0_SEG0 0x00000C20
278 #define ATHUB_BASE__INST0_SEG1 0x02408C00
279 #define ATHUB_BASE__INST0_SEG2 0
280 #define ATHUB_BASE__INST0_SEG3 0
281 #define ATHUB_BASE__INST0_SEG4 0
282
283 #define ATHUB_BASE__INST1_SEG0 0
284 #define ATHUB_BASE__INST1_SEG1 0
285 #define ATHUB_BASE__INST1_SEG2 0
286 #define ATHUB_BASE__INST1_SEG3 0
287 #define ATHUB_BASE__INST1_SEG4 0
288
289 #define ATHUB_BASE__INST2_SEG0 0
290 #define ATHUB_BASE__INST2_SEG1 0
291 #define ATHUB_BASE__INST2_SEG2 0
292 #define ATHUB_BASE__INST2_SEG3 0
293 #define ATHUB_BASE__INST2_SEG4 0
294
295 #define ATHUB_BASE__INST3_SEG0 0
296 #define ATHUB_BASE__INST3_SEG1 0
297 #define ATHUB_BASE__INST3_SEG2 0
298 #define ATHUB_BASE__INST3_SEG3 0
299 #define ATHUB_BASE__INST3_SEG4 0
300
301 #define ATHUB_BASE__INST4_SEG0 0
302 #define ATHUB_BASE__INST4_SEG1 0
303 #define ATHUB_BASE__INST4_SEG2 0
304 #define ATHUB_BASE__INST4_SEG3 0
305 #define ATHUB_BASE__INST4_SEG4 0
306
307 #define ATHUB_BASE__INST5_SEG0 0
308 #define ATHUB_BASE__INST5_SEG1 0
309 #define ATHUB_BASE__INST5_SEG2 0
310 #define ATHUB_BASE__INST5_SEG3 0
311 #define ATHUB_BASE__INST5_SEG4 0
312
313 #define ATHUB_BASE__INST6_SEG0 0
314 #define ATHUB_BASE__INST6_SEG1 0
315 #define ATHUB_BASE__INST6_SEG2 0
316 #define ATHUB_BASE__INST6_SEG3 0
317 #define ATHUB_BASE__INST6_SEG4 0
318
319 #define CLK_BASE__INST0_SEG0 0x00016C00
320 #define CLK_BASE__INST0_SEG1 0x00016E00
321 #define CLK_BASE__INST0_SEG2 0x00017000
322 #define CLK_BASE__INST0_SEG3 0x00017E00
323 #define CLK_BASE__INST0_SEG4 0
324
325 #define CLK_BASE__INST1_SEG0 0
326 #define CLK_BASE__INST1_SEG1 0
327 #define CLK_BASE__INST1_SEG2 0
328 #define CLK_BASE__INST1_SEG3 0
329 #define CLK_BASE__INST1_SEG4 0
330
331 #define CLK_BASE__INST2_SEG0 0
332 #define CLK_BASE__INST2_SEG1 0
333 #define CLK_BASE__INST2_SEG2 0
334 #define CLK_BASE__INST2_SEG3 0
335 #define CLK_BASE__INST2_SEG4 0
336
337 #define CLK_BASE__INST3_SEG0 0
338 #define CLK_BASE__INST3_SEG1 0
339 #define CLK_BASE__INST3_SEG2 0
340 #define CLK_BASE__INST3_SEG3 0
341 #define CLK_BASE__INST3_SEG4 0
342
343 #define CLK_BASE__INST4_SEG0 0
344 #define CLK_BASE__INST4_SEG1 0
345 #define CLK_BASE__INST4_SEG2 0
346 #define CLK_BASE__INST4_SEG3 0
347 #define CLK_BASE__INST4_SEG4 0
348
349 #define CLK_BASE__INST5_SEG0 0
350 #define CLK_BASE__INST5_SEG1 0
351 #define CLK_BASE__INST5_SEG2 0
352 #define CLK_BASE__INST5_SEG3 0
353 #define CLK_BASE__INST5_SEG4 0
354
355 #define CLK_BASE__INST6_SEG0 0
356 #define CLK_BASE__INST6_SEG1 0
357 #define CLK_BASE__INST6_SEG2 0
358 #define CLK_BASE__INST6_SEG3 0
359 #define CLK_BASE__INST6_SEG4 0
360
361 #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
362 #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
363 #define DBGU_IO0_BASE__INST0_SEG2 0
364 #define DBGU_IO0_BASE__INST0_SEG3 0
365 #define DBGU_IO0_BASE__INST0_SEG4 0
366
367 #define DBGU_IO0_BASE__INST1_SEG0 0
368 #define DBGU_IO0_BASE__INST1_SEG1 0
369 #define DBGU_IO0_BASE__INST1_SEG2 0
370 #define DBGU_IO0_BASE__INST1_SEG3 0
371 #define DBGU_IO0_BASE__INST1_SEG4 0
372
373 #define DBGU_IO0_BASE__INST2_SEG0 0
374 #define DBGU_IO0_BASE__INST2_SEG1 0
375 #define DBGU_IO0_BASE__INST2_SEG2 0
376 #define DBGU_IO0_BASE__INST2_SEG3 0
377 #define DBGU_IO0_BASE__INST2_SEG4 0
378
379 #define DBGU_IO0_BASE__INST3_SEG0 0
380 #define DBGU_IO0_BASE__INST3_SEG1 0
381 #define DBGU_IO0_BASE__INST3_SEG2 0
382 #define DBGU_IO0_BASE__INST3_SEG3 0
383 #define DBGU_IO0_BASE__INST3_SEG4 0
384
385 #define DBGU_IO0_BASE__INST4_SEG0 0
386 #define DBGU_IO0_BASE__INST4_SEG1 0
387 #define DBGU_IO0_BASE__INST4_SEG2 0
388 #define DBGU_IO0_BASE__INST4_SEG3 0
389 #define DBGU_IO0_BASE__INST4_SEG4 0
390
391 #define DBGU_IO0_BASE__INST5_SEG0 0
392 #define DBGU_IO0_BASE__INST5_SEG1 0
393 #define DBGU_IO0_BASE__INST5_SEG2 0
394 #define DBGU_IO0_BASE__INST5_SEG3 0
395 #define DBGU_IO0_BASE__INST5_SEG4 0
396
397 #define DBGU_IO0_BASE__INST6_SEG0 0
398 #define DBGU_IO0_BASE__INST6_SEG1 0
399 #define DBGU_IO0_BASE__INST6_SEG2 0
400 #define DBGU_IO0_BASE__INST6_SEG3 0
401 #define DBGU_IO0_BASE__INST6_SEG4 0
402
403 #define DF_BASE__INST0_SEG0 0x00007000
404 #define DF_BASE__INST0_SEG1 0x0240B800
405 #define DF_BASE__INST0_SEG2 0
406 #define DF_BASE__INST0_SEG3 0
407 #define DF_BASE__INST0_SEG4 0
408
409 #define DF_BASE__INST1_SEG0 0
410 #define DF_BASE__INST1_SEG1 0
411 #define DF_BASE__INST1_SEG2 0
412 #define DF_BASE__INST1_SEG3 0
413 #define DF_BASE__INST1_SEG4 0
414
415 #define DF_BASE__INST2_SEG0 0
416 #define DF_BASE__INST2_SEG1 0
417 #define DF_BASE__INST2_SEG2 0
418 #define DF_BASE__INST2_SEG3 0
419 #define DF_BASE__INST2_SEG4 0
420
421 #define DF_BASE__INST3_SEG0 0
422 #define DF_BASE__INST3_SEG1 0
423 #define DF_BASE__INST3_SEG2 0
424 #define DF_BASE__INST3_SEG3 0
425 #define DF_BASE__INST3_SEG4 0
426
427 #define DF_BASE__INST4_SEG0 0
428 #define DF_BASE__INST4_SEG1 0
429 #define DF_BASE__INST4_SEG2 0
430 #define DF_BASE__INST4_SEG3 0
431 #define DF_BASE__INST4_SEG4 0
432
433 #define DF_BASE__INST5_SEG0 0
434 #define DF_BASE__INST5_SEG1 0
435 #define DF_BASE__INST5_SEG2 0
436 #define DF_BASE__INST5_SEG3 0
437 #define DF_BASE__INST5_SEG4 0
438
439 #define DF_BASE__INST6_SEG0 0
440 #define DF_BASE__INST6_SEG1 0
441 #define DF_BASE__INST6_SEG2 0
442 #define DF_BASE__INST6_SEG3 0
443 #define DF_BASE__INST6_SEG4 0
444
445 #define DIO_BASE__INST0_SEG0 0x02404000
446 #define DIO_BASE__INST0_SEG1 0
447 #define DIO_BASE__INST0_SEG2 0
448 #define DIO_BASE__INST0_SEG3 0
449 #define DIO_BASE__INST0_SEG4 0
450
451 #define DIO_BASE__INST1_SEG0 0
452 #define DIO_BASE__INST1_SEG1 0
453 #define DIO_BASE__INST1_SEG2 0
454 #define DIO_BASE__INST1_SEG3 0
455 #define DIO_BASE__INST1_SEG4 0
456
457 #define DIO_BASE__INST2_SEG0 0
458 #define DIO_BASE__INST2_SEG1 0
459 #define DIO_BASE__INST2_SEG2 0
460 #define DIO_BASE__INST2_SEG3 0
461 #define DIO_BASE__INST2_SEG4 0
462
463 #define DIO_BASE__INST3_SEG0 0
464 #define DIO_BASE__INST3_SEG1 0
465 #define DIO_BASE__INST3_SEG2 0
466 #define DIO_BASE__INST3_SEG3 0
467 #define DIO_BASE__INST3_SEG4 0
468
469 #define DIO_BASE__INST4_SEG0 0
470 #define DIO_BASE__INST4_SEG1 0
471 #define DIO_BASE__INST4_SEG2 0
472 #define DIO_BASE__INST4_SEG3 0
473 #define DIO_BASE__INST4_SEG4 0
474
475 #define DIO_BASE__INST5_SEG0 0
476 #define DIO_BASE__INST5_SEG1 0
477 #define DIO_BASE__INST5_SEG2 0
478 #define DIO_BASE__INST5_SEG3 0
479 #define DIO_BASE__INST5_SEG4 0
480
481 #define DIO_BASE__INST6_SEG0 0
482 #define DIO_BASE__INST6_SEG1 0
483 #define DIO_BASE__INST6_SEG2 0
484 #define DIO_BASE__INST6_SEG3 0
485 #define DIO_BASE__INST6_SEG4 0
486
487 #define DMU_BASE__INST0_SEG0 0x00000012
488 #define DMU_BASE__INST0_SEG1 0x000000C0
489 #define DMU_BASE__INST0_SEG2 0x000034C0
490 #define DMU_BASE__INST0_SEG3 0x00009000
491 #define DMU_BASE__INST0_SEG4 0x02403C00
492
493 #define DMU_BASE__INST1_SEG0 0
494 #define DMU_BASE__INST1_SEG1 0
495 #define DMU_BASE__INST1_SEG2 0
496 #define DMU_BASE__INST1_SEG3 0
497 #define DMU_BASE__INST1_SEG4 0
498
499 #define DMU_BASE__INST2_SEG0 0
500 #define DMU_BASE__INST2_SEG1 0
501 #define DMU_BASE__INST2_SEG2 0
502 #define DMU_BASE__INST2_SEG3 0
503 #define DMU_BASE__INST2_SEG4 0
504
505 #define DMU_BASE__INST3_SEG0 0
506 #define DMU_BASE__INST3_SEG1 0
507 #define DMU_BASE__INST3_SEG2 0
508 #define DMU_BASE__INST3_SEG3 0
509 #define DMU_BASE__INST3_SEG4 0
510
511 #define DMU_BASE__INST4_SEG0 0
512 #define DMU_BASE__INST4_SEG1 0
513 #define DMU_BASE__INST4_SEG2 0
514 #define DMU_BASE__INST4_SEG3 0
515 #define DMU_BASE__INST4_SEG4 0
516
517 #define DMU_BASE__INST5_SEG0 0
518 #define DMU_BASE__INST5_SEG1 0
519 #define DMU_BASE__INST5_SEG2 0
520 #define DMU_BASE__INST5_SEG3 0
521 #define DMU_BASE__INST5_SEG4 0
522
523 #define DMU_BASE__INST6_SEG0 0
524 #define DMU_BASE__INST6_SEG1 0
525 #define DMU_BASE__INST6_SEG2 0
526 #define DMU_BASE__INST6_SEG3 0
527 #define DMU_BASE__INST6_SEG4 0
528
529 #define DPCS_BASE__INST0_SEG0 0x00000012
530 #define DPCS_BASE__INST0_SEG1 0x000000C0
531 #define DPCS_BASE__INST0_SEG2 0x000034C0
532 #define DPCS_BASE__INST0_SEG3 0x00009000
533 #define DPCS_BASE__INST0_SEG4 0x02403C00
534
535 #define DPCS_BASE__INST1_SEG0 0
536 #define DPCS_BASE__INST1_SEG1 0
537 #define DPCS_BASE__INST1_SEG2 0
538 #define DPCS_BASE__INST1_SEG3 0
539 #define DPCS_BASE__INST1_SEG4 0
540
541 #define DPCS_BASE__INST2_SEG0 0
542 #define DPCS_BASE__INST2_SEG1 0
543 #define DPCS_BASE__INST2_SEG2 0
544 #define DPCS_BASE__INST2_SEG3 0
545 #define DPCS_BASE__INST2_SEG4 0
546
547 #define DPCS_BASE__INST3_SEG0 0
548 #define DPCS_BASE__INST3_SEG1 0
549 #define DPCS_BASE__INST3_SEG2 0
550 #define DPCS_BASE__INST3_SEG3 0
551 #define DPCS_BASE__INST3_SEG4 0
552
553 #define DPCS_BASE__INST4_SEG0 0
554 #define DPCS_BASE__INST4_SEG1 0
555 #define DPCS_BASE__INST4_SEG2 0
556 #define DPCS_BASE__INST4_SEG3 0
557 #define DPCS_BASE__INST4_SEG4 0
558
559 #define DPCS_BASE__INST5_SEG0 0
560 #define DPCS_BASE__INST5_SEG1 0
561 #define DPCS_BASE__INST5_SEG2 0
562 #define DPCS_BASE__INST5_SEG3 0
563 #define DPCS_BASE__INST5_SEG4 0
564
565 #define DPCS_BASE__INST6_SEG0 0
566 #define DPCS_BASE__INST6_SEG1 0
567 #define DPCS_BASE__INST6_SEG2 0
568 #define DPCS_BASE__INST6_SEG3 0
569 #define DPCS_BASE__INST6_SEG4 0
570
571 #define FUSE_BASE__INST0_SEG0 0x00017400
572 #define FUSE_BASE__INST0_SEG1 0x02401400
573 #define FUSE_BASE__INST0_SEG2 0
574 #define FUSE_BASE__INST0_SEG3 0
575 #define FUSE_BASE__INST0_SEG4 0
576
577 #define FUSE_BASE__INST1_SEG0 0
578 #define FUSE_BASE__INST1_SEG1 0
579 #define FUSE_BASE__INST1_SEG2 0
580 #define FUSE_BASE__INST1_SEG3 0
581 #define FUSE_BASE__INST1_SEG4 0
582
583 #define FUSE_BASE__INST2_SEG0 0
584 #define FUSE_BASE__INST2_SEG1 0
585 #define FUSE_BASE__INST2_SEG2 0
586 #define FUSE_BASE__INST2_SEG3 0
587 #define FUSE_BASE__INST2_SEG4 0
588
589 #define FUSE_BASE__INST3_SEG0 0
590 #define FUSE_BASE__INST3_SEG1 0
591 #define FUSE_BASE__INST3_SEG2 0
592 #define FUSE_BASE__INST3_SEG3 0
593 #define FUSE_BASE__INST3_SEG4 0
594
595 #define FUSE_BASE__INST4_SEG0 0
596 #define FUSE_BASE__INST4_SEG1 0
597 #define FUSE_BASE__INST4_SEG2 0
598 #define FUSE_BASE__INST4_SEG3 0
599 #define FUSE_BASE__INST4_SEG4 0
600
601 #define FUSE_BASE__INST5_SEG0 0
602 #define FUSE_BASE__INST5_SEG1 0
603 #define FUSE_BASE__INST5_SEG2 0
604 #define FUSE_BASE__INST5_SEG3 0
605 #define FUSE_BASE__INST5_SEG4 0
606
607 #define FUSE_BASE__INST6_SEG0 0
608 #define FUSE_BASE__INST6_SEG1 0
609 #define FUSE_BASE__INST6_SEG2 0
610 #define FUSE_BASE__INST6_SEG3 0
611 #define FUSE_BASE__INST6_SEG4 0
612
613 #define GC_BASE__INST0_SEG0 0x00002000
614 #define GC_BASE__INST0_SEG1 0x0000A000
615 #define GC_BASE__INST0_SEG2 0x02402C00
616 #define GC_BASE__INST0_SEG3 0
617 #define GC_BASE__INST0_SEG4 0
618
619 #define GC_BASE__INST1_SEG0 0
620 #define GC_BASE__INST1_SEG1 0
621 #define GC_BASE__INST1_SEG2 0
622 #define GC_BASE__INST1_SEG3 0
623 #define GC_BASE__INST1_SEG4 0
624
625 #define GC_BASE__INST2_SEG0 0
626 #define GC_BASE__INST2_SEG1 0
627 #define GC_BASE__INST2_SEG2 0
628 #define GC_BASE__INST2_SEG3 0
629 #define GC_BASE__INST2_SEG4 0
630
631 #define GC_BASE__INST3_SEG0 0
632 #define GC_BASE__INST3_SEG1 0
633 #define GC_BASE__INST3_SEG2 0
634 #define GC_BASE__INST3_SEG3 0
635 #define GC_BASE__INST3_SEG4 0
636
637 #define GC_BASE__INST4_SEG0 0
638 #define GC_BASE__INST4_SEG1 0
639 #define GC_BASE__INST4_SEG2 0
640 #define GC_BASE__INST4_SEG3 0
641 #define GC_BASE__INST4_SEG4 0
642
643 #define GC_BASE__INST5_SEG0 0
644 #define GC_BASE__INST5_SEG1 0
645 #define GC_BASE__INST5_SEG2 0
646 #define GC_BASE__INST5_SEG3 0
647 #define GC_BASE__INST5_SEG4 0
648
649 #define GC_BASE__INST6_SEG0 0
650 #define GC_BASE__INST6_SEG1 0
651 #define GC_BASE__INST6_SEG2 0
652 #define GC_BASE__INST6_SEG3 0
653 #define GC_BASE__INST6_SEG4 0
654
655 #define HDA_BASE__INST0_SEG0 0x02404800
656 #define HDA_BASE__INST0_SEG1 0x004C0000
657 #define HDA_BASE__INST0_SEG2 0
658 #define HDA_BASE__INST0_SEG3 0
659 #define HDA_BASE__INST0_SEG4 0
660
661 #define HDA_BASE__INST1_SEG0 0
662 #define HDA_BASE__INST1_SEG1 0
663 #define HDA_BASE__INST1_SEG2 0
664 #define HDA_BASE__INST1_SEG3 0
665 #define HDA_BASE__INST1_SEG4 0
666
667 #define HDA_BASE__INST2_SEG0 0
668 #define HDA_BASE__INST2_SEG1 0
669 #define HDA_BASE__INST2_SEG2 0
670 #define HDA_BASE__INST2_SEG3 0
671 #define HDA_BASE__INST2_SEG4 0
672
673 #define HDA_BASE__INST3_SEG0 0
674 #define HDA_BASE__INST3_SEG1 0
675 #define HDA_BASE__INST3_SEG2 0
676 #define HDA_BASE__INST3_SEG3 0
677 #define HDA_BASE__INST3_SEG4 0
678
679 #define HDA_BASE__INST4_SEG0 0
680 #define HDA_BASE__INST4_SEG1 0
681 #define HDA_BASE__INST4_SEG2 0
682 #define HDA_BASE__INST4_SEG3 0
683 #define HDA_BASE__INST4_SEG4 0
684
685 #define HDA_BASE__INST5_SEG0 0
686 #define HDA_BASE__INST5_SEG1 0
687 #define HDA_BASE__INST5_SEG2 0
688 #define HDA_BASE__INST5_SEG3 0
689 #define HDA_BASE__INST5_SEG4 0
690
691 #define HDA_BASE__INST6_SEG0 0
692 #define HDA_BASE__INST6_SEG1 0
693 #define HDA_BASE__INST6_SEG2 0
694 #define HDA_BASE__INST6_SEG3 0
695 #define HDA_BASE__INST6_SEG4 0
696
697 #define HDP_BASE__INST0_SEG0 0x00000F20
698 #define HDP_BASE__INST0_SEG1 0x0240A400
699 #define HDP_BASE__INST0_SEG2 0
700 #define HDP_BASE__INST0_SEG3 0
701 #define HDP_BASE__INST0_SEG4 0
702
703 #define HDP_BASE__INST1_SEG0 0
704 #define HDP_BASE__INST1_SEG1 0
705 #define HDP_BASE__INST1_SEG2 0
706 #define HDP_BASE__INST1_SEG3 0
707 #define HDP_BASE__INST1_SEG4 0
708
709 #define HDP_BASE__INST2_SEG0 0
710 #define HDP_BASE__INST2_SEG1 0
711 #define HDP_BASE__INST2_SEG2 0
712 #define HDP_BASE__INST2_SEG3 0
713 #define HDP_BASE__INST2_SEG4 0
714
715 #define HDP_BASE__INST3_SEG0 0
716 #define HDP_BASE__INST3_SEG1 0
717 #define HDP_BASE__INST3_SEG2 0
718 #define HDP_BASE__INST3_SEG3 0
719 #define HDP_BASE__INST3_SEG4 0
720
721 #define HDP_BASE__INST4_SEG0 0
722 #define HDP_BASE__INST4_SEG1 0
723 #define HDP_BASE__INST4_SEG2 0
724 #define HDP_BASE__INST4_SEG3 0
725 #define HDP_BASE__INST4_SEG4 0
726
727 #define HDP_BASE__INST5_SEG0 0
728 #define HDP_BASE__INST5_SEG1 0
729 #define HDP_BASE__INST5_SEG2 0
730 #define HDP_BASE__INST5_SEG3 0
731 #define HDP_BASE__INST5_SEG4 0
732
733 #define HDP_BASE__INST6_SEG0 0
734 #define HDP_BASE__INST6_SEG1 0
735 #define HDP_BASE__INST6_SEG2 0
736 #define HDP_BASE__INST6_SEG3 0
737 #define HDP_BASE__INST6_SEG4 0
738
739 #define IOHC0_BASE__INST0_SEG0 0x00010000
740 #define IOHC0_BASE__INST0_SEG1 0x02406000
741 #define IOHC0_BASE__INST0_SEG2 0x04EC0000
742 #define IOHC0_BASE__INST0_SEG3 0
743 #define IOHC0_BASE__INST0_SEG4 0
744
745 #define IOHC0_BASE__INST1_SEG0 0
746 #define IOHC0_BASE__INST1_SEG1 0
747 #define IOHC0_BASE__INST1_SEG2 0
748 #define IOHC0_BASE__INST1_SEG3 0
749 #define IOHC0_BASE__INST1_SEG4 0
750
751 #define IOHC0_BASE__INST2_SEG0 0
752 #define IOHC0_BASE__INST2_SEG1 0
753 #define IOHC0_BASE__INST2_SEG2 0
754 #define IOHC0_BASE__INST2_SEG3 0
755 #define IOHC0_BASE__INST2_SEG4 0
756
757 #define IOHC0_BASE__INST3_SEG0 0
758 #define IOHC0_BASE__INST3_SEG1 0
759 #define IOHC0_BASE__INST3_SEG2 0
760 #define IOHC0_BASE__INST3_SEG3 0
761 #define IOHC0_BASE__INST3_SEG4 0
762
763 #define IOHC0_BASE__INST4_SEG0 0
764 #define IOHC0_BASE__INST4_SEG1 0
765 #define IOHC0_BASE__INST4_SEG2 0
766 #define IOHC0_BASE__INST4_SEG3 0
767 #define IOHC0_BASE__INST4_SEG4 0
768
769 #define IOHC0_BASE__INST5_SEG0 0
770 #define IOHC0_BASE__INST5_SEG1 0
771 #define IOHC0_BASE__INST5_SEG2 0
772 #define IOHC0_BASE__INST5_SEG3 0
773 #define IOHC0_BASE__INST5_SEG4 0
774
775 #define IOHC0_BASE__INST6_SEG0 0
776 #define IOHC0_BASE__INST6_SEG1 0
777 #define IOHC0_BASE__INST6_SEG2 0
778 #define IOHC0_BASE__INST6_SEG3 0
779 #define IOHC0_BASE__INST6_SEG4 0
780
781 #define ISP_BASE__INST0_SEG0 0x00018000
782 #define ISP_BASE__INST0_SEG1 0x0240B000
783 #define ISP_BASE__INST0_SEG2 0
784 #define ISP_BASE__INST0_SEG3 0
785 #define ISP_BASE__INST0_SEG4 0
786
787 #define ISP_BASE__INST1_SEG0 0
788 #define ISP_BASE__INST1_SEG1 0
789 #define ISP_BASE__INST1_SEG2 0
790 #define ISP_BASE__INST1_SEG3 0
791 #define ISP_BASE__INST1_SEG4 0
792
793 #define ISP_BASE__INST2_SEG0 0
794 #define ISP_BASE__INST2_SEG1 0
795 #define ISP_BASE__INST2_SEG2 0
796 #define ISP_BASE__INST2_SEG3 0
797 #define ISP_BASE__INST2_SEG4 0
798
799 #define ISP_BASE__INST3_SEG0 0
800 #define ISP_BASE__INST3_SEG1 0
801 #define ISP_BASE__INST3_SEG2 0
802 #define ISP_BASE__INST3_SEG3 0
803 #define ISP_BASE__INST3_SEG4 0
804
805 #define ISP_BASE__INST4_SEG0 0
806 #define ISP_BASE__INST4_SEG1 0
807 #define ISP_BASE__INST4_SEG2 0
808 #define ISP_BASE__INST4_SEG3 0
809 #define ISP_BASE__INST4_SEG4 0
810
811 #define ISP_BASE__INST5_SEG0 0
812 #define ISP_BASE__INST5_SEG1 0
813 #define ISP_BASE__INST5_SEG2 0
814 #define ISP_BASE__INST5_SEG3 0
815 #define ISP_BASE__INST5_SEG4 0
816
817 #define ISP_BASE__INST6_SEG0 0
818 #define ISP_BASE__INST6_SEG1 0
819 #define ISP_BASE__INST6_SEG2 0
820 #define ISP_BASE__INST6_SEG3 0
821 #define ISP_BASE__INST6_SEG4 0
822
823 #define L2IMU0_BASE__INST0_SEG0 0x00007DC0
824 #define L2IMU0_BASE__INST0_SEG1 0x02407000
825 #define L2IMU0_BASE__INST0_SEG2 0x00900000
826 #define L2IMU0_BASE__INST0_SEG3 0x04FC0000
827 #define L2IMU0_BASE__INST0_SEG4 0x055C0000
828
829 #define L2IMU0_BASE__INST1_SEG0 0
830 #define L2IMU0_BASE__INST1_SEG1 0
831 #define L2IMU0_BASE__INST1_SEG2 0
832 #define L2IMU0_BASE__INST1_SEG3 0
833 #define L2IMU0_BASE__INST1_SEG4 0
834
835 #define L2IMU0_BASE__INST2_SEG0 0
836 #define L2IMU0_BASE__INST2_SEG1 0
837 #define L2IMU0_BASE__INST2_SEG2 0
838 #define L2IMU0_BASE__INST2_SEG3 0
839 #define L2IMU0_BASE__INST2_SEG4 0
840
841 #define L2IMU0_BASE__INST3_SEG0 0
842 #define L2IMU0_BASE__INST3_SEG1 0
843 #define L2IMU0_BASE__INST3_SEG2 0
844 #define L2IMU0_BASE__INST3_SEG3 0
845 #define L2IMU0_BASE__INST3_SEG4 0
846
847 #define L2IMU0_BASE__INST4_SEG0 0
848 #define L2IMU0_BASE__INST4_SEG1 0
849 #define L2IMU0_BASE__INST4_SEG2 0
850 #define L2IMU0_BASE__INST4_SEG3 0
851 #define L2IMU0_BASE__INST4_SEG4 0
852
853 #define L2IMU0_BASE__INST5_SEG0 0
854 #define L2IMU0_BASE__INST5_SEG1 0
855 #define L2IMU0_BASE__INST5_SEG2 0
856 #define L2IMU0_BASE__INST5_SEG3 0
857 #define L2IMU0_BASE__INST5_SEG4 0
858
859 #define L2IMU0_BASE__INST6_SEG0 0
860 #define L2IMU0_BASE__INST6_SEG1 0
861 #define L2IMU0_BASE__INST6_SEG2 0
862 #define L2IMU0_BASE__INST6_SEG3 0
863 #define L2IMU0_BASE__INST6_SEG4 0
864
865 #define MMHUB_BASE__INST0_SEG0 0x0001A000
866 #define MMHUB_BASE__INST0_SEG1 0x02408800
867 #define MMHUB_BASE__INST0_SEG2 0
868 #define MMHUB_BASE__INST0_SEG3 0
869 #define MMHUB_BASE__INST0_SEG4 0
870
871 #define MMHUB_BASE__INST1_SEG0 0
872 #define MMHUB_BASE__INST1_SEG1 0
873 #define MMHUB_BASE__INST1_SEG2 0
874 #define MMHUB_BASE__INST1_SEG3 0
875 #define MMHUB_BASE__INST1_SEG4 0
876
877 #define MMHUB_BASE__INST2_SEG0 0
878 #define MMHUB_BASE__INST2_SEG1 0
879 #define MMHUB_BASE__INST2_SEG2 0
880 #define MMHUB_BASE__INST2_SEG3 0
881 #define MMHUB_BASE__INST2_SEG4 0
882
883 #define MMHUB_BASE__INST3_SEG0 0
884 #define MMHUB_BASE__INST3_SEG1 0
885 #define MMHUB_BASE__INST3_SEG2 0
886 #define MMHUB_BASE__INST3_SEG3 0
887 #define MMHUB_BASE__INST3_SEG4 0
888
889 #define MMHUB_BASE__INST4_SEG0 0
890 #define MMHUB_BASE__INST4_SEG1 0
891 #define MMHUB_BASE__INST4_SEG2 0
892 #define MMHUB_BASE__INST4_SEG3 0
893 #define MMHUB_BASE__INST4_SEG4 0
894
895 #define MMHUB_BASE__INST5_SEG0 0
896 #define MMHUB_BASE__INST5_SEG1 0
897 #define MMHUB_BASE__INST5_SEG2 0
898 #define MMHUB_BASE__INST5_SEG3 0
899 #define MMHUB_BASE__INST5_SEG4 0
900
901 #define MMHUB_BASE__INST6_SEG0 0
902 #define MMHUB_BASE__INST6_SEG1 0
903 #define MMHUB_BASE__INST6_SEG2 0
904 #define MMHUB_BASE__INST6_SEG3 0
905 #define MMHUB_BASE__INST6_SEG4 0
906
907 #define MP0_BASE__INST0_SEG0 0x00016000
908 #define MP0_BASE__INST0_SEG1 0x0243FC00
909 #define MP0_BASE__INST0_SEG2 0x00DC0000
910 #define MP0_BASE__INST0_SEG3 0x00E00000
911 #define MP0_BASE__INST0_SEG4 0x00E40000
912
913 #define MP0_BASE__INST1_SEG0 0
914 #define MP0_BASE__INST1_SEG1 0
915 #define MP0_BASE__INST1_SEG2 0
916 #define MP0_BASE__INST1_SEG3 0
917 #define MP0_BASE__INST1_SEG4 0
918
919 #define MP0_BASE__INST2_SEG0 0
920 #define MP0_BASE__INST2_SEG1 0
921 #define MP0_BASE__INST2_SEG2 0
922 #define MP0_BASE__INST2_SEG3 0
923 #define MP0_BASE__INST2_SEG4 0
924
925 #define MP0_BASE__INST3_SEG0 0
926 #define MP0_BASE__INST3_SEG1 0
927 #define MP0_BASE__INST3_SEG2 0
928 #define MP0_BASE__INST3_SEG3 0
929 #define MP0_BASE__INST3_SEG4 0
930
931 #define MP0_BASE__INST4_SEG0 0
932 #define MP0_BASE__INST4_SEG1 0
933 #define MP0_BASE__INST4_SEG2 0
934 #define MP0_BASE__INST4_SEG3 0
935 #define MP0_BASE__INST4_SEG4 0
936
937 #define MP0_BASE__INST5_SEG0 0
938 #define MP0_BASE__INST5_SEG1 0
939 #define MP0_BASE__INST5_SEG2 0
940 #define MP0_BASE__INST5_SEG3 0
941 #define MP0_BASE__INST5_SEG4 0
942
943 #define MP0_BASE__INST6_SEG0 0
944 #define MP0_BASE__INST6_SEG1 0
945 #define MP0_BASE__INST6_SEG2 0
946 #define MP0_BASE__INST6_SEG3 0
947 #define MP0_BASE__INST6_SEG4 0
948
949 #define MP1_BASE__INST0_SEG0 0x00016200
950 #define MP1_BASE__INST0_SEG1 0x02400400
951 #define MP1_BASE__INST0_SEG2 0x00E80000
952 #define MP1_BASE__INST0_SEG3 0x00EC0000
953 #define MP1_BASE__INST0_SEG4 0x00F00000
954
955 #define MP1_BASE__INST1_SEG0 0
956 #define MP1_BASE__INST1_SEG1 0
957 #define MP1_BASE__INST1_SEG2 0
958 #define MP1_BASE__INST1_SEG3 0
959 #define MP1_BASE__INST1_SEG4 0
960
961 #define MP1_BASE__INST2_SEG0 0
962 #define MP1_BASE__INST2_SEG1 0
963 #define MP1_BASE__INST2_SEG2 0
964 #define MP1_BASE__INST2_SEG3 0
965 #define MP1_BASE__INST2_SEG4 0
966
967 #define MP1_BASE__INST3_SEG0 0
968 #define MP1_BASE__INST3_SEG1 0
969 #define MP1_BASE__INST3_SEG2 0
970 #define MP1_BASE__INST3_SEG3 0
971 #define MP1_BASE__INST3_SEG4 0
972
973 #define MP1_BASE__INST4_SEG0 0
974 #define MP1_BASE__INST4_SEG1 0
975 #define MP1_BASE__INST4_SEG2 0
976 #define MP1_BASE__INST4_SEG3 0
977 #define MP1_BASE__INST4_SEG4 0
978
979 #define MP1_BASE__INST5_SEG0 0
980 #define MP1_BASE__INST5_SEG1 0
981 #define MP1_BASE__INST5_SEG2 0
982 #define MP1_BASE__INST5_SEG3 0
983 #define MP1_BASE__INST5_SEG4 0
984
985 #define MP1_BASE__INST6_SEG0 0
986 #define MP1_BASE__INST6_SEG1 0
987 #define MP1_BASE__INST6_SEG2 0
988 #define MP1_BASE__INST6_SEG3 0
989 #define MP1_BASE__INST6_SEG4 0
990
991 #define NBIF0_BASE__INST0_SEG0 0x00000000
992 #define NBIF0_BASE__INST0_SEG1 0x00000014
993 #define NBIF0_BASE__INST0_SEG2 0x00000D20
994 #define NBIF0_BASE__INST0_SEG3 0x00010400
995 #define NBIF0_BASE__INST0_SEG4 0x0241B000
996
997 #define NBIF0_BASE__INST1_SEG0 0
998 #define NBIF0_BASE__INST1_SEG1 0
999 #define NBIF0_BASE__INST1_SEG2 0
1000 #define NBIF0_BASE__INST1_SEG3 0
1001 #define NBIF0_BASE__INST1_SEG4 0
1002
1003 #define NBIF0_BASE__INST2_SEG0 0
1004 #define NBIF0_BASE__INST2_SEG1 0
1005 #define NBIF0_BASE__INST2_SEG2 0
1006 #define NBIF0_BASE__INST2_SEG3 0
1007 #define NBIF0_BASE__INST2_SEG4 0
1008
1009 #define NBIF0_BASE__INST3_SEG0 0
1010 #define NBIF0_BASE__INST3_SEG1 0
1011 #define NBIF0_BASE__INST3_SEG2 0
1012 #define NBIF0_BASE__INST3_SEG3 0
1013 #define NBIF0_BASE__INST3_SEG4 0
1014
1015 #define NBIF0_BASE__INST4_SEG0 0
1016 #define NBIF0_BASE__INST4_SEG1 0
1017 #define NBIF0_BASE__INST4_SEG2 0
1018 #define NBIF0_BASE__INST4_SEG3 0
1019 #define NBIF0_BASE__INST4_SEG4 0
1020
1021 #define NBIF0_BASE__INST5_SEG0 0
1022 #define NBIF0_BASE__INST5_SEG1 0
1023 #define NBIF0_BASE__INST5_SEG2 0
1024 #define NBIF0_BASE__INST5_SEG3 0
1025 #define NBIF0_BASE__INST5_SEG4 0
1026
1027 #define NBIF0_BASE__INST6_SEG0 0
1028 #define NBIF0_BASE__INST6_SEG1 0
1029 #define NBIF0_BASE__INST6_SEG2 0
1030 #define NBIF0_BASE__INST6_SEG3 0
1031 #define NBIF0_BASE__INST6_SEG4 0
1032
1033 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
1034 #define OSSSYS_BASE__INST0_SEG1 0x0240A000
1035 #define OSSSYS_BASE__INST0_SEG2 0
1036 #define OSSSYS_BASE__INST0_SEG3 0
1037 #define OSSSYS_BASE__INST0_SEG4 0
1038
1039 #define OSSSYS_BASE__INST1_SEG0 0
1040 #define OSSSYS_BASE__INST1_SEG1 0
1041 #define OSSSYS_BASE__INST1_SEG2 0
1042 #define OSSSYS_BASE__INST1_SEG3 0
1043 #define OSSSYS_BASE__INST1_SEG4 0
1044
1045 #define OSSSYS_BASE__INST2_SEG0 0
1046 #define OSSSYS_BASE__INST2_SEG1 0
1047 #define OSSSYS_BASE__INST2_SEG2 0
1048 #define OSSSYS_BASE__INST2_SEG3 0
1049 #define OSSSYS_BASE__INST2_SEG4 0
1050
1051 #define OSSSYS_BASE__INST3_SEG0 0
1052 #define OSSSYS_BASE__INST3_SEG1 0
1053 #define OSSSYS_BASE__INST3_SEG2 0
1054 #define OSSSYS_BASE__INST3_SEG3 0
1055 #define OSSSYS_BASE__INST3_SEG4 0
1056
1057 #define OSSSYS_BASE__INST4_SEG0 0
1058 #define OSSSYS_BASE__INST4_SEG1 0
1059 #define OSSSYS_BASE__INST4_SEG2 0
1060 #define OSSSYS_BASE__INST4_SEG3 0
1061 #define OSSSYS_BASE__INST4_SEG4 0
1062
1063 #define OSSSYS_BASE__INST5_SEG0 0
1064 #define OSSSYS_BASE__INST5_SEG1 0
1065 #define OSSSYS_BASE__INST5_SEG2 0
1066 #define OSSSYS_BASE__INST5_SEG3 0
1067 #define OSSSYS_BASE__INST5_SEG4 0
1068
1069 #define OSSSYS_BASE__INST6_SEG0 0
1070 #define OSSSYS_BASE__INST6_SEG1 0
1071 #define OSSSYS_BASE__INST6_SEG2 0
1072 #define OSSSYS_BASE__INST6_SEG3 0
1073 #define OSSSYS_BASE__INST6_SEG4 0
1074
1075 #define PCIE0_BASE__INST0_SEG0 0x02411800
1076 #define PCIE0_BASE__INST0_SEG1 0x04440000
1077 #define PCIE0_BASE__INST0_SEG2 0
1078 #define PCIE0_BASE__INST0_SEG3 0
1079 #define PCIE0_BASE__INST0_SEG4 0
1080
1081 #define PCIE0_BASE__INST1_SEG0 0
1082 #define PCIE0_BASE__INST1_SEG1 0
1083 #define PCIE0_BASE__INST1_SEG2 0
1084 #define PCIE0_BASE__INST1_SEG3 0
1085 #define PCIE0_BASE__INST1_SEG4 0
1086
1087 #define PCIE0_BASE__INST2_SEG0 0
1088 #define PCIE0_BASE__INST2_SEG1 0
1089 #define PCIE0_BASE__INST2_SEG2 0
1090 #define PCIE0_BASE__INST2_SEG3 0
1091 #define PCIE0_BASE__INST2_SEG4 0
1092
1093 #define PCIE0_BASE__INST3_SEG0 0
1094 #define PCIE0_BASE__INST3_SEG1 0
1095 #define PCIE0_BASE__INST3_SEG2 0
1096 #define PCIE0_BASE__INST3_SEG3 0
1097 #define PCIE0_BASE__INST3_SEG4 0
1098
1099 #define PCIE0_BASE__INST4_SEG0 0
1100 #define PCIE0_BASE__INST4_SEG1 0
1101 #define PCIE0_BASE__INST4_SEG2 0
1102 #define PCIE0_BASE__INST4_SEG3 0
1103 #define PCIE0_BASE__INST4_SEG4 0
1104
1105 #define PCIE0_BASE__INST5_SEG0 0
1106 #define PCIE0_BASE__INST5_SEG1 0
1107 #define PCIE0_BASE__INST5_SEG2 0
1108 #define PCIE0_BASE__INST5_SEG3 0
1109 #define PCIE0_BASE__INST5_SEG4 0
1110
1111 #define PCIE0_BASE__INST6_SEG0 0
1112 #define PCIE0_BASE__INST6_SEG1 0
1113 #define PCIE0_BASE__INST6_SEG2 0
1114 #define PCIE0_BASE__INST6_SEG3 0
1115 #define PCIE0_BASE__INST6_SEG4 0
1116
1117 #define SDMA0_BASE__INST0_SEG0 0x00001260
1118 #define SDMA0_BASE__INST0_SEG1 0x0240A800
1119 #define SDMA0_BASE__INST0_SEG2 0
1120 #define SDMA0_BASE__INST0_SEG3 0
1121 #define SDMA0_BASE__INST0_SEG4 0
1122
1123 #define SDMA0_BASE__INST1_SEG0 0
1124 #define SDMA0_BASE__INST1_SEG1 0
1125 #define SDMA0_BASE__INST1_SEG2 0
1126 #define SDMA0_BASE__INST1_SEG3 0
1127 #define SDMA0_BASE__INST1_SEG4 0
1128
1129 #define SDMA0_BASE__INST2_SEG0 0
1130 #define SDMA0_BASE__INST2_SEG1 0
1131 #define SDMA0_BASE__INST2_SEG2 0
1132 #define SDMA0_BASE__INST2_SEG3 0
1133 #define SDMA0_BASE__INST2_SEG4 0
1134
1135 #define SDMA0_BASE__INST3_SEG0 0
1136 #define SDMA0_BASE__INST3_SEG1 0
1137 #define SDMA0_BASE__INST3_SEG2 0
1138 #define SDMA0_BASE__INST3_SEG3 0
1139 #define SDMA0_BASE__INST3_SEG4 0
1140
1141 #define SDMA0_BASE__INST4_SEG0 0
1142 #define SDMA0_BASE__INST4_SEG1 0
1143 #define SDMA0_BASE__INST4_SEG2 0
1144 #define SDMA0_BASE__INST4_SEG3 0
1145 #define SDMA0_BASE__INST4_SEG4 0
1146
1147 #define SDMA0_BASE__INST5_SEG0 0
1148 #define SDMA0_BASE__INST5_SEG1 0
1149 #define SDMA0_BASE__INST5_SEG2 0
1150 #define SDMA0_BASE__INST5_SEG3 0
1151 #define SDMA0_BASE__INST5_SEG4 0
1152
1153 #define SDMA0_BASE__INST6_SEG0 0
1154 #define SDMA0_BASE__INST6_SEG1 0
1155 #define SDMA0_BASE__INST6_SEG2 0
1156 #define SDMA0_BASE__INST6_SEG3 0
1157 #define SDMA0_BASE__INST6_SEG4 0
1158
1159 #define SMUIO_BASE__INST0_SEG0 0x00016800
1160 #define SMUIO_BASE__INST0_SEG1 0x00016A00
1161 #define SMUIO_BASE__INST0_SEG2 0x02401000
1162 #define SMUIO_BASE__INST0_SEG3 0x00440000
1163 #define SMUIO_BASE__INST0_SEG4 0
1164
1165 #define SMUIO_BASE__INST1_SEG0 0
1166 #define SMUIO_BASE__INST1_SEG1 0
1167 #define SMUIO_BASE__INST1_SEG2 0
1168 #define SMUIO_BASE__INST1_SEG3 0
1169 #define SMUIO_BASE__INST1_SEG4 0
1170
1171 #define SMUIO_BASE__INST2_SEG0 0
1172 #define SMUIO_BASE__INST2_SEG1 0
1173 #define SMUIO_BASE__INST2_SEG2 0
1174 #define SMUIO_BASE__INST2_SEG3 0
1175 #define SMUIO_BASE__INST2_SEG4 0
1176
1177 #define SMUIO_BASE__INST3_SEG0 0
1178 #define SMUIO_BASE__INST3_SEG1 0
1179 #define SMUIO_BASE__INST3_SEG2 0
1180 #define SMUIO_BASE__INST3_SEG3 0
1181 #define SMUIO_BASE__INST3_SEG4 0
1182
1183 #define SMUIO_BASE__INST4_SEG0 0
1184 #define SMUIO_BASE__INST4_SEG1 0
1185 #define SMUIO_BASE__INST4_SEG2 0
1186 #define SMUIO_BASE__INST4_SEG3 0
1187 #define SMUIO_BASE__INST4_SEG4 0
1188
1189 #define SMUIO_BASE__INST5_SEG0 0
1190 #define SMUIO_BASE__INST5_SEG1 0
1191 #define SMUIO_BASE__INST5_SEG2 0
1192 #define SMUIO_BASE__INST5_SEG3 0
1193 #define SMUIO_BASE__INST5_SEG4 0
1194
1195 #define SMUIO_BASE__INST6_SEG0 0
1196 #define SMUIO_BASE__INST6_SEG1 0
1197 #define SMUIO_BASE__INST6_SEG2 0
1198 #define SMUIO_BASE__INST6_SEG3 0
1199 #define SMUIO_BASE__INST6_SEG4 0
1200
1201 #define THM_BASE__INST0_SEG0 0x00016600
1202 #define THM_BASE__INST0_SEG1 0x02400C00
1203 #define THM_BASE__INST0_SEG2 0
1204 #define THM_BASE__INST0_SEG3 0
1205 #define THM_BASE__INST0_SEG4 0
1206
1207 #define THM_BASE__INST1_SEG0 0
1208 #define THM_BASE__INST1_SEG1 0
1209 #define THM_BASE__INST1_SEG2 0
1210 #define THM_BASE__INST1_SEG3 0
1211 #define THM_BASE__INST1_SEG4 0
1212
1213 #define THM_BASE__INST2_SEG0 0
1214 #define THM_BASE__INST2_SEG1 0
1215 #define THM_BASE__INST2_SEG2 0
1216 #define THM_BASE__INST2_SEG3 0
1217 #define THM_BASE__INST2_SEG4 0
1218
1219 #define THM_BASE__INST3_SEG0 0
1220 #define THM_BASE__INST3_SEG1 0
1221 #define THM_BASE__INST3_SEG2 0
1222 #define THM_BASE__INST3_SEG3 0
1223 #define THM_BASE__INST3_SEG4 0
1224
1225 #define THM_BASE__INST4_SEG0 0
1226 #define THM_BASE__INST4_SEG1 0
1227 #define THM_BASE__INST4_SEG2 0
1228 #define THM_BASE__INST4_SEG3 0
1229 #define THM_BASE__INST4_SEG4 0
1230
1231 #define THM_BASE__INST5_SEG0 0
1232 #define THM_BASE__INST5_SEG1 0
1233 #define THM_BASE__INST5_SEG2 0
1234 #define THM_BASE__INST5_SEG3 0
1235 #define THM_BASE__INST5_SEG4 0
1236
1237 #define THM_BASE__INST6_SEG0 0
1238 #define THM_BASE__INST6_SEG1 0
1239 #define THM_BASE__INST6_SEG2 0
1240 #define THM_BASE__INST6_SEG3 0
1241 #define THM_BASE__INST6_SEG4 0
1242
1243 #define UMC_BASE__INST0_SEG0 0x00014000
1244 #define UMC_BASE__INST0_SEG1 0x02425800
1245 #define UMC_BASE__INST0_SEG2 0
1246 #define UMC_BASE__INST0_SEG3 0
1247 #define UMC_BASE__INST0_SEG4 0
1248
1249 #define UMC_BASE__INST1_SEG0 0x00054000
1250 #define UMC_BASE__INST1_SEG1 0x02425C00
1251 #define UMC_BASE__INST1_SEG2 0
1252 #define UMC_BASE__INST1_SEG3 0
1253 #define UMC_BASE__INST1_SEG4 0
1254
1255 #define UMC_BASE__INST2_SEG0 0
1256 #define UMC_BASE__INST2_SEG1 0
1257 #define UMC_BASE__INST2_SEG2 0
1258 #define UMC_BASE__INST2_SEG3 0
1259 #define UMC_BASE__INST2_SEG4 0
1260
1261 #define UMC_BASE__INST3_SEG0 0
1262 #define UMC_BASE__INST3_SEG1 0
1263 #define UMC_BASE__INST3_SEG2 0
1264 #define UMC_BASE__INST3_SEG3 0
1265 #define UMC_BASE__INST3_SEG4 0
1266
1267 #define UMC_BASE__INST4_SEG0 0
1268 #define UMC_BASE__INST4_SEG1 0
1269 #define UMC_BASE__INST4_SEG2 0
1270 #define UMC_BASE__INST4_SEG3 0
1271 #define UMC_BASE__INST4_SEG4 0
1272
1273 #define UMC_BASE__INST5_SEG0 0
1274 #define UMC_BASE__INST5_SEG1 0
1275 #define UMC_BASE__INST5_SEG2 0
1276 #define UMC_BASE__INST5_SEG3 0
1277 #define UMC_BASE__INST5_SEG4 0
1278
1279 #define UMC_BASE__INST6_SEG0 0
1280 #define UMC_BASE__INST6_SEG1 0
1281 #define UMC_BASE__INST6_SEG2 0
1282 #define UMC_BASE__INST6_SEG3 0
1283 #define UMC_BASE__INST6_SEG4 0
1284
1285 #define USB0_BASE__INST0_SEG0 0x0242A800
1286 #define USB0_BASE__INST0_SEG1 0x05B00000
1287 #define USB0_BASE__INST0_SEG2 0
1288 #define USB0_BASE__INST0_SEG3 0
1289 #define USB0_BASE__INST0_SEG4 0
1290
1291 #define USB0_BASE__INST1_SEG0 0
1292 #define USB0_BASE__INST1_SEG1 0
1293 #define USB0_BASE__INST1_SEG2 0
1294 #define USB0_BASE__INST1_SEG3 0
1295 #define USB0_BASE__INST1_SEG4 0
1296
1297 #define USB0_BASE__INST2_SEG0 0
1298 #define USB0_BASE__INST2_SEG1 0
1299 #define USB0_BASE__INST2_SEG2 0
1300 #define USB0_BASE__INST2_SEG3 0
1301 #define USB0_BASE__INST2_SEG4 0
1302
1303 #define USB0_BASE__INST3_SEG0 0
1304 #define USB0_BASE__INST3_SEG1 0
1305 #define USB0_BASE__INST3_SEG2 0
1306 #define USB0_BASE__INST3_SEG3 0
1307 #define USB0_BASE__INST3_SEG4 0
1308
1309 #define USB0_BASE__INST4_SEG0 0
1310 #define USB0_BASE__INST4_SEG1 0
1311 #define USB0_BASE__INST4_SEG2 0
1312 #define USB0_BASE__INST4_SEG3 0
1313 #define USB0_BASE__INST4_SEG4 0
1314
1315 #define USB0_BASE__INST5_SEG0 0
1316 #define USB0_BASE__INST5_SEG1 0
1317 #define USB0_BASE__INST5_SEG2 0
1318 #define USB0_BASE__INST5_SEG3 0
1319 #define USB0_BASE__INST5_SEG4 0
1320
1321 #define USB0_BASE__INST6_SEG0 0
1322 #define USB0_BASE__INST6_SEG1 0
1323 #define USB0_BASE__INST6_SEG2 0
1324 #define USB0_BASE__INST6_SEG3 0
1325 #define USB0_BASE__INST6_SEG4 0
1326
1327 #define UVD0_BASE__INST0_SEG0 0x00007800
1328 #define UVD0_BASE__INST0_SEG1 0x00007E00
1329 #define UVD0_BASE__INST0_SEG2 0x02403000
1330 #define UVD0_BASE__INST0_SEG3 0
1331 #define UVD0_BASE__INST0_SEG4 0
1332
1333 #define UVD0_BASE__INST1_SEG0 0
1334 #define UVD0_BASE__INST1_SEG1 0
1335 #define UVD0_BASE__INST1_SEG2 0
1336 #define UVD0_BASE__INST1_SEG3 0
1337 #define UVD0_BASE__INST1_SEG4 0
1338
1339 #define UVD0_BASE__INST2_SEG0 0
1340 #define UVD0_BASE__INST2_SEG1 0
1341 #define UVD0_BASE__INST2_SEG2 0
1342 #define UVD0_BASE__INST2_SEG3 0
1343 #define UVD0_BASE__INST2_SEG4 0
1344
1345 #define UVD0_BASE__INST3_SEG0 0
1346 #define UVD0_BASE__INST3_SEG1 0
1347 #define UVD0_BASE__INST3_SEG2 0
1348 #define UVD0_BASE__INST3_SEG3 0
1349 #define UVD0_BASE__INST3_SEG4 0
1350
1351 #define UVD0_BASE__INST4_SEG0 0
1352 #define UVD0_BASE__INST4_SEG1 0
1353 #define UVD0_BASE__INST4_SEG2 0
1354 #define UVD0_BASE__INST4_SEG3 0
1355 #define UVD0_BASE__INST4_SEG4 0
1356
1357 #define UVD0_BASE__INST5_SEG0 0
1358 #define UVD0_BASE__INST5_SEG1 0
1359 #define UVD0_BASE__INST5_SEG2 0
1360 #define UVD0_BASE__INST5_SEG3 0
1361 #define UVD0_BASE__INST5_SEG4 0
1362
1363 #define UVD0_BASE__INST6_SEG0 0
1364 #define UVD0_BASE__INST6_SEG1 0
1365 #define UVD0_BASE__INST6_SEG2 0
1366 #define UVD0_BASE__INST6_SEG3 0
1367 #define UVD0_BASE__INST6_SEG4 0
1368
1369 #define DCN_BASE__INST0_SEG0 0x00000012
1370 #define DCN_BASE__INST0_SEG1 0x000000C0
1371 #define DCN_BASE__INST0_SEG2 0x000034C0
1372 #define DCN_BASE__INST0_SEG3 0
1373 #define DCN_BASE__INST0_SEG4 0
1374
1375 #define DCN_BASE__INST1_SEG0 0
1376 #define DCN_BASE__INST1_SEG1 0
1377 #define DCN_BASE__INST1_SEG2 0
1378 #define DCN_BASE__INST1_SEG3 0
1379 #define DCN_BASE__INST1_SEG4 0
1380
1381 #define DCN_BASE__INST2_SEG0 0
1382 #define DCN_BASE__INST2_SEG1 0
1383 #define DCN_BASE__INST2_SEG2 0
1384 #define DCN_BASE__INST2_SEG3 0
1385 #define DCN_BASE__INST2_SEG4 0
1386
1387 #define DCN_BASE__INST3_SEG0 0
1388 #define DCN_BASE__INST3_SEG1 0
1389 #define DCN_BASE__INST3_SEG2 0
1390 #define DCN_BASE__INST3_SEG3 0
1391 #define DCN_BASE__INST3_SEG4 0
1392
1393 #define DCN_BASE__INST4_SEG0 0
1394 #define DCN_BASE__INST4_SEG1 0
1395 #define DCN_BASE__INST4_SEG2 0
1396 #define DCN_BASE__INST4_SEG3 0
1397 #define DCN_BASE__INST4_SEG4 0
1398 #endif
Linux with added FPC-III support