2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "ppatomctrl.h"
30 #define SMU7_MAX_HARDWARE_POWERLEVELS 2
32 #define SMU7_VOLTAGE_CONTROL_NONE 0x0
33 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1
34 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
35 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3
37 enum gpu_pt_config_reg_type
{
38 GPU_CONFIGREG_MMR
= 0,
39 GPU_CONFIGREG_SMC_IND
,
40 GPU_CONFIGREG_DIDT_IND
,
41 GPU_CONFIGREG_GC_CAC_IND
,
46 struct gpu_pt_config_reg
{
51 enum gpu_pt_config_reg_type type
;
54 struct smu7_performance_level
{
55 uint32_t memory_clock
;
56 uint32_t engine_clock
;
61 struct smu7_thermal_temperature_setting
{
63 long temperature_high
;
64 long temperature_shutdown
;
67 struct smu7_uvd_clocks
{
72 struct smu7_vce_clocks
{
77 struct smu7_power_state
{
79 struct smu7_uvd_clocks uvd_clks
;
80 struct smu7_vce_clocks vce_clks
;
82 uint16_t performance_level_count
;
84 uint32_t sclk_threshold
;
85 struct smu7_performance_level performance_levels
[SMU7_MAX_HARDWARE_POWERLEVELS
];
88 struct smu7_dpm_level
{
94 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
95 #define MAX_REGULAR_DPM_NUMBER 8
96 #define SMU7_MINIMUM_ENGINE_CLOCK 2500
98 struct smu7_single_dpm_table
{
100 struct smu7_dpm_level dpm_levels
[MAX_REGULAR_DPM_NUMBER
];
103 struct smu7_dpm_table
{
104 struct smu7_single_dpm_table sclk_table
;
105 struct smu7_single_dpm_table mclk_table
;
106 struct smu7_single_dpm_table pcie_speed_table
;
107 struct smu7_single_dpm_table vddc_table
;
108 struct smu7_single_dpm_table vddci_table
;
109 struct smu7_single_dpm_table mvdd_table
;
112 struct smu7_clock_registers
{
113 uint32_t vCG_SPLL_FUNC_CNTL
;
114 uint32_t vCG_SPLL_FUNC_CNTL_2
;
115 uint32_t vCG_SPLL_FUNC_CNTL_3
;
116 uint32_t vCG_SPLL_FUNC_CNTL_4
;
117 uint32_t vCG_SPLL_SPREAD_SPECTRUM
;
118 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2
;
120 uint32_t vMCLK_PWRMGT_CNTL
;
121 uint32_t vMPLL_AD_FUNC_CNTL
;
122 uint32_t vMPLL_DQ_FUNC_CNTL
;
123 uint32_t vMPLL_FUNC_CNTL
;
124 uint32_t vMPLL_FUNC_CNTL_1
;
125 uint32_t vMPLL_FUNC_CNTL_2
;
130 #define DISABLE_MC_LOADMICROCODE 1
131 #define DISABLE_MC_CFGPROGRAMMING 2
133 struct smu7_voltage_smio_registers
{
134 uint32_t vS0_VID_LOWER_SMIO_CNTL
;
137 #define SMU7_MAX_LEAKAGE_COUNT 8
139 struct smu7_leakage_voltage
{
141 uint16_t leakage_id
[SMU7_MAX_LEAKAGE_COUNT
];
142 uint16_t actual_voltage
[SMU7_MAX_LEAKAGE_COUNT
];
145 struct smu7_vbios_boot_state
{
146 uint16_t mvdd_bootup_value
;
147 uint16_t vddc_bootup_value
;
148 uint16_t vddci_bootup_value
;
149 uint16_t vddgfx_bootup_value
;
150 uint32_t sclk_bootup_value
;
151 uint32_t mclk_bootup_value
;
152 uint16_t pcie_gen_bootup_value
;
153 uint16_t pcie_lane_bootup_value
;
156 struct smu7_display_timing
{
157 uint32_t min_clock_in_sr
;
158 uint32_t num_existing_displays
;
162 struct smu7_dpmlevel_enable_mask
{
163 uint32_t uvd_dpm_enable_mask
;
164 uint32_t vce_dpm_enable_mask
;
165 uint32_t acp_dpm_enable_mask
;
166 uint32_t samu_dpm_enable_mask
;
167 uint32_t sclk_dpm_enable_mask
;
168 uint32_t mclk_dpm_enable_mask
;
169 uint32_t pcie_dpm_enable_mask
;
172 struct smu7_pcie_perf_range
{
177 struct smu7_odn_clock_voltage_dependency_table
{
179 phm_ppt_v1_clock_voltage_dependency_record entries
[MAX_REGULAR_DPM_NUMBER
];
182 struct smu7_odn_dpm_table
{
183 struct phm_odn_clock_levels odn_core_clock_dpm_levels
;
184 struct phm_odn_clock_levels odn_memory_clock_dpm_levels
;
185 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk
;
186 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk
;
187 uint32_t odn_mclk_min_limit
;
192 struct profile_mode_setting
{
193 uint8_t bupdate_sclk
;
194 uint8_t sclk_up_hyst
;
195 uint8_t sclk_down_hyst
;
196 uint16_t sclk_activity
;
197 uint8_t bupdate_mclk
;
198 uint8_t mclk_up_hyst
;
199 uint8_t mclk_down_hyst
;
200 uint16_t mclk_activity
;
204 struct smu7_dpm_table dpm_table
;
205 struct smu7_dpm_table golden_dpm_table
;
206 struct smu7_odn_dpm_table odn_dpm_table
;
208 uint32_t voting_rights_clients
[8];
209 uint32_t static_screen_threshold_unit
;
210 uint32_t static_screen_threshold
;
211 uint32_t voltage_control
;
212 uint32_t vdd_gfx_control
;
213 uint32_t vddc_vddgfx_delta
;
214 uint32_t active_auto_throttle_sources
;
216 struct smu7_clock_registers clock_registers
;
218 bool is_memory_gddr5
;
220 bool pspp_notify_required
;
221 uint16_t force_pcie_gen
;
222 uint16_t acpi_pcie_gen
;
223 uint32_t pcie_gen_cap
;
224 uint32_t pcie_lane_cap
;
225 uint32_t pcie_spc_cap
;
226 struct smu7_leakage_voltage vddc_leakage
;
227 struct smu7_leakage_voltage vddci_leakage
;
228 struct smu7_leakage_voltage vddcgfx_leakage
;
230 uint32_t mvdd_control
;
231 uint32_t vddc_mask_low
;
232 uint32_t mvdd_mask_low
;
233 uint16_t max_vddc_in_pptable
;
234 uint16_t min_vddc_in_pptable
;
235 uint16_t max_vddci_in_pptable
;
236 uint16_t min_vddci_in_pptable
;
238 struct smu7_vbios_boot_state vbios_boot_state
;
240 bool pcie_performance_request
;
243 bool disable_handshake
;
244 bool smc_voltage_control_enabled
;
245 bool vbi_time_out_support
;
247 uint32_t soft_regs_start
;
248 /* ---- Stuff originally coming from Evergreen ---- */
249 uint32_t vddci_control
;
250 struct pp_atomctrl_voltage_table vddc_voltage_table
;
251 struct pp_atomctrl_voltage_table vddci_voltage_table
;
252 struct pp_atomctrl_voltage_table mvdd_voltage_table
;
253 struct pp_atomctrl_voltage_table vddgfx_voltage_table
;
255 uint32_t mgcg_cgtt_local2
;
256 uint32_t mgcg_cgtt_local3
;
258 uint32_t mc_micro_code_feature
;
259 uint32_t highest_mclk
;
261 uint8_t mvdd_high_index
;
262 uint8_t mvdd_low_index
;
264 bool performance_request_registered
;
266 /* ---- Low Power Features ---- */
269 /* ---- CAC Stuff ---- */
270 uint32_t cac_table_start
;
271 bool cac_configuration_required
;
272 bool driver_calculate_cac_leakage
;
275 /* ---- DPM2 Parameters ---- */
276 uint32_t power_containment_features
;
277 bool enable_dte_feature
;
278 bool enable_tdc_limit_feature
;
279 bool enable_pkg_pwr_tracking_feature
;
280 bool disable_uvd_power_tune_feature
;
283 uint32_t dte_tj_offset
;
284 uint32_t fast_watermark_threshold
;
286 /* ---- Phase Shedding ---- */
287 uint8_t vddc_phase_shed_control
;
289 /* ---- DI/DT ---- */
290 struct smu7_display_timing display_timing
;
292 /* ---- Thermal Temperature Setting ---- */
293 struct smu7_thermal_temperature_setting thermal_temp_setting
;
294 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask
;
295 uint32_t need_update_smu7_dpm_table
;
296 uint32_t sclk_dpm_key_disabled
;
297 uint32_t mclk_dpm_key_disabled
;
298 uint32_t pcie_dpm_key_disabled
;
299 uint32_t min_engine_clocks
;
300 struct smu7_pcie_perf_range pcie_gen_performance
;
301 struct smu7_pcie_perf_range pcie_lane_performance
;
302 struct smu7_pcie_perf_range pcie_gen_power_saving
;
303 struct smu7_pcie_perf_range pcie_lane_power_saving
;
304 bool use_pcie_performance_levels
;
305 bool use_pcie_power_saving_levels
;
306 uint32_t mclk_dpm0_activity_target
;
307 uint32_t low_sclk_interrupt_threshold
;
308 uint32_t last_mclk_dpm_enable_mask
;
311 /* ---- Power Gating States ---- */
312 bool uvd_power_gated
;
313 bool vce_power_gated
;
314 bool need_long_memory_training
;
316 /* Application power optimization parameters */
318 bool update_down_hyst
;
321 uint32_t disable_dpm_mask
;
322 bool apply_optimized_settings
;
324 uint32_t avfs_vdroop_override_setting
;
325 bool apply_avfs_cks_off_voltage
;
326 uint32_t frame_time_x2
;
327 uint16_t mem_latency_high
;
328 uint16_t mem_latency_low
;
330 struct profile_mode_setting current_profile_setting
;
333 /* To convert to Q8.8 format for firmware */
334 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256
336 enum SMU7_I2CLineID
{
337 SMU7_I2CLineID_DDC1
= 0x90,
338 SMU7_I2CLineID_DDC2
= 0x91,
339 SMU7_I2CLineID_DDC3
= 0x92,
340 SMU7_I2CLineID_DDC4
= 0x93,
341 SMU7_I2CLineID_DDC5
= 0x94,
342 SMU7_I2CLineID_DDC6
= 0x95,
343 SMU7_I2CLineID_SCLSDA
= 0x96,
344 SMU7_I2CLineID_DDCVGA
= 0x97
347 #define SMU7_I2C_DDC1DATA 0
348 #define SMU7_I2C_DDC1CLK 1
349 #define SMU7_I2C_DDC2DATA 2
350 #define SMU7_I2C_DDC2CLK 3
351 #define SMU7_I2C_DDC3DATA 4
352 #define SMU7_I2C_DDC3CLK 5
353 #define SMU7_I2C_SDA 40
354 #define SMU7_I2C_SCL 41
355 #define SMU7_I2C_DDC4DATA 65
356 #define SMU7_I2C_DDC4CLK 66
357 #define SMU7_I2C_DDC5DATA 0x48
358 #define SMU7_I2C_DDC5CLK 0x49
359 #define SMU7_I2C_DDC6DATA 0x4a
360 #define SMU7_I2C_DDC6CLK 0x4b
361 #define SMU7_I2C_DDCVGADATA 0x4c
362 #define SMU7_I2C_DDCVGACLK 0x4d
364 #define SMU7_UNUSED_GPIO_PIN 0x7F
365 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock
,
366 uint32_t clock_insr
);