drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "soc15.h"
  25 #include "soc15_hw_ip.h"
  26 #include "soc15_common.h"
  27 #include "vega20_inc.h"
  28 #include "vega20_ppsmc.h"
  29 #include "vega20_baco.h"
  30 #include "vega20_smumgr.h"
  31
  32 #include "amdgpu_ras.h"
  33
  34 static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
  35 {
  36         {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
  37         {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
  38 };
  39
  40 int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
  41 {
  42         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
  43         uint32_t reg;
  44
  45         *cap = false;
  46         if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
  47                 return 0;
  48
  49         if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
  50                 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
  51
  52                 if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
  53                         *cap = true;
  54         }
  55
  56         return 0;
  57 }
  58
  59 int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
  60 {
  61         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
  62         uint32_t reg;
  63
  64         reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
  65
  66         if (reg & BACO_CNTL__BACO_MODE_MASK)
  67                 /* gfx has already entered BACO state */
  68                 *state = BACO_STATE_IN;
  69         else
  70                 *state = BACO_STATE_OUT;
  71         return 0;
  72 }
  73
  74 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
  75 {
  76         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
  77         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
  78         enum BACO_STATE cur_state;
  79         uint32_t data;
  80
  81         vega20_baco_get_state(hwmgr, &cur_state);
  82
  83         if (cur_state == state)
  84                 /* aisc already in the target state */
  85                 return 0;
  86
  87         if (state == BACO_STATE_IN) {
  88                 if (!ras || !ras->supported) {
  89                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
  90                         data |= 0x80000000;
  91                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
  92
  93                         if(smum_send_msg_to_smc_with_parameter(hwmgr,
  94                                         PPSMC_MSG_EnterBaco, 0))
  95                                 return -EINVAL;
  96                 } else {
  97                         if(smum_send_msg_to_smc_with_parameter(hwmgr,
  98                                         PPSMC_MSG_EnterBaco, 1))
  99                                 return -EINVAL;
 100                 }
 101
 102         } else if (state == BACO_STATE_OUT) {
 103                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
 104                         return -EINVAL;
 105                 if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
 106                                                      ARRAY_SIZE(clean_baco_tbl)))
 107                         return -EINVAL;
 108         }
 109
 110         return 0;
 111 }
 112
 113 int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
 114 {
 115         int ret = 0;
 116
 117         ret = vega20_set_pptable_driver_address(hwmgr);
 118         if (ret)
 119                 return ret;
 120
 121         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI);
 122 }