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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / powerplay / inc / amdgpu_smu.h
blobb0591a8dda411507f041c2cc02e3040565040eb9
1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
24
25 #include "amdgpu.h"
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
30
31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34
35 struct smu_hw_power_state {
36 unsigned int magic;
37 };
38
39 struct smu_power_state;
40
41 enum smu_state_ui_label {
42 SMU_STATE_UI_LABEL_NONE,
43 SMU_STATE_UI_LABEL_BATTERY,
44 SMU_STATE_UI_TABEL_MIDDLE_LOW,
45 SMU_STATE_UI_LABEL_BALLANCED,
46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
47 SMU_STATE_UI_LABEL_PERFORMANCE,
48 SMU_STATE_UI_LABEL_BACO,
49 };
50
51 enum smu_state_classification_flag {
52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
73 };
74
75 struct smu_state_classification_block {
76 enum smu_state_ui_label ui_label;
77 enum smu_state_classification_flag flags;
78 int bios_index;
79 bool temporary_state;
80 bool to_be_deleted;
81 };
82
83 struct smu_state_pcie_block {
84 unsigned int lanes;
85 };
86
87 enum smu_refreshrate_source {
88 SMU_REFRESHRATE_SOURCE_EDID,
89 SMU_REFRESHRATE_SOURCE_EXPLICIT
90 };
91
92 struct smu_state_display_block {
93 bool disable_frame_modulation;
94 bool limit_refreshrate;
95 enum smu_refreshrate_source refreshrate_source;
96 int explicit_refreshrate;
97 int edid_refreshrate_index;
98 bool enable_vari_bright;
99 };
100
101 struct smu_state_memroy_block {
102 bool dll_off;
103 uint8_t m3arb;
104 uint8_t unused[3];
105 };
106
107 struct smu_state_software_algorithm_block {
108 bool disable_load_balancing;
109 bool enable_sleep_for_timestamps;
110 };
111
112 struct smu_temperature_range {
113 int min;
114 int max;
115 int edge_emergency_max;
116 int hotspot_min;
117 int hotspot_crit_max;
118 int hotspot_emergency_max;
119 int mem_min;
120 int mem_crit_max;
121 int mem_emergency_max;
122 };
123
124 struct smu_state_validation_block {
125 bool single_display_only;
126 bool disallow_on_dc;
127 uint8_t supported_power_levels;
128 };
129
130 struct smu_uvd_clocks {
131 uint32_t vclk;
132 uint32_t dclk;
133 };
134
135 /**
136 * Structure to hold a SMU Power State.
137 */
138 struct smu_power_state {
139 uint32_t id;
140 struct list_head ordered_list;
141 struct list_head all_states_list;
142
143 struct smu_state_classification_block classification;
144 struct smu_state_validation_block validation;
145 struct smu_state_pcie_block pcie;
146 struct smu_state_display_block display;
147 struct smu_state_memroy_block memory;
148 struct smu_temperature_range temperatures;
149 struct smu_state_software_algorithm_block software;
150 struct smu_uvd_clocks uvd_clocks;
151 struct smu_hw_power_state hardware;
152 };
153
154 enum smu_power_src_type
155 {
156 SMU_POWER_SOURCE_AC,
157 SMU_POWER_SOURCE_DC,
158 SMU_POWER_SOURCE_COUNT,
159 };
160
161 enum smu_memory_pool_size
162 {
163 SMU_MEMORY_POOL_SIZE_ZERO = 0,
164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
168 };
169
170 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
171 do { \
172 tables[table_id].size = s; \
173 tables[table_id].align = a; \
174 tables[table_id].domain = d; \
175 } while (0)
176
177 struct smu_table {
178 uint64_t size;
179 uint32_t align;
180 uint8_t domain;
181 uint64_t mc_address;
182 void *cpu_addr;
183 struct amdgpu_bo *bo;
184 };
185
186 enum smu_perf_level_designation {
187 PERF_LEVEL_ACTIVITY,
188 PERF_LEVEL_POWER_CONTAINMENT,
189 };
190
191 struct smu_performance_level {
192 uint32_t core_clock;
193 uint32_t memory_clock;
194 uint32_t vddc;
195 uint32_t vddci;
196 uint32_t non_local_mem_freq;
197 uint32_t non_local_mem_width;
198 };
199
200 struct smu_clock_info {
201 uint32_t min_mem_clk;
202 uint32_t max_mem_clk;
203 uint32_t min_eng_clk;
204 uint32_t max_eng_clk;
205 uint32_t min_bus_bandwidth;
206 uint32_t max_bus_bandwidth;
207 };
208
209 struct smu_bios_boot_up_values
210 {
211 uint32_t revision;
212 uint32_t gfxclk;
213 uint32_t uclk;
214 uint32_t socclk;
215 uint32_t dcefclk;
216 uint32_t eclk;
217 uint32_t vclk;
218 uint32_t dclk;
219 uint16_t vddc;
220 uint16_t vddci;
221 uint16_t mvddc;
222 uint16_t vdd_gfx;
223 uint8_t cooling_id;
224 uint32_t pp_table_id;
225 uint32_t format_revision;
226 uint32_t content_revision;
227 uint32_t fclk;
228 };
229
230 enum smu_table_id
231 {
232 SMU_TABLE_PPTABLE = 0,
233 SMU_TABLE_WATERMARKS,
234 SMU_TABLE_CUSTOM_DPM,
235 SMU_TABLE_DPMCLOCKS,
236 SMU_TABLE_AVFS,
237 SMU_TABLE_AVFS_PSM_DEBUG,
238 SMU_TABLE_AVFS_FUSE_OVERRIDE,
239 SMU_TABLE_PMSTATUSLOG,
240 SMU_TABLE_SMU_METRICS,
241 SMU_TABLE_DRIVER_SMU_CONFIG,
242 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
243 SMU_TABLE_OVERDRIVE,
244 SMU_TABLE_I2C_COMMANDS,
245 SMU_TABLE_PACE,
246 SMU_TABLE_COUNT,
247 };
248
249 struct smu_table_context
250 {
251 void *power_play_table;
252 uint32_t power_play_table_size;
253 void *hardcode_pptable;
254 unsigned long metrics_time;
255 void *metrics_table;
256 void *clocks_table;
257 void *watermarks_table;
258
259 void *max_sustainable_clocks;
260 struct smu_bios_boot_up_values boot_values;
261 void *driver_pptable;
262 struct smu_table *tables;
263 /*
264 * The driver table is just a staging buffer for
265 * uploading/downloading content from the SMU.
266 *
267 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
268 * SMU_MSG_TransferTableDram2Smu instructs SMU
269 * which content driver is interested.
270 */
271 struct smu_table driver_table;
272 struct smu_table memory_pool;
273 uint8_t thermal_controller_type;
274
275 void *overdrive_table;
276 };
277
278 struct smu_dpm_context {
279 uint32_t dpm_context_size;
280 void *dpm_context;
281 void *golden_dpm_context;
282 bool enable_umd_pstate;
283 enum amd_dpm_forced_level dpm_level;
284 enum amd_dpm_forced_level saved_dpm_level;
285 enum amd_dpm_forced_level requested_dpm_level;
286 struct smu_power_state *dpm_request_power_state;
287 struct smu_power_state *dpm_current_power_state;
288 struct mclock_latency_table *mclk_latency_table;
289 };
290
291 struct smu_power_gate {
292 bool uvd_gated;
293 bool vce_gated;
294 bool vcn_gated;
295 bool jpeg_gated;
296 };
297
298 struct smu_power_context {
299 void *power_context;
300 uint32_t power_context_size;
301 struct smu_power_gate power_gate;
302 };
303
304
305 #define SMU_FEATURE_MAX (64)
306 struct smu_feature
307 {
308 uint32_t feature_num;
309 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
310 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
311 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
312 struct mutex mutex;
313 };
314
315 struct smu_clocks {
316 uint32_t engine_clock;
317 uint32_t memory_clock;
318 uint32_t bus_bandwidth;
319 uint32_t engine_clock_in_sr;
320 uint32_t dcef_clock;
321 uint32_t dcef_clock_in_sr;
322 };
323
324 #define MAX_REGULAR_DPM_NUM 16
325 struct mclk_latency_entries {
326 uint32_t frequency;
327 uint32_t latency;
328 };
329 struct mclock_latency_table {
330 uint32_t count;
331 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
332 };
333
334 enum smu_reset_mode
335 {
336 SMU_RESET_MODE_0,
337 SMU_RESET_MODE_1,
338 SMU_RESET_MODE_2,
339 };
340
341 enum smu_baco_state
342 {
343 SMU_BACO_STATE_ENTER = 0,
344 SMU_BACO_STATE_EXIT,
345 };
346
347 struct smu_baco_context
348 {
349 struct mutex mutex;
350 uint32_t state;
351 bool platform_support;
352 };
353
354 #define WORKLOAD_POLICY_MAX 7
355 struct smu_context
356 {
357 struct amdgpu_device *adev;
358 struct amdgpu_irq_src *irq_source;
359
360 const struct pptable_funcs *ppt_funcs;
361 struct mutex mutex;
362 struct mutex sensor_lock;
363 struct mutex metrics_lock;
364 uint64_t pool_size;
365
366 struct smu_table_context smu_table;
367 struct smu_dpm_context smu_dpm;
368 struct smu_power_context smu_power;
369 struct smu_feature smu_feature;
370 struct amd_pp_display_configuration *display_config;
371 struct smu_baco_context smu_baco;
372 void *od_settings;
373
374 uint32_t pstate_sclk;
375 uint32_t pstate_mclk;
376
377 bool od_enabled;
378 uint32_t power_limit;
379 uint32_t default_power_limit;
380
381 /* soft pptable */
382 uint32_t ppt_offset_bytes;
383 uint32_t ppt_size_bytes;
384 uint8_t *ppt_start_addr;
385
386 bool support_power_containment;
387 bool disable_watermark;
388
389 #define WATERMARKS_EXIST (1 << 0)
390 #define WATERMARKS_LOADED (1 << 1)
391 uint32_t watermarks_bitmap;
392 uint32_t hard_min_uclk_req_from_dal;
393 bool disable_uclk_switch;
394
395 uint32_t workload_mask;
396 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
397 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
398 uint32_t power_profile_mode;
399 uint32_t default_power_profile_mode;
400 bool pm_enabled;
401 bool is_apu;
402
403 uint32_t smc_if_version;
404
405 bool uploading_custom_pp_table;
406 };
407
408 struct i2c_adapter;
409
410 struct pptable_funcs {
411 int (*alloc_dpm_context)(struct smu_context *smu);
412 int (*store_powerplay_table)(struct smu_context *smu);
413 int (*check_powerplay_table)(struct smu_context *smu);
414 int (*append_powerplay_table)(struct smu_context *smu);
415 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
416 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
417 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
418 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
419 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
420 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
421 int (*run_btc)(struct smu_context *smu);
422 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
423 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
424 int (*set_default_dpm_table)(struct smu_context *smu);
425 int (*set_power_state)(struct smu_context *smu);
426 int (*populate_umd_state_clk)(struct smu_context *smu);
427 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
428 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
429 int (*set_default_od8_settings)(struct smu_context *smu);
430 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
431 int (*set_od_percentage)(struct smu_context *smu,
432 enum smu_clk_type clk_type,
433 uint32_t value);
434 int (*od_edit_dpm_table)(struct smu_context *smu,
435 enum PP_OD_DPM_TABLE_COMMAND type,
436 long *input, uint32_t size);
437 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
438 enum smu_clk_type clk_type,
439 struct
440 pp_clock_levels_with_latency
441 *clocks);
442 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
443 enum amd_pp_clock_type type,
444 struct
445 pp_clock_levels_with_voltage
446 *clocks);
447 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
448 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
449 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
450 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
451 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
452 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
453 void *data, uint32_t *size);
454 int (*pre_display_config_changed)(struct smu_context *smu);
455 int (*display_config_changed)(struct smu_context *smu);
456 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
457 int (*notify_smc_display_config)(struct smu_context *smu);
458 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
459 int (*unforce_dpm_levels)(struct smu_context *smu);
460 int (*get_profiling_clk_mask)(struct smu_context *smu,
461 enum amd_dpm_forced_level level,
462 uint32_t *sclk_mask,
463 uint32_t *mclk_mask,
464 uint32_t *soc_mask);
465 int (*set_cpu_power_state)(struct smu_context *smu);
466 bool (*is_dpm_running)(struct smu_context *smu);
467 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
468 int (*set_thermal_fan_table)(struct smu_context *smu);
469 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
470 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
471 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
472 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
473 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
474 enum smu_clk_type clk_type,
475 uint32_t *value);
476 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
477 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
478 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
479 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
480 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
481 void (*dump_pptable)(struct smu_context *smu);
482 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
483 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
484 uint32_t dpm_level, uint32_t *freq);
485 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
486 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
487 int (*i2c_eeprom_init)(struct i2c_adapter *control);
488 void (*i2c_eeprom_fini)(struct i2c_adapter *control);
489 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
490 int (*init_microcode)(struct smu_context *smu);
491 int (*load_microcode)(struct smu_context *smu);
492 int (*init_smc_tables)(struct smu_context *smu);
493 int (*fini_smc_tables)(struct smu_context *smu);
494 int (*init_power)(struct smu_context *smu);
495 int (*fini_power)(struct smu_context *smu);
496 int (*check_fw_status)(struct smu_context *smu);
497 int (*setup_pptable)(struct smu_context *smu);
498 int (*get_vbios_bootup_values)(struct smu_context *smu);
499 int (*get_clk_info_from_vbios)(struct smu_context *smu);
500 int (*check_pptable)(struct smu_context *smu);
501 int (*parse_pptable)(struct smu_context *smu);
502 int (*populate_smc_tables)(struct smu_context *smu);
503 int (*check_fw_version)(struct smu_context *smu);
504 int (*powergate_sdma)(struct smu_context *smu, bool gate);
505 int (*powergate_vcn)(struct smu_context *smu, bool gate);
506 int (*powergate_jpeg)(struct smu_context *smu, bool gate);
507 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
508 int (*write_pptable)(struct smu_context *smu);
509 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
510 int (*set_driver_table_location)(struct smu_context *smu);
511 int (*set_tool_table_location)(struct smu_context *smu);
512 int (*notify_memory_pool_location)(struct smu_context *smu);
513 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
514 int (*system_features_control)(struct smu_context *smu, bool en);
515 int (*send_smc_msg_with_param)(struct smu_context *smu,
516 enum smu_message_type msg, uint32_t param);
517 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
518 int (*init_display_count)(struct smu_context *smu, uint32_t count);
519 int (*set_allowed_mask)(struct smu_context *smu);
520 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
521 int (*notify_display_change)(struct smu_context *smu);
522 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
523 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
524 int (*init_max_sustainable_clocks)(struct smu_context *smu);
525 int (*start_thermal_control)(struct smu_context *smu);
526 int (*stop_thermal_control)(struct smu_context *smu);
527 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
528 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
529 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
530 bool cc6_disable, bool pstate_disable,
531 bool pstate_switch_disable);
532 int (*get_clock_by_type)(struct smu_context *smu,
533 enum amd_pp_clock_type type,
534 struct amd_pp_clocks *clocks);
535 int (*get_max_high_clocks)(struct smu_context *smu,
536 struct amd_pp_simple_clock_info *clocks);
537 int (*display_clock_voltage_request)(struct smu_context *smu, struct
538 pp_display_clock_request
539 *clock_req);
540 int (*get_dal_power_level)(struct smu_context *smu,
541 struct amd_pp_simple_clock_info *clocks);
542 int (*get_perf_level)(struct smu_context *smu,
543 enum smu_perf_level_designation designation,
544 struct smu_performance_level *level);
545 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
546 struct smu_clock_info *clocks);
547 int (*notify_smu_enable_pwe)(struct smu_context *smu);
548 int (*conv_power_profile_to_pplib_workload)(int power_profile);
549 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
550 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
551 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
552 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
553 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
554 int (*gfx_off_control)(struct smu_context *smu, bool enable);
555 int (*register_irq_handler)(struct smu_context *smu);
556 int (*set_azalia_d3_pme)(struct smu_context *smu);
557 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
558 bool (*baco_is_support)(struct smu_context *smu);
559 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
560 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
561 int (*baco_enter)(struct smu_context *smu);
562 int (*baco_exit)(struct smu_context *smu);
563 int (*mode2_reset)(struct smu_context *smu);
564 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
565 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
566 int (*override_pcie_parameters)(struct smu_context *smu);
567 uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
568 };
569
570 int smu_load_microcode(struct smu_context *smu);
571
572 int smu_check_fw_status(struct smu_context *smu);
573
574 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
575
576 #define smu_i2c_eeprom_init(smu, control) \
577 ((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL)
578 #define smu_i2c_eeprom_fini(smu, control) \
579 ((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL)
580
581 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
582
583 int smu_get_power_limit(struct smu_context *smu,
584 uint32_t *limit,
585 bool def,
586 bool lock_needed);
587
588 int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
589 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
590 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
591 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
592
593 int smu_od_edit_dpm_table(struct smu_context *smu,
594 enum PP_OD_DPM_TABLE_COMMAND type,
595 long *input, uint32_t size);
596
597 int smu_read_sensor(struct smu_context *smu,
598 enum amd_pp_sensors sensor,
599 void *data, uint32_t *size);
600 int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
601
602 int smu_set_power_profile_mode(struct smu_context *smu,
603 long *param,
604 uint32_t param_size,
605 bool lock_needed);
606 int smu_get_fan_control_mode(struct smu_context *smu);
607 int smu_set_fan_control_mode(struct smu_context *smu, int value);
608 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
609 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
610 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
611
612 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
613 int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
614
615 int smu_get_clock_by_type(struct smu_context *smu,
616 enum amd_pp_clock_type type,
617 struct amd_pp_clocks *clocks);
618
619 int smu_get_max_high_clocks(struct smu_context *smu,
620 struct amd_pp_simple_clock_info *clocks);
621
622 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
623 enum smu_clk_type clk_type,
624 struct pp_clock_levels_with_latency *clocks);
625
626 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
627 enum amd_pp_clock_type type,
628 struct pp_clock_levels_with_voltage *clocks);
629
630 int smu_display_clock_voltage_request(struct smu_context *smu,
631 struct pp_display_clock_request *clock_req);
632 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
633 int smu_notify_smu_enable_pwe(struct smu_context *smu);
634
635 int smu_set_xgmi_pstate(struct smu_context *smu,
636 uint32_t pstate);
637
638 int smu_set_azalia_d3_pme(struct smu_context *smu);
639
640 bool smu_baco_is_support(struct smu_context *smu);
641
642 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
643
644 int smu_baco_enter(struct smu_context *smu);
645 int smu_baco_exit(struct smu_context *smu);
646
647 int smu_mode2_reset(struct smu_context *smu);
648
649 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
650 uint16_t *size, uint8_t *frev, uint8_t *crev,
651 uint8_t **addr);
652
653 extern const struct amd_ip_funcs smu_ip_funcs;
654
655 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
656 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
657
658 extern int smu_feature_init_dpm(struct smu_context *smu);
659
660 extern int smu_feature_is_enabled(struct smu_context *smu,
661 enum smu_feature_mask mask);
662 extern int smu_feature_set_enabled(struct smu_context *smu,
663 enum smu_feature_mask mask, bool enable);
664 extern int smu_feature_is_supported(struct smu_context *smu,
665 enum smu_feature_mask mask);
666 extern int smu_feature_set_supported(struct smu_context *smu,
667 enum smu_feature_mask mask, bool enable);
668
669 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
670 void *table_data, bool drv2smu);
671
672 bool is_support_sw_smu(struct amdgpu_device *adev);
673 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
674 int smu_reset(struct smu_context *smu);
675 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
676 void *data, uint32_t *size);
677 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
678 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
679 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
680 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
681 int smu_write_watermarks_table(struct smu_context *smu);
682 int smu_set_watermarks_for_clock_ranges(
683 struct smu_context *smu,
684 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
685
686 /* smu to display interface */
687 extern int smu_display_configuration_change(struct smu_context *smu, const
688 struct amd_pp_display_configuration
689 *display_config);
690 extern int smu_get_current_clocks(struct smu_context *smu,
691 struct amd_pp_clock_info *clocks);
692 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
693 extern int smu_handle_task(struct smu_context *smu,
694 enum amd_dpm_forced_level level,
695 enum amd_pp_task task_id,
696 bool lock_needed);
697 int smu_switch_power_profile(struct smu_context *smu,
698 enum PP_SMC_POWER_PROFILE type,
699 bool en);
700 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
701 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
702 uint16_t level, uint32_t *value);
703 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
704 uint32_t *value);
705 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
706 uint32_t *min, uint32_t *max, bool lock_needed);
707 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
708 uint32_t min, uint32_t max);
709 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
710 uint32_t min, uint32_t max);
711 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
712 uint32_t *min_value, uint32_t *max_value);
713 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
714 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
715 int smu_set_display_count(struct smu_context *smu, uint32_t count);
716 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
717 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
718 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
719 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
720 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
721 int smu_force_clk_levels(struct smu_context *smu,
722 enum smu_clk_type clk_type,
723 uint32_t mask,
724 bool lock_needed);
725 int smu_set_mp1_state(struct smu_context *smu,
726 enum pp_mp1_state mp1_state);
727 int smu_set_df_cstate(struct smu_context *smu,
728 enum pp_df_cstate state);
729
730 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
731 struct pp_smu_nv_clock_table *max_clocks);
732
733 int smu_get_uclk_dpm_states(struct smu_context *smu,
734 unsigned int *clock_values_in_khz,
735 unsigned int *num_states);
736
737 int smu_get_dpm_clock_table(struct smu_context *smu,
738 struct dpm_clocks *clock_table);
739
740 uint32_t smu_get_pptable_power_limit(struct smu_context *smu);
741
742 #endif
Linux with added FPC-III support