drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __SMU_V12_0_H__
  24 #define __SMU_V12_0_H__
  25
  26 #include "amdgpu_smu.h"
  27
  28 /* MP Apertures */
  29 #define MP0_Public                      0x03800000
  30 #define MP0_SRAM                        0x03900000
  31 #define MP1_Public                      0x03b00000
  32 #define MP1_SRAM                        0x03c00004
  33
  34
  35 struct smu_12_0_cmn2aisc_mapping {
  36         int     valid_mapping;
  37         int     map_to;
  38 };
  39
  40 int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
  41                                               uint16_t msg);
  42
  43 int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
  44
  45 int smu_v12_0_wait_for_response(struct smu_context *smu);
  46
  47 int
  48 smu_v12_0_send_msg_with_param(struct smu_context *smu,
  49                               enum smu_message_type msg,
  50                               uint32_t param);
  51
  52 int smu_v12_0_check_fw_status(struct smu_context *smu);
  53
  54 int smu_v12_0_check_fw_version(struct smu_context *smu);
  55
  56 int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
  57
  58 int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
  59
  60 int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
  61
  62 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
  63
  64 int smu_v12_0_read_sensor(struct smu_context *smu,
  65                           enum amd_pp_sensors sensor,
  66                           void *data, uint32_t *size);
  67
  68 uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
  69
  70 int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
  71
  72 int smu_v12_0_init_smc_tables(struct smu_context *smu);
  73
  74 int smu_v12_0_fini_smc_tables(struct smu_context *smu);
  75
  76 int smu_v12_0_populate_smc_tables(struct smu_context *smu);
  77
  78 int smu_v12_0_get_enabled_mask(struct smu_context *smu,
  79                                       uint32_t *feature_mask, uint32_t num);
  80
  81 int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
  82                                           enum smu_clk_type clk_id,
  83                                           uint32_t *value);
  84
  85 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
  86                                                  uint32_t *min, uint32_t *max);
  87
  88 int smu_v12_0_mode2_reset(struct smu_context *smu);
  89
  90 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
  91                             uint32_t min, uint32_t max);
  92
  93 int smu_v12_0_set_driver_table_location(struct smu_context *smu);
  94
  95 #endif