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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / powerplay / smu_v11_0.c
blob02f8c9cb89d9f0df3ace9093cccb9b9a56d2c25d
1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26
27 #define SMU_11_0_PARTIAL_PPTABLE
28
29 #include "pp_debug.h"
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "smu_v11_0.h"
36 #include "smu_v11_0_pptable.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amd_pcie.h"
40 #include "amdgpu_ras.h"
41
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/nbio/nbio_7_4_offset.h"
47 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
48 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
49 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50
51 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
52 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
53 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
54 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
55 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
56
57 #define SMU11_VOLTAGE_SCALE 4
58
59 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
60 uint16_t msg)
61 {
62 struct amdgpu_device *adev = smu->adev;
63 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
64 return 0;
65 }
66
67 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
68 {
69 struct amdgpu_device *adev = smu->adev;
70
71 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
72 return 0;
73 }
74
75 static int smu_v11_0_wait_for_response(struct smu_context *smu)
76 {
77 struct amdgpu_device *adev = smu->adev;
78 uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
79
80 for (i = 0; i < timeout; i++) {
81 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
82 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
83 return cur_value == 0x1 ? 0 : -EIO;
84
85 udelay(1);
86 }
87
88 /* timeout means wrong logic */
89 return -ETIME;
90 }
91
92 int
93 smu_v11_0_send_msg_with_param(struct smu_context *smu,
94 enum smu_message_type msg,
95 uint32_t param)
96 {
97 struct amdgpu_device *adev = smu->adev;
98 int ret = 0, index = 0;
99
100 index = smu_msg_get_index(smu, msg);
101 if (index < 0)
102 return index;
103
104 ret = smu_v11_0_wait_for_response(smu);
105 if (ret) {
106 pr_err("Msg issuing pre-check failed and "
107 "SMU may be not in the right state!\n");
108 return ret;
109 }
110
111 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
112
113 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
114
115 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
116
117 ret = smu_v11_0_wait_for_response(smu);
118 if (ret)
119 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
120 smu_get_message_name(smu, msg), index, param, ret);
121
122 return ret;
123 }
124
125 int smu_v11_0_init_microcode(struct smu_context *smu)
126 {
127 struct amdgpu_device *adev = smu->adev;
128 const char *chip_name;
129 char fw_name[30];
130 int err = 0;
131 const struct smc_firmware_header_v1_0 *hdr;
132 const struct common_firmware_header *header;
133 struct amdgpu_firmware_info *ucode = NULL;
134
135 switch (adev->asic_type) {
136 case CHIP_VEGA20:
137 chip_name = "vega20";
138 break;
139 case CHIP_ARCTURUS:
140 chip_name = "arcturus";
141 break;
142 case CHIP_NAVI10:
143 chip_name = "navi10";
144 break;
145 case CHIP_NAVI14:
146 chip_name = "navi14";
147 break;
148 case CHIP_NAVI12:
149 chip_name = "navi12";
150 break;
151 default:
152 BUG();
153 }
154
155 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
156
157 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
158 if (err)
159 goto out;
160 err = amdgpu_ucode_validate(adev->pm.fw);
161 if (err)
162 goto out;
163
164 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
165 amdgpu_ucode_print_smc_hdr(&hdr->header);
166 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
167
168 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
169 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
170 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
171 ucode->fw = adev->pm.fw;
172 header = (const struct common_firmware_header *)ucode->fw->data;
173 adev->firmware.fw_size +=
174 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
175 }
176
177 out:
178 if (err) {
179 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
180 fw_name);
181 release_firmware(adev->pm.fw);
182 adev->pm.fw = NULL;
183 }
184 return err;
185 }
186
187 int smu_v11_0_load_microcode(struct smu_context *smu)
188 {
189 struct amdgpu_device *adev = smu->adev;
190 const uint32_t *src;
191 const struct smc_firmware_header_v1_0 *hdr;
192 uint32_t addr_start = MP1_SRAM;
193 uint32_t i;
194 uint32_t mp1_fw_flags;
195
196 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
197 src = (const uint32_t *)(adev->pm.fw->data +
198 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
199
200 for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
201 WREG32_PCIE(addr_start, src[i]);
202 addr_start += 4;
203 }
204
205 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
206 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
207 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
208 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
209
210 for (i = 0; i < adev->usec_timeout; i++) {
211 mp1_fw_flags = RREG32_PCIE(MP1_Public |
212 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
213 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
214 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
215 break;
216 udelay(1);
217 }
218
219 if (i == adev->usec_timeout)
220 return -ETIME;
221
222 return 0;
223 }
224
225 int smu_v11_0_check_fw_status(struct smu_context *smu)
226 {
227 struct amdgpu_device *adev = smu->adev;
228 uint32_t mp1_fw_flags;
229
230 mp1_fw_flags = RREG32_PCIE(MP1_Public |
231 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
232
233 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
234 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
235 return 0;
236
237 return -EIO;
238 }
239
240 int smu_v11_0_check_fw_version(struct smu_context *smu)
241 {
242 uint32_t if_version = 0xff, smu_version = 0xff;
243 uint16_t smu_major;
244 uint8_t smu_minor, smu_debug;
245 int ret = 0;
246
247 ret = smu_get_smc_version(smu, &if_version, &smu_version);
248 if (ret)
249 return ret;
250
251 smu_major = (smu_version >> 16) & 0xffff;
252 smu_minor = (smu_version >> 8) & 0xff;
253 smu_debug = (smu_version >> 0) & 0xff;
254
255 switch (smu->adev->asic_type) {
256 case CHIP_VEGA20:
257 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
258 break;
259 case CHIP_ARCTURUS:
260 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
261 break;
262 case CHIP_NAVI10:
263 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
264 break;
265 case CHIP_NAVI14:
266 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
267 break;
268 default:
269 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
270 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
271 break;
272 }
273
274 /*
275 * 1. if_version mismatch is not critical as our fw is designed
276 * to be backward compatible.
277 * 2. New fw usually brings some optimizations. But that's visible
278 * only on the paired driver.
279 * Considering above, we just leave user a warning message instead
280 * of halt driver loading.
281 */
282 if (if_version != smu->smc_if_version) {
283 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
284 "smu fw version = 0x%08x (%d.%d.%d)\n",
285 smu->smc_if_version, if_version,
286 smu_version, smu_major, smu_minor, smu_debug);
287 pr_warn("SMU driver if version not matched\n");
288 }
289
290 return ret;
291 }
292
293 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
294 {
295 struct amdgpu_device *adev = smu->adev;
296 uint32_t ppt_offset_bytes;
297 const struct smc_firmware_header_v2_0 *v2;
298
299 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
300
301 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
302 *size = le32_to_cpu(v2->ppt_size_bytes);
303 *table = (uint8_t *)v2 + ppt_offset_bytes;
304
305 return 0;
306 }
307
308 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
309 uint32_t *size, uint32_t pptable_id)
310 {
311 struct amdgpu_device *adev = smu->adev;
312 const struct smc_firmware_header_v2_1 *v2_1;
313 struct smc_soft_pptable_entry *entries;
314 uint32_t pptable_count = 0;
315 int i = 0;
316
317 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
318 entries = (struct smc_soft_pptable_entry *)
319 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
320 pptable_count = le32_to_cpu(v2_1->pptable_count);
321 for (i = 0; i < pptable_count; i++) {
322 if (le32_to_cpu(entries[i].id) == pptable_id) {
323 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
324 *size = le32_to_cpu(entries[i].ppt_size_bytes);
325 break;
326 }
327 }
328
329 if (i == pptable_count)
330 return -EINVAL;
331
332 return 0;
333 }
334
335 int smu_v11_0_setup_pptable(struct smu_context *smu)
336 {
337 struct amdgpu_device *adev = smu->adev;
338 const struct smc_firmware_header_v1_0 *hdr;
339 int ret, index;
340 uint32_t size = 0;
341 uint16_t atom_table_size;
342 uint8_t frev, crev;
343 void *table;
344 uint16_t version_major, version_minor;
345
346 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
347 version_major = le16_to_cpu(hdr->header.header_version_major);
348 version_minor = le16_to_cpu(hdr->header.header_version_minor);
349 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
350 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
351 switch (version_minor) {
352 case 0:
353 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
354 break;
355 case 1:
356 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
357 smu->smu_table.boot_values.pp_table_id);
358 break;
359 default:
360 ret = -EINVAL;
361 break;
362 }
363 if (ret)
364 return ret;
365
366 } else {
367 pr_info("use vbios provided pptable\n");
368 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
369 powerplayinfo);
370
371 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
372 (uint8_t **)&table);
373 if (ret)
374 return ret;
375 size = atom_table_size;
376 }
377
378 if (!smu->smu_table.power_play_table)
379 smu->smu_table.power_play_table = table;
380 if (!smu->smu_table.power_play_table_size)
381 smu->smu_table.power_play_table_size = size;
382
383 return 0;
384 }
385
386 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
387 {
388 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
389
390 if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
391 return -EINVAL;
392
393 return smu_alloc_dpm_context(smu);
394 }
395
396 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
397 {
398 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
399
400 if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
401 return -EINVAL;
402
403 kfree(smu_dpm->dpm_context);
404 kfree(smu_dpm->golden_dpm_context);
405 kfree(smu_dpm->dpm_current_power_state);
406 kfree(smu_dpm->dpm_request_power_state);
407 smu_dpm->dpm_context = NULL;
408 smu_dpm->golden_dpm_context = NULL;
409 smu_dpm->dpm_context_size = 0;
410 smu_dpm->dpm_current_power_state = NULL;
411 smu_dpm->dpm_request_power_state = NULL;
412
413 return 0;
414 }
415
416 int smu_v11_0_init_smc_tables(struct smu_context *smu)
417 {
418 struct smu_table_context *smu_table = &smu->smu_table;
419 struct smu_table *tables = NULL;
420 int ret = 0;
421
422 if (smu_table->tables)
423 return -EINVAL;
424
425 tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
426 GFP_KERNEL);
427 if (!tables)
428 return -ENOMEM;
429
430 smu_table->tables = tables;
431
432 ret = smu_tables_init(smu, tables);
433 if (ret)
434 return ret;
435
436 ret = smu_v11_0_init_dpm_context(smu);
437 if (ret)
438 return ret;
439
440 return 0;
441 }
442
443 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
444 {
445 struct smu_table_context *smu_table = &smu->smu_table;
446 int ret = 0;
447
448 if (!smu_table->tables)
449 return -EINVAL;
450
451 kfree(smu_table->tables);
452 kfree(smu_table->metrics_table);
453 kfree(smu_table->watermarks_table);
454 smu_table->tables = NULL;
455 smu_table->metrics_table = NULL;
456 smu_table->watermarks_table = NULL;
457 smu_table->metrics_time = 0;
458
459 ret = smu_v11_0_fini_dpm_context(smu);
460 if (ret)
461 return ret;
462 return 0;
463 }
464
465 int smu_v11_0_init_power(struct smu_context *smu)
466 {
467 struct smu_power_context *smu_power = &smu->smu_power;
468
469 if (!smu->pm_enabled)
470 return 0;
471 if (smu_power->power_context || smu_power->power_context_size != 0)
472 return -EINVAL;
473
474 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
475 GFP_KERNEL);
476 if (!smu_power->power_context)
477 return -ENOMEM;
478 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
479
480 return 0;
481 }
482
483 int smu_v11_0_fini_power(struct smu_context *smu)
484 {
485 struct smu_power_context *smu_power = &smu->smu_power;
486
487 if (!smu->pm_enabled)
488 return 0;
489 if (!smu_power->power_context || smu_power->power_context_size == 0)
490 return -EINVAL;
491
492 kfree(smu_power->power_context);
493 smu_power->power_context = NULL;
494 smu_power->power_context_size = 0;
495
496 return 0;
497 }
498
499 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
500 {
501 int ret, index;
502 uint16_t size;
503 uint8_t frev, crev;
504 struct atom_common_table_header *header;
505 struct atom_firmware_info_v3_3 *v_3_3;
506 struct atom_firmware_info_v3_1 *v_3_1;
507
508 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
509 firmwareinfo);
510
511 ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
512 (uint8_t **)&header);
513 if (ret)
514 return ret;
515
516 if (header->format_revision != 3) {
517 pr_err("unknown atom_firmware_info version! for smu11\n");
518 return -EINVAL;
519 }
520
521 switch (header->content_revision) {
522 case 0:
523 case 1:
524 case 2:
525 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
526 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
527 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
528 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
529 smu->smu_table.boot_values.socclk = 0;
530 smu->smu_table.boot_values.dcefclk = 0;
531 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
532 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
533 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
534 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
535 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
536 smu->smu_table.boot_values.pp_table_id = 0;
537 break;
538 case 3:
539 default:
540 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
541 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
542 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
543 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
544 smu->smu_table.boot_values.socclk = 0;
545 smu->smu_table.boot_values.dcefclk = 0;
546 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
547 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
548 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
549 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
550 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
551 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
552 }
553
554 smu->smu_table.boot_values.format_revision = header->format_revision;
555 smu->smu_table.boot_values.content_revision = header->content_revision;
556
557 return 0;
558 }
559
560 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
561 {
562 int ret, index;
563 struct amdgpu_device *adev = smu->adev;
564 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
565 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
566
567 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
568 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
569 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
570 getsmuclockinfo);
571
572 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
573 (uint32_t *)&input);
574 if (ret)
575 return -EINVAL;
576
577 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
578 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
579
580 memset(&input, 0, sizeof(input));
581 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
582 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
583 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
584 getsmuclockinfo);
585
586 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
587 (uint32_t *)&input);
588 if (ret)
589 return -EINVAL;
590
591 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
592 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
593
594 memset(&input, 0, sizeof(input));
595 input.clk_id = SMU11_SYSPLL0_ECLK_ID;
596 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
597 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
598 getsmuclockinfo);
599
600 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
601 (uint32_t *)&input);
602 if (ret)
603 return -EINVAL;
604
605 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
606 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
607
608 memset(&input, 0, sizeof(input));
609 input.clk_id = SMU11_SYSPLL0_VCLK_ID;
610 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
611 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
612 getsmuclockinfo);
613
614 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
615 (uint32_t *)&input);
616 if (ret)
617 return -EINVAL;
618
619 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
620 smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
621
622 memset(&input, 0, sizeof(input));
623 input.clk_id = SMU11_SYSPLL0_DCLK_ID;
624 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
625 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
626 getsmuclockinfo);
627
628 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
629 (uint32_t *)&input);
630 if (ret)
631 return -EINVAL;
632
633 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
634 smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
635
636 if ((smu->smu_table.boot_values.format_revision == 3) &&
637 (smu->smu_table.boot_values.content_revision >= 2)) {
638 memset(&input, 0, sizeof(input));
639 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
640 input.syspll_id = SMU11_SYSPLL1_2_ID;
641 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
642 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
643 getsmuclockinfo);
644
645 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
646 (uint32_t *)&input);
647 if (ret)
648 return -EINVAL;
649
650 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
651 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
652 }
653
654 return 0;
655 }
656
657 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
658 {
659 struct smu_table_context *smu_table = &smu->smu_table;
660 struct smu_table *memory_pool = &smu_table->memory_pool;
661 int ret = 0;
662 uint64_t address;
663 uint32_t address_low, address_high;
664
665 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
666 return ret;
667
668 address = (uintptr_t)memory_pool->cpu_addr;
669 address_high = (uint32_t)upper_32_bits(address);
670 address_low = (uint32_t)lower_32_bits(address);
671
672 ret = smu_send_smc_msg_with_param(smu,
673 SMU_MSG_SetSystemVirtualDramAddrHigh,
674 address_high);
675 if (ret)
676 return ret;
677 ret = smu_send_smc_msg_with_param(smu,
678 SMU_MSG_SetSystemVirtualDramAddrLow,
679 address_low);
680 if (ret)
681 return ret;
682
683 address = memory_pool->mc_address;
684 address_high = (uint32_t)upper_32_bits(address);
685 address_low = (uint32_t)lower_32_bits(address);
686
687 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
688 address_high);
689 if (ret)
690 return ret;
691 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
692 address_low);
693 if (ret)
694 return ret;
695 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
696 (uint32_t)memory_pool->size);
697 if (ret)
698 return ret;
699
700 return ret;
701 }
702
703 int smu_v11_0_check_pptable(struct smu_context *smu)
704 {
705 int ret;
706
707 ret = smu_check_powerplay_table(smu);
708 return ret;
709 }
710
711 int smu_v11_0_parse_pptable(struct smu_context *smu)
712 {
713 int ret;
714
715 struct smu_table_context *table_context = &smu->smu_table;
716 struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
717
718 if (table_context->driver_pptable)
719 return -EINVAL;
720
721 table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
722
723 if (!table_context->driver_pptable)
724 return -ENOMEM;
725
726 ret = smu_store_powerplay_table(smu);
727 if (ret)
728 return -EINVAL;
729
730 ret = smu_append_powerplay_table(smu);
731
732 return ret;
733 }
734
735 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
736 {
737 int ret;
738
739 ret = smu_set_default_dpm_table(smu);
740
741 return ret;
742 }
743
744 int smu_v11_0_write_pptable(struct smu_context *smu)
745 {
746 struct smu_table_context *table_context = &smu->smu_table;
747 int ret = 0;
748
749 ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
750 table_context->driver_pptable, true);
751
752 return ret;
753 }
754
755 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
756 {
757 int ret;
758
759 ret = smu_send_smc_msg_with_param(smu,
760 SMU_MSG_SetMinDeepSleepDcefclk, clk);
761 if (ret)
762 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
763
764 return ret;
765 }
766
767 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
768 {
769 struct smu_table_context *table_context = &smu->smu_table;
770
771 if (!smu->pm_enabled)
772 return 0;
773 if (!table_context)
774 return -EINVAL;
775
776 return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
777 }
778
779 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
780 {
781 struct smu_table *driver_table = &smu->smu_table.driver_table;
782 int ret = 0;
783
784 if (driver_table->mc_address) {
785 ret = smu_send_smc_msg_with_param(smu,
786 SMU_MSG_SetDriverDramAddrHigh,
787 upper_32_bits(driver_table->mc_address));
788 if (!ret)
789 ret = smu_send_smc_msg_with_param(smu,
790 SMU_MSG_SetDriverDramAddrLow,
791 lower_32_bits(driver_table->mc_address));
792 }
793
794 return ret;
795 }
796
797 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
798 {
799 int ret = 0;
800 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
801
802 if (tool_table->mc_address) {
803 ret = smu_send_smc_msg_with_param(smu,
804 SMU_MSG_SetToolsDramAddrHigh,
805 upper_32_bits(tool_table->mc_address));
806 if (!ret)
807 ret = smu_send_smc_msg_with_param(smu,
808 SMU_MSG_SetToolsDramAddrLow,
809 lower_32_bits(tool_table->mc_address));
810 }
811
812 return ret;
813 }
814
815 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
816 {
817 int ret = 0;
818
819 if (!smu->pm_enabled)
820 return ret;
821
822 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
823 return ret;
824 }
825
826
827 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
828 {
829 struct smu_feature *feature = &smu->smu_feature;
830 int ret = 0;
831 uint32_t feature_mask[2];
832
833 mutex_lock(&feature->mutex);
834 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
835 goto failed;
836
837 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
838
839 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
840 feature_mask[1]);
841 if (ret)
842 goto failed;
843
844 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
845 feature_mask[0]);
846 if (ret)
847 goto failed;
848
849 failed:
850 mutex_unlock(&feature->mutex);
851 return ret;
852 }
853
854 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
855 uint32_t *feature_mask, uint32_t num)
856 {
857 uint32_t feature_mask_high = 0, feature_mask_low = 0;
858 struct smu_feature *feature = &smu->smu_feature;
859 int ret = 0;
860
861 if (!feature_mask || num < 2)
862 return -EINVAL;
863
864 if (bitmap_empty(feature->enabled, feature->feature_num)) {
865 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
866 if (ret)
867 return ret;
868 ret = smu_read_smc_arg(smu, &feature_mask_high);
869 if (ret)
870 return ret;
871
872 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
873 if (ret)
874 return ret;
875 ret = smu_read_smc_arg(smu, &feature_mask_low);
876 if (ret)
877 return ret;
878
879 feature_mask[0] = feature_mask_low;
880 feature_mask[1] = feature_mask_high;
881 } else {
882 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
883 feature->feature_num);
884 }
885
886 return ret;
887 }
888
889 int smu_v11_0_system_features_control(struct smu_context *smu,
890 bool en)
891 {
892 struct smu_feature *feature = &smu->smu_feature;
893 uint32_t feature_mask[2];
894 int ret = 0;
895
896 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
897 SMU_MSG_DisableAllSmuFeatures));
898 if (ret)
899 return ret;
900
901 if (en) {
902 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
903 if (ret)
904 return ret;
905
906 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
907 feature->feature_num);
908 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
909 feature->feature_num);
910 } else {
911 bitmap_zero(feature->enabled, feature->feature_num);
912 bitmap_zero(feature->supported, feature->feature_num);
913 }
914
915 return ret;
916 }
917
918 int smu_v11_0_notify_display_change(struct smu_context *smu)
919 {
920 int ret = 0;
921
922 if (!smu->pm_enabled)
923 return ret;
924 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
925 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
926 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
927
928 return ret;
929 }
930
931 static int
932 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
933 enum smu_clk_type clock_select)
934 {
935 int ret = 0;
936 int clk_id;
937
938 if (!smu->pm_enabled)
939 return ret;
940
941 if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
942 (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
943 return 0;
944
945 clk_id = smu_clk_get_index(smu, clock_select);
946 if (clk_id < 0)
947 return -EINVAL;
948
949 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
950 clk_id << 16);
951 if (ret) {
952 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
953 return ret;
954 }
955
956 ret = smu_read_smc_arg(smu, clock);
957 if (ret)
958 return ret;
959
960 if (*clock != 0)
961 return 0;
962
963 /* if DC limit is zero, return AC limit */
964 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
965 clk_id << 16);
966 if (ret) {
967 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
968 return ret;
969 }
970
971 ret = smu_read_smc_arg(smu, clock);
972
973 return ret;
974 }
975
976 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
977 {
978 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
979 int ret = 0;
980
981 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
982 GFP_KERNEL);
983 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
984
985 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
986 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
987 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
988 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
989 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
990 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
991
992 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
993 ret = smu_v11_0_get_max_sustainable_clock(smu,
994 &(max_sustainable_clocks->uclock),
995 SMU_UCLK);
996 if (ret) {
997 pr_err("[%s] failed to get max UCLK from SMC!",
998 __func__);
999 return ret;
1000 }
1001 }
1002
1003 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1004 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005 &(max_sustainable_clocks->soc_clock),
1006 SMU_SOCCLK);
1007 if (ret) {
1008 pr_err("[%s] failed to get max SOCCLK from SMC!",
1009 __func__);
1010 return ret;
1011 }
1012 }
1013
1014 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1015 ret = smu_v11_0_get_max_sustainable_clock(smu,
1016 &(max_sustainable_clocks->dcef_clock),
1017 SMU_DCEFCLK);
1018 if (ret) {
1019 pr_err("[%s] failed to get max DCEFCLK from SMC!",
1020 __func__);
1021 return ret;
1022 }
1023
1024 ret = smu_v11_0_get_max_sustainable_clock(smu,
1025 &(max_sustainable_clocks->display_clock),
1026 SMU_DISPCLK);
1027 if (ret) {
1028 pr_err("[%s] failed to get max DISPCLK from SMC!",
1029 __func__);
1030 return ret;
1031 }
1032 ret = smu_v11_0_get_max_sustainable_clock(smu,
1033 &(max_sustainable_clocks->phy_clock),
1034 SMU_PHYCLK);
1035 if (ret) {
1036 pr_err("[%s] failed to get max PHYCLK from SMC!",
1037 __func__);
1038 return ret;
1039 }
1040 ret = smu_v11_0_get_max_sustainable_clock(smu,
1041 &(max_sustainable_clocks->pixel_clock),
1042 SMU_PIXCLK);
1043 if (ret) {
1044 pr_err("[%s] failed to get max PIXCLK from SMC!",
1045 __func__);
1046 return ret;
1047 }
1048 }
1049
1050 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1051 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1052
1053 return 0;
1054 }
1055
1056 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1057 uint32_t od_limit, max_power_limit;
1058 struct smu_11_0_powerplay_table *powerplay_table = NULL;
1059 struct smu_table_context *table_context = &smu->smu_table;
1060 powerplay_table = table_context->power_play_table;
1061
1062 max_power_limit = smu_get_pptable_power_limit(smu);
1063
1064 if (!max_power_limit) {
1065 // If we couldn't get the table limit, fall back on first-read value
1066 if (!smu->default_power_limit)
1067 smu->default_power_limit = smu->power_limit;
1068 max_power_limit = smu->default_power_limit;
1069 }
1070
1071 if (smu->od_enabled) {
1072 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1073
1074 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1075
1076 max_power_limit *= (100 + od_limit);
1077 max_power_limit /= 100;
1078 }
1079
1080 return max_power_limit;
1081 }
1082
1083 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1084 {
1085 int ret = 0;
1086 uint32_t max_power_limit;
1087
1088 max_power_limit = smu_v11_0_get_max_power_limit(smu);
1089
1090 if (n > max_power_limit) {
1091 pr_err("New power limit (%d) is over the max allowed %d\n",
1092 n,
1093 max_power_limit);
1094 return -EINVAL;
1095 }
1096
1097 if (n == 0)
1098 n = smu->default_power_limit;
1099
1100 if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1101 pr_err("Setting new power limit is not supported!\n");
1102 return -EOPNOTSUPP;
1103 }
1104
1105 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1106 if (ret) {
1107 pr_err("[%s] Set power limit Failed!\n", __func__);
1108 return ret;
1109 }
1110 smu->power_limit = n;
1111
1112 return 0;
1113 }
1114
1115 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1116 enum smu_clk_type clk_id,
1117 uint32_t *value)
1118 {
1119 int ret = 0;
1120 uint32_t freq = 0;
1121 int asic_clk_id;
1122
1123 if (clk_id >= SMU_CLK_COUNT || !value)
1124 return -EINVAL;
1125
1126 asic_clk_id = smu_clk_get_index(smu, clk_id);
1127 if (asic_clk_id < 0)
1128 return -EINVAL;
1129
1130 /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1131 if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1132 ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1133 else {
1134 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1135 (asic_clk_id << 16));
1136 if (ret)
1137 return ret;
1138
1139 ret = smu_read_smc_arg(smu, &freq);
1140 if (ret)
1141 return ret;
1142 }
1143
1144 freq *= 100;
1145 *value = freq;
1146
1147 return ret;
1148 }
1149
1150 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1151 struct smu_temperature_range range)
1152 {
1153 struct amdgpu_device *adev = smu->adev;
1154 int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1155 int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1156 uint32_t val;
1157 struct smu_table_context *table_context = &smu->smu_table;
1158 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1159
1160 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1161 range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1162 high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
1163
1164 if (low > high)
1165 return -EINVAL;
1166
1167 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1168 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1169 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1170 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1171 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1172 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1173 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1174 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1175
1176 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1177
1178 return 0;
1179 }
1180
1181 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1182 {
1183 struct amdgpu_device *adev = smu->adev;
1184 uint32_t val = 0;
1185
1186 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1187 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1188 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1189
1190 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1191
1192 return 0;
1193 }
1194
1195 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1196 {
1197 int ret = 0;
1198 struct smu_temperature_range range;
1199 struct amdgpu_device *adev = smu->adev;
1200
1201 if (!smu->pm_enabled)
1202 return ret;
1203
1204 memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1205
1206 ret = smu_get_thermal_temperature_range(smu, &range);
1207 if (ret)
1208 return ret;
1209
1210 if (smu->smu_table.thermal_controller_type) {
1211 ret = smu_v11_0_set_thermal_range(smu, range);
1212 if (ret)
1213 return ret;
1214
1215 ret = smu_v11_0_enable_thermal_alert(smu);
1216 if (ret)
1217 return ret;
1218
1219 ret = smu_set_thermal_fan_table(smu);
1220 if (ret)
1221 return ret;
1222 }
1223
1224 adev->pm.dpm.thermal.min_temp = range.min;
1225 adev->pm.dpm.thermal.max_temp = range.max;
1226 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1227 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1228 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1229 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1230 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1231 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1232 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1233
1234 return ret;
1235 }
1236
1237 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1238 {
1239 struct amdgpu_device *adev = smu->adev;
1240
1241 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1242
1243 return 0;
1244 }
1245
1246 static uint16_t convert_to_vddc(uint8_t vid)
1247 {
1248 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1249 }
1250
1251 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1252 {
1253 struct amdgpu_device *adev = smu->adev;
1254 uint32_t vdd = 0, val_vid = 0;
1255
1256 if (!value)
1257 return -EINVAL;
1258 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1259 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1260 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1261
1262 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1263
1264 *value = vdd;
1265
1266 return 0;
1267
1268 }
1269
1270 int smu_v11_0_read_sensor(struct smu_context *smu,
1271 enum amd_pp_sensors sensor,
1272 void *data, uint32_t *size)
1273 {
1274 int ret = 0;
1275
1276 if(!data || !size)
1277 return -EINVAL;
1278
1279 switch (sensor) {
1280 case AMDGPU_PP_SENSOR_GFX_MCLK:
1281 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1282 *size = 4;
1283 break;
1284 case AMDGPU_PP_SENSOR_GFX_SCLK:
1285 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1286 *size = 4;
1287 break;
1288 case AMDGPU_PP_SENSOR_VDDGFX:
1289 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1290 *size = 4;
1291 break;
1292 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1293 *(uint32_t *)data = 0;
1294 *size = 4;
1295 break;
1296 default:
1297 ret = smu_common_read_sensor(smu, sensor, data, size);
1298 break;
1299 }
1300
1301 if (ret)
1302 *size = 0;
1303
1304 return ret;
1305 }
1306
1307 int
1308 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1309 struct pp_display_clock_request
1310 *clock_req)
1311 {
1312 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1313 int ret = 0;
1314 enum smu_clk_type clk_select = 0;
1315 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1316
1317 if (!smu->pm_enabled)
1318 return -EINVAL;
1319
1320 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1321 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1322 switch (clk_type) {
1323 case amd_pp_dcef_clock:
1324 clk_select = SMU_DCEFCLK;
1325 break;
1326 case amd_pp_disp_clock:
1327 clk_select = SMU_DISPCLK;
1328 break;
1329 case amd_pp_pixel_clock:
1330 clk_select = SMU_PIXCLK;
1331 break;
1332 case amd_pp_phy_clock:
1333 clk_select = SMU_PHYCLK;
1334 break;
1335 case amd_pp_mem_clock:
1336 clk_select = SMU_UCLK;
1337 break;
1338 default:
1339 pr_info("[%s] Invalid Clock Type!", __func__);
1340 ret = -EINVAL;
1341 break;
1342 }
1343
1344 if (ret)
1345 goto failed;
1346
1347 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1348 return 0;
1349
1350 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1351
1352 if(clk_select == SMU_UCLK)
1353 smu->hard_min_uclk_req_from_dal = clk_freq;
1354 }
1355
1356 failed:
1357 return ret;
1358 }
1359
1360 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1361 {
1362 int ret = 0;
1363 struct amdgpu_device *adev = smu->adev;
1364
1365 switch (adev->asic_type) {
1366 case CHIP_VEGA20:
1367 break;
1368 case CHIP_NAVI10:
1369 case CHIP_NAVI14:
1370 case CHIP_NAVI12:
1371 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1372 return 0;
1373 if (enable)
1374 ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1375 else
1376 ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1377 break;
1378 default:
1379 break;
1380 }
1381
1382 return ret;
1383 }
1384
1385 uint32_t
1386 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1387 {
1388 if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1389 return AMD_FAN_CTRL_MANUAL;
1390 else
1391 return AMD_FAN_CTRL_AUTO;
1392 }
1393
1394 static int
1395 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1396 {
1397 int ret = 0;
1398
1399 if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1400 return 0;
1401
1402 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1403 if (ret)
1404 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1405 __func__, (auto_fan_control ? "Start" : "Stop"));
1406
1407 return ret;
1408 }
1409
1410 static int
1411 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1412 {
1413 struct amdgpu_device *adev = smu->adev;
1414
1415 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1416 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1417 CG_FDO_CTRL2, TMIN, 0));
1418 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1419 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1420 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1421
1422 return 0;
1423 }
1424
1425 int
1426 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1427 {
1428 struct amdgpu_device *adev = smu->adev;
1429 uint32_t duty100, duty;
1430 uint64_t tmp64;
1431
1432 if (speed > 100)
1433 speed = 100;
1434
1435 if (smu_v11_0_auto_fan_control(smu, 0))
1436 return -EINVAL;
1437
1438 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1439 CG_FDO_CTRL1, FMAX_DUTY100);
1440 if (!duty100)
1441 return -EINVAL;
1442
1443 tmp64 = (uint64_t)speed * duty100;
1444 do_div(tmp64, 100);
1445 duty = (uint32_t)tmp64;
1446
1447 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1448 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1449 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1450
1451 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1452 }
1453
1454 int
1455 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1456 uint32_t mode)
1457 {
1458 int ret = 0;
1459
1460 switch (mode) {
1461 case AMD_FAN_CTRL_NONE:
1462 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1463 break;
1464 case AMD_FAN_CTRL_MANUAL:
1465 ret = smu_v11_0_auto_fan_control(smu, 0);
1466 break;
1467 case AMD_FAN_CTRL_AUTO:
1468 ret = smu_v11_0_auto_fan_control(smu, 1);
1469 break;
1470 default:
1471 break;
1472 }
1473
1474 if (ret) {
1475 pr_err("[%s]Set fan control mode failed!", __func__);
1476 return -EINVAL;
1477 }
1478
1479 return ret;
1480 }
1481
1482 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1483 uint32_t speed)
1484 {
1485 struct amdgpu_device *adev = smu->adev;
1486 int ret;
1487 uint32_t tach_period, crystal_clock_freq;
1488
1489 if (!speed)
1490 return -EINVAL;
1491
1492 ret = smu_v11_0_auto_fan_control(smu, 0);
1493 if (ret)
1494 return ret;
1495
1496 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1497 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1498 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1499 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1500 CG_TACH_CTRL, TARGET_PERIOD,
1501 tach_period));
1502
1503 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1504
1505 return ret;
1506 }
1507
1508 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1509 uint32_t pstate)
1510 {
1511 int ret = 0;
1512 ret = smu_send_smc_msg_with_param(smu,
1513 SMU_MSG_SetXgmiMode,
1514 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1515 return ret;
1516 }
1517
1518 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1519 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1520
1521 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1522 struct amdgpu_irq_src *source,
1523 struct amdgpu_iv_entry *entry)
1524 {
1525 uint32_t client_id = entry->client_id;
1526 uint32_t src_id = entry->src_id;
1527
1528 if (client_id == SOC15_IH_CLIENTID_THM) {
1529 switch (src_id) {
1530 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1531 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1532 PCI_BUS_NUM(adev->pdev->devfn),
1533 PCI_SLOT(adev->pdev->devfn),
1534 PCI_FUNC(adev->pdev->devfn));
1535 break;
1536 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1537 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1538 PCI_BUS_NUM(adev->pdev->devfn),
1539 PCI_SLOT(adev->pdev->devfn),
1540 PCI_FUNC(adev->pdev->devfn));
1541 break;
1542 default:
1543 pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1544 src_id,
1545 PCI_BUS_NUM(adev->pdev->devfn),
1546 PCI_SLOT(adev->pdev->devfn),
1547 PCI_FUNC(adev->pdev->devfn));
1548 break;
1549
1550 }
1551 }
1552
1553 return 0;
1554 }
1555
1556 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1557 {
1558 .process = smu_v11_0_irq_process,
1559 };
1560
1561 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1562 {
1563 struct amdgpu_device *adev = smu->adev;
1564 struct amdgpu_irq_src *irq_src = smu->irq_source;
1565 int ret = 0;
1566
1567 /* already register */
1568 if (irq_src)
1569 return 0;
1570
1571 irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1572 if (!irq_src)
1573 return -ENOMEM;
1574 smu->irq_source = irq_src;
1575
1576 irq_src->funcs = &smu_v11_0_irq_funcs;
1577
1578 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1579 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1580 irq_src);
1581 if (ret)
1582 return ret;
1583
1584 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1585 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1586 irq_src);
1587 if (ret)
1588 return ret;
1589
1590 return ret;
1591 }
1592
1593 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1594 struct pp_smu_nv_clock_table *max_clocks)
1595 {
1596 struct smu_table_context *table_context = &smu->smu_table;
1597 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1598
1599 if (!max_clocks || !table_context->max_sustainable_clocks)
1600 return -EINVAL;
1601
1602 sustainable_clocks = table_context->max_sustainable_clocks;
1603
1604 max_clocks->dcfClockInKhz =
1605 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1606 max_clocks->displayClockInKhz =
1607 (unsigned int) sustainable_clocks->display_clock * 1000;
1608 max_clocks->phyClockInKhz =
1609 (unsigned int) sustainable_clocks->phy_clock * 1000;
1610 max_clocks->pixelClockInKhz =
1611 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1612 max_clocks->uClockInKhz =
1613 (unsigned int) sustainable_clocks->uclock * 1000;
1614 max_clocks->socClockInKhz =
1615 (unsigned int) sustainable_clocks->soc_clock * 1000;
1616 max_clocks->dscClockInKhz = 0;
1617 max_clocks->dppClockInKhz = 0;
1618 max_clocks->fabricClockInKhz = 0;
1619
1620 return 0;
1621 }
1622
1623 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1624 {
1625 int ret = 0;
1626
1627 ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1628
1629 return ret;
1630 }
1631
1632 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1633 {
1634 return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1635 }
1636
1637 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1638 {
1639 struct amdgpu_device *adev = smu->adev;
1640 struct smu_baco_context *smu_baco = &smu->smu_baco;
1641 uint32_t val;
1642 bool baco_support;
1643
1644 mutex_lock(&smu_baco->mutex);
1645 baco_support = smu_baco->platform_support;
1646 mutex_unlock(&smu_baco->mutex);
1647
1648 if (!baco_support)
1649 return false;
1650
1651 /* Arcturus does not support this bit mask */
1652 if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1653 !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1654 return false;
1655
1656 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1657 if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1658 return true;
1659
1660 return false;
1661 }
1662
1663 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1664 {
1665 struct smu_baco_context *smu_baco = &smu->smu_baco;
1666 enum smu_baco_state baco_state;
1667
1668 mutex_lock(&smu_baco->mutex);
1669 baco_state = smu_baco->state;
1670 mutex_unlock(&smu_baco->mutex);
1671
1672 return baco_state;
1673 }
1674
1675 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1676 {
1677
1678 struct smu_baco_context *smu_baco = &smu->smu_baco;
1679 struct amdgpu_device *adev = smu->adev;
1680 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1681 uint32_t bif_doorbell_intr_cntl;
1682 uint32_t data;
1683 int ret = 0;
1684
1685 if (smu_v11_0_baco_get_state(smu) == state)
1686 return 0;
1687
1688 mutex_lock(&smu_baco->mutex);
1689
1690 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
1691
1692 if (state == SMU_BACO_STATE_ENTER) {
1693 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1694 BIF_DOORBELL_INT_CNTL,
1695 DOORBELL_INTERRUPT_DISABLE, 1);
1696 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1697
1698 if (!ras || !ras->supported) {
1699 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1700 data |= 0x80000000;
1701 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1702
1703 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
1704 } else {
1705 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
1706 }
1707 } else {
1708 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1709 if (ret)
1710 goto out;
1711
1712 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1713 BIF_DOORBELL_INT_CNTL,
1714 DOORBELL_INTERRUPT_DISABLE, 0);
1715 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1716
1717 /* clear vbios scratch 6 and 7 for coming asic reinit */
1718 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1719 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1720 }
1721 if (ret)
1722 goto out;
1723
1724 smu_baco->state = state;
1725 out:
1726 mutex_unlock(&smu_baco->mutex);
1727 return ret;
1728 }
1729
1730 int smu_v11_0_baco_enter(struct smu_context *smu)
1731 {
1732 struct amdgpu_device *adev = smu->adev;
1733 int ret = 0;
1734
1735 /* Arcturus does not need this audio workaround */
1736 if (adev->asic_type != CHIP_ARCTURUS) {
1737 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1738 if (ret)
1739 return ret;
1740 }
1741
1742 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1743 if (ret)
1744 return ret;
1745
1746 msleep(10);
1747
1748 return ret;
1749 }
1750
1751 int smu_v11_0_baco_exit(struct smu_context *smu)
1752 {
1753 int ret = 0;
1754
1755 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1756 if (ret)
1757 return ret;
1758
1759 return ret;
1760 }
1761
1762 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1763 uint32_t *min, uint32_t *max)
1764 {
1765 int ret = 0, clk_id = 0;
1766 uint32_t param = 0;
1767
1768 clk_id = smu_clk_get_index(smu, clk_type);
1769 if (clk_id < 0) {
1770 ret = -EINVAL;
1771 goto failed;
1772 }
1773 param = (clk_id & 0xffff) << 16;
1774
1775 if (max) {
1776 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1777 if (ret)
1778 goto failed;
1779 ret = smu_read_smc_arg(smu, max);
1780 if (ret)
1781 goto failed;
1782 }
1783
1784 if (min) {
1785 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1786 if (ret)
1787 goto failed;
1788 ret = smu_read_smc_arg(smu, min);
1789 if (ret)
1790 goto failed;
1791 }
1792
1793 failed:
1794 return ret;
1795 }
1796
1797 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1798 uint32_t min, uint32_t max)
1799 {
1800 int ret = 0, clk_id = 0;
1801 uint32_t param;
1802
1803 clk_id = smu_clk_get_index(smu, clk_type);
1804 if (clk_id < 0)
1805 return clk_id;
1806
1807 if (max > 0) {
1808 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1809 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1810 param);
1811 if (ret)
1812 return ret;
1813 }
1814
1815 if (min > 0) {
1816 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1817 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1818 param);
1819 if (ret)
1820 return ret;
1821 }
1822
1823 return ret;
1824 }
1825
1826 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1827 {
1828 struct amdgpu_device *adev = smu->adev;
1829 uint32_t pcie_gen = 0, pcie_width = 0;
1830 int ret;
1831
1832 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1833 pcie_gen = 3;
1834 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1835 pcie_gen = 2;
1836 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1837 pcie_gen = 1;
1838 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1839 pcie_gen = 0;
1840
1841 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1842 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1843 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1844 */
1845 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1846 pcie_width = 6;
1847 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1848 pcie_width = 5;
1849 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1850 pcie_width = 4;
1851 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1852 pcie_width = 3;
1853 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1854 pcie_width = 2;
1855 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1856 pcie_width = 1;
1857
1858 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1859
1860 if (ret)
1861 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1862
1863 return ret;
1864
1865 }
1866
1867 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1868 {
1869 struct smu_table_context *table_context = &smu->smu_table;
1870 int ret = 0;
1871
1872 if (initialize) {
1873 if (table_context->overdrive_table) {
1874 return -EINVAL;
1875 }
1876 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1877 if (!table_context->overdrive_table) {
1878 return -ENOMEM;
1879 }
1880 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1881 if (ret) {
1882 pr_err("Failed to export overdrive table!\n");
1883 return ret;
1884 }
1885 }
1886 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1887 if (ret) {
1888 pr_err("Failed to import overdrive table!\n");
1889 return ret;
1890 }
1891 return ret;
1892 }
1893
1894 int smu_v11_0_set_performance_level(struct smu_context *smu,
1895 enum amd_dpm_forced_level level)
1896 {
1897 int ret = 0;
1898 uint32_t sclk_mask, mclk_mask, soc_mask;
1899
1900 switch (level) {
1901 case AMD_DPM_FORCED_LEVEL_HIGH:
1902 ret = smu_force_dpm_limit_value(smu, true);
1903 break;
1904 case AMD_DPM_FORCED_LEVEL_LOW:
1905 ret = smu_force_dpm_limit_value(smu, false);
1906 break;
1907 case AMD_DPM_FORCED_LEVEL_AUTO:
1908 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1909 ret = smu_unforce_dpm_levels(smu);
1910 break;
1911 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1912 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1913 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1914 ret = smu_get_profiling_clk_mask(smu, level,
1915 &sclk_mask,
1916 &mclk_mask,
1917 &soc_mask);
1918 if (ret)
1919 return ret;
1920 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1921 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1922 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1923 break;
1924 case AMD_DPM_FORCED_LEVEL_MANUAL:
1925 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1926 default:
1927 break;
1928 }
1929 return ret;
1930 }
1931
Linux with added FPC-III support