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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / powerplay / smumgr / ci_smumgr.c
blob868e2d5f6e621e1c04980314de23b6f9180e2353
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include "linux/delay.h"
27 #include <linux/types.h>
28 #include <linux/pci.h>
29
30 #include "smumgr.h"
31 #include "pp_debug.h"
32 #include "ci_smumgr.h"
33 #include "ppsmc.h"
34 #include "smu7_hwmgr.h"
35 #include "hardwaremanager.h"
36 #include "ppatomctrl.h"
37 #include "cgs_common.h"
38 #include "atombios.h"
39 #include "pppcielanes.h"
40
41 #include "smu/smu_7_0_1_d.h"
42 #include "smu/smu_7_0_1_sh_mask.h"
43
44 #include "dce/dce_8_0_d.h"
45 #include "dce/dce_8_0_sh_mask.h"
46
47 #include "bif/bif_4_1_d.h"
48 #include "bif/bif_4_1_sh_mask.h"
49
50 #include "gca/gfx_7_2_d.h"
51 #include "gca/gfx_7_2_sh_mask.h"
52
53 #include "gmc/gmc_7_1_d.h"
54 #include "gmc/gmc_7_1_sh_mask.h"
55
56 #include "processpptables.h"
57
58 #define MC_CG_ARB_FREQ_F0 0x0a
59 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define MC_CG_ARB_FREQ_F2 0x0c
61 #define MC_CG_ARB_FREQ_F3 0x0d
62
63 #define SMC_RAM_END 0x40000
64
65 #define CISLAND_MINIMUM_ENGINE_CLOCK 800
66 #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
67
68 static const struct ci_pt_defaults defaults_hawaii_xt = {
69 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
70 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
71 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
72 };
73
74 static const struct ci_pt_defaults defaults_hawaii_pro = {
75 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
76 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
77 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
78 };
79
80 static const struct ci_pt_defaults defaults_bonaire_xt = {
81 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
82 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
83 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
84 };
85
86
87 static const struct ci_pt_defaults defaults_saturn_xt = {
88 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
89 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
90 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
91 };
92
93
94 static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
95 uint32_t smc_addr, uint32_t limit)
96 {
97 if ((0 != (3 & smc_addr))
98 || ((smc_addr + 3) >= limit)) {
99 pr_err("smc_addr invalid \n");
100 return -EINVAL;
101 }
102
103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
105 return 0;
106 }
107
108 static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
109 const uint8_t *src, uint32_t byte_count, uint32_t limit)
110 {
111 int result;
112 uint32_t data = 0;
113 uint32_t original_data;
114 uint32_t addr = 0;
115 uint32_t extra_shift;
116
117 if ((3 & smc_start_address)
118 || ((smc_start_address + byte_count) >= limit)) {
119 pr_err("smc_start_address invalid \n");
120 return -EINVAL;
121 }
122
123 addr = smc_start_address;
124
125 while (byte_count >= 4) {
126 /* Bytes are written into the SMC address space with the MSB first. */
127 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
128
129 result = ci_set_smc_sram_address(hwmgr, addr, limit);
130
131 if (0 != result)
132 return result;
133
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
135
136 src += 4;
137 byte_count -= 4;
138 addr += 4;
139 }
140
141 if (0 != byte_count) {
142
143 data = 0;
144
145 result = ci_set_smc_sram_address(hwmgr, addr, limit);
146
147 if (0 != result)
148 return result;
149
150
151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
152
153 extra_shift = 8 * (4 - byte_count);
154
155 while (byte_count > 0) {
156 /* Bytes are written into the SMC addres space with the MSB first. */
157 data = (0x100 * data) + *src++;
158 byte_count--;
159 }
160
161 data <<= extra_shift;
162
163 data |= (original_data & ~((~0UL) << extra_shift));
164
165 result = ci_set_smc_sram_address(hwmgr, addr, limit);
166
167 if (0 != result)
168 return result;
169
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
171 }
172
173 return 0;
174 }
175
176
177 static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
178 {
179 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
180
181 ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
182
183 return 0;
184 }
185
186 bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
187 {
188 return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
189 CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
190 && (0x20100 <= cgs_read_ind_register(hwmgr->device,
191 CGS_IND_REG__SMC, ixSMC_PC_C)));
192 }
193
194 static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
195 uint32_t *value, uint32_t limit)
196 {
197 int result;
198
199 result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
200
201 if (result)
202 return result;
203
204 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
205 return 0;
206 }
207
208 static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
209 {
210 int ret;
211
212 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
213 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
214
215 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
216
217 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
218
219 if (ret != 1)
220 pr_info("\n failed to send message %x ret is %d\n", msg, ret);
221
222 return 0;
223 }
224
225 static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
226 uint16_t msg, uint32_t parameter)
227 {
228 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
229 return ci_send_msg_to_smc(hwmgr, msg);
230 }
231
232 static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
233 {
234 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
235 struct amdgpu_device *adev = hwmgr->adev;
236 uint32_t dev_id;
237
238 dev_id = adev->pdev->device;
239
240 switch (dev_id) {
241 case 0x67BA:
242 case 0x66B1:
243 smu_data->power_tune_defaults = &defaults_hawaii_pro;
244 break;
245 case 0x67B8:
246 case 0x66B0:
247 smu_data->power_tune_defaults = &defaults_hawaii_xt;
248 break;
249 case 0x6640:
250 case 0x6641:
251 case 0x6646:
252 case 0x6647:
253 smu_data->power_tune_defaults = &defaults_saturn_xt;
254 break;
255 case 0x6649:
256 case 0x6650:
257 case 0x6651:
258 case 0x6658:
259 case 0x665C:
260 case 0x665D:
261 case 0x67A0:
262 case 0x67A1:
263 case 0x67A2:
264 case 0x67A8:
265 case 0x67A9:
266 case 0x67AA:
267 case 0x67B9:
268 case 0x67BE:
269 default:
270 smu_data->power_tune_defaults = &defaults_bonaire_xt;
271 break;
272 }
273 }
274
275 static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
276 struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
277 uint32_t clock, uint32_t *vol)
278 {
279 uint32_t i = 0;
280
281 if (allowed_clock_voltage_table->count == 0)
282 return -EINVAL;
283
284 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
285 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
286 *vol = allowed_clock_voltage_table->entries[i].v;
287 return 0;
288 }
289 }
290
291 *vol = allowed_clock_voltage_table->entries[i - 1].v;
292 return 0;
293 }
294
295 static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr,
296 uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)
297 {
298 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
299 struct pp_atomctrl_clock_dividers_vi dividers;
300 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
301 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
302 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
303 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
304 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
305 uint32_t ref_clock;
306 uint32_t ref_divider;
307 uint32_t fbdiv;
308 int result;
309
310 /* get the engine clock dividers for this clock value */
311 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
312
313 PP_ASSERT_WITH_CODE(result == 0,
314 "Error retrieving Engine Clock dividers from VBIOS.",
315 return result);
316
317 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
318 ref_clock = atomctrl_get_reference_clock(hwmgr);
319 ref_divider = 1 + dividers.uc_pll_ref_div;
320
321 /* low 14 bits is fraction and high 12 bits is divider */
322 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
323
324 /* SPLL_FUNC_CNTL setup */
325 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
326 SPLL_REF_DIV, dividers.uc_pll_ref_div);
327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
328 SPLL_PDIV_A, dividers.uc_pll_post_div);
329
330 /* SPLL_FUNC_CNTL_3 setup*/
331 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
332 SPLL_FB_DIV, fbdiv);
333
334 /* set to use fractional accumulation*/
335 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
336 SPLL_DITHEN, 1);
337
338 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
339 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
340 struct pp_atomctrl_internal_ss_info ss_info;
341 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
342
343 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
344 vco_freq, &ss_info)) {
345 uint32_t clk_s = ref_clock * 5 /
346 (ref_divider * ss_info.speed_spectrum_rate);
347 uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage *
348 fbdiv / (clk_s * 10000);
349
350 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
351 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
352 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
353 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
354 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
355 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
356 }
357 }
358
359 sclk->SclkFrequency = clock;
360 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
361 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
362 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
363 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
364 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
365
366 return 0;
367 }
368
369 static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
370 const struct phm_phase_shedding_limits_table *pl,
371 uint32_t sclk, uint32_t *p_shed)
372 {
373 unsigned int i;
374
375 /* use the minimum phase shedding */
376 *p_shed = 1;
377
378 for (i = 0; i < pl->count; i++) {
379 if (sclk < pl->entries[i].Sclk) {
380 *p_shed = i;
381 break;
382 }
383 }
384 }
385
386 static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
387 uint32_t clock_insr)
388 {
389 uint8_t i;
390 uint32_t temp;
391 uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK);
392
393 if (clock < min) {
394 pr_info("Engine clock can't satisfy stutter requirement!\n");
395 return 0;
396 }
397 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
398 temp = clock >> i;
399
400 if (temp >= min || i == 0)
401 break;
402 }
403 return i;
404 }
405
406 static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
407 uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)
408 {
409 int result;
410 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
411
412
413 result = ci_calculate_sclk_params(hwmgr, clock, level);
414
415 /* populate graphics levels */
416 result = ci_get_dependency_volt_by_clk(hwmgr,
417 hwmgr->dyn_state.vddc_dependency_on_sclk, clock,
418 (uint32_t *)(&level->MinVddc));
419 if (result) {
420 pr_err("vdd_dep_on_sclk table is NULL\n");
421 return result;
422 }
423
424 level->SclkFrequency = clock;
425 level->MinVddcPhases = 1;
426
427 if (data->vddc_phase_shed_control)
428 ci_populate_phase_value_based_on_sclk(hwmgr,
429 hwmgr->dyn_state.vddc_phase_shed_limits_table,
430 clock,
431 &level->MinVddcPhases);
432
433 level->ActivityLevel = data->current_profile_setting.sclk_activity;
434 level->CcPwrDynRm = 0;
435 level->CcPwrDynRm1 = 0;
436 level->EnabledForActivity = 0;
437 /* this level can be used for throttling.*/
438 level->EnabledForThrottle = 1;
439 level->UpH = data->current_profile_setting.sclk_up_hyst;
440 level->DownH = data->current_profile_setting.sclk_down_hyst;
441 level->VoltageDownH = 0;
442 level->PowerThrottle = 0;
443
444
445 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
446 PHM_PlatformCaps_SclkDeepSleep))
447 level->DeepSleepDivId =
448 ci_get_sleep_divider_id_from_clock(clock,
449 CISLAND_MINIMUM_ENGINE_CLOCK);
450
451 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
452 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
453
454 if (0 == result) {
455 level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE);
456 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases);
457 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
458 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
459 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
460 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
461 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
462 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
463 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
464 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
465 }
466
467 return result;
468 }
469
470 static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
471 {
472 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
473 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
474 struct smu7_dpm_table *dpm_table = &data->dpm_table;
475 int result = 0;
476 uint32_t array = smu_data->dpm_table_start +
477 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
478 uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
479 SMU7_MAX_LEVELS_GRAPHICS;
480 struct SMU7_Discrete_GraphicsLevel *levels =
481 smu_data->smc_state_table.GraphicsLevel;
482 uint32_t i;
483
484 for (i = 0; i < dpm_table->sclk_table.count; i++) {
485 result = ci_populate_single_graphic_level(hwmgr,
486 dpm_table->sclk_table.dpm_levels[i].value,
487 &levels[i]);
488 if (result)
489 return result;
490 if (i > 1)
491 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
492 if (i == (dpm_table->sclk_table.count - 1))
493 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
494 PPSMC_DISPLAY_WATERMARK_HIGH;
495 }
496
497 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
498
499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
500 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
501 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
502
503 result = ci_copy_bytes_to_smc(hwmgr, array,
504 (u8 *)levels, array_size,
505 SMC_RAM_END);
506
507 return result;
508
509 }
510
511 static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
512 {
513 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
514 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
515
516 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
517 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
518 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
519 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
520
521 return 0;
522 }
523
524 static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
525 {
526 uint16_t tdc_limit;
527 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
528 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
529
530 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
531 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
532 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
533 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
534 defaults->tdc_vddc_throttle_release_limit_perc;
535 smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
536
537 return 0;
538 }
539
540 static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
541 {
542 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
543 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
544 uint32_t temp;
545
546 if (ci_read_smc_sram_dword(hwmgr,
547 fuse_table_offset +
548 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
549 (uint32_t *)&temp, SMC_RAM_END))
550 PP_ASSERT_WITH_CODE(false,
551 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
552 return -EINVAL);
553 else
554 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
555
556 return 0;
557 }
558
559 static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
560 {
561 uint16_t tmp;
562 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
563
564 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
565 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
566 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
567 else
568 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
569
570 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
571
572 return 0;
573 }
574
575 static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
576 {
577 int i;
578 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
579 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
580 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
581 uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;
582
583 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
584 "The CAC Leakage table does not exist!", return -EINVAL);
585 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
586 "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
587 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
588 "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
589
590 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
591 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
592 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
593 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
594 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3);
595 } else {
596 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc);
597 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage);
598 }
599 }
600
601 return 0;
602 }
603
604 static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
605 {
606 int i;
607 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
608 uint8_t *vid = smu_data->power_tune_table.VddCVid;
609 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
610
611 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
612 "There should never be more than 8 entries for VddcVid!!!",
613 return -EINVAL);
614
615 for (i = 0; i < (int)data->vddc_voltage_table.count; i++)
616 vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
617
618 return 0;
619 }
620
621 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
622 {
623 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
624 u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
625 u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
626 int i, min, max;
627
628 min = max = hi_vid[0];
629 for (i = 0; i < 8; i++) {
630 if (0 != hi_vid[i]) {
631 if (min > hi_vid[i])
632 min = hi_vid[i];
633 if (max < hi_vid[i])
634 max = hi_vid[i];
635 }
636
637 if (0 != lo_vid[i]) {
638 if (min > lo_vid[i])
639 min = lo_vid[i];
640 if (max < lo_vid[i])
641 max = lo_vid[i];
642 }
643 }
644
645 if ((min == 0) || (max == 0))
646 return -EINVAL;
647 smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;
648 smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;
649
650 return 0;
651 }
652
653 static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
654 {
655 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
656 uint16_t HiSidd;
657 uint16_t LoSidd;
658 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
659
660 HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
661 LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
662
663 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
664 CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
665 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
666 CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
667
668 return 0;
669 }
670
671 static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
672 {
673 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
674 uint32_t pm_fuse_table_offset;
675 int ret = 0;
676
677 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
678 PHM_PlatformCaps_PowerContainment)) {
679 if (ci_read_smc_sram_dword(hwmgr,
680 SMU7_FIRMWARE_HEADER_LOCATION +
681 offsetof(SMU7_Firmware_Header, PmFuseTable),
682 &pm_fuse_table_offset, SMC_RAM_END)) {
683 pr_err("Attempt to get pm_fuse_table_offset Failed!\n");
684 return -EINVAL;
685 }
686
687 /* DW0 - DW3 */
688 ret = ci_populate_bapm_vddc_vid_sidd(hwmgr);
689 /* DW4 - DW5 */
690 ret |= ci_populate_vddc_vid(hwmgr);
691 /* DW6 */
692 ret |= ci_populate_svi_load_line(hwmgr);
693 /* DW7 */
694 ret |= ci_populate_tdc_limit(hwmgr);
695 /* DW8 */
696 ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset);
697
698 ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset);
699
700 ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr);
701
702 ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr);
703 if (ret)
704 return ret;
705
706 ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
707 (uint8_t *)&smu_data->power_tune_table,
708 sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
709 }
710 return ret;
711 }
712
713 static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
714 {
715 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
716 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
717 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
718 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
719 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
720 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
721 const uint16_t *def1, *def2;
722 int i, j, k;
723
724 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
725 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
726
727 dpm_table->DTETjOffset = 0;
728 dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
729 dpm_table->GpuTjHyst = 8;
730
731 dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
732
733 if (ppm) {
734 dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
735 dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
736 } else {
737 dpm_table->PPM_PkgPwrLimit = 0;
738 dpm_table->PPM_TemperatureLimit = 0;
739 }
740
741 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
742 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
743
744 dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
745 def1 = defaults->bapmti_r;
746 def2 = defaults->bapmti_rc;
747
748 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
749 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
750 for (k = 0; k < SMU7_DTE_SINKS; k++) {
751 dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
752 dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
753 def1++;
754 def2++;
755 }
756 }
757 }
758
759 return 0;
760 }
761
762 static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
763 pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
764 uint16_t *lo)
765 {
766 uint16_t v_index;
767 bool vol_found = false;
768 *hi = tab->value * VOLTAGE_SCALE;
769 *lo = tab->value * VOLTAGE_SCALE;
770
771 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
772 "The SCLK/VDDC Dependency Table does not exist.\n",
773 return -EINVAL);
774
775 if (NULL == hwmgr->dyn_state.cac_leakage_table) {
776 pr_warn("CAC Leakage Table does not exist, using vddc.\n");
777 return 0;
778 }
779
780 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
781 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
782 vol_found = true;
783 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
784 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
785 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
786 } else {
787 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
788 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
789 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
790 }
791 break;
792 }
793 }
794
795 if (!vol_found) {
796 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
797 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
798 vol_found = true;
799 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
800 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
801 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
802 } else {
803 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
804 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
805 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
806 }
807 break;
808 }
809 }
810
811 if (!vol_found)
812 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
813 }
814
815 return 0;
816 }
817
818 static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
819 pp_atomctrl_voltage_table_entry *tab,
820 SMU7_Discrete_VoltageLevel *smc_voltage_tab)
821 {
822 int result;
823
824 result = ci_get_std_voltage_value_sidd(hwmgr, tab,
825 &smc_voltage_tab->StdVoltageHiSidd,
826 &smc_voltage_tab->StdVoltageLoSidd);
827 if (result) {
828 smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
829 smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
830 }
831
832 smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
833 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
834 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageLoSidd);
835
836 return 0;
837 }
838
839 static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
840 SMU7_Discrete_DpmTable *table)
841 {
842 unsigned int count;
843 int result;
844 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
845
846 table->VddcLevelCount = data->vddc_voltage_table.count;
847 for (count = 0; count < table->VddcLevelCount; count++) {
848 result = ci_populate_smc_voltage_table(hwmgr,
849 &(data->vddc_voltage_table.entries[count]),
850 &(table->VddcLevel[count]));
851 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
852
853 /* GPIO voltage control */
854 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
855 table->VddcLevel[count].Smio = (uint8_t) count;
856 table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low;
857 table->SmioMaskVddcVid |= data->vddc_voltage_table.entries[count].smio_low;
858 } else {
859 table->VddcLevel[count].Smio = 0;
860 }
861 }
862
863 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
864
865 return 0;
866 }
867
868 static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
869 SMU7_Discrete_DpmTable *table)
870 {
871 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
872 uint32_t count;
873 int result;
874
875 table->VddciLevelCount = data->vddci_voltage_table.count;
876
877 for (count = 0; count < table->VddciLevelCount; count++) {
878 result = ci_populate_smc_voltage_table(hwmgr,
879 &(data->vddci_voltage_table.entries[count]),
880 &(table->VddciLevel[count]));
881 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
882 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
883 table->VddciLevel[count].Smio = (uint8_t) count;
884 table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low;
885 table->SmioMaskVddciVid |= data->vddci_voltage_table.entries[count].smio_low;
886 } else {
887 table->VddciLevel[count].Smio = 0;
888 }
889 }
890
891 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
892
893 return 0;
894 }
895
896 static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
897 SMU7_Discrete_DpmTable *table)
898 {
899 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
900 uint32_t count;
901 int result;
902
903 table->MvddLevelCount = data->mvdd_voltage_table.count;
904
905 for (count = 0; count < table->MvddLevelCount; count++) {
906 result = ci_populate_smc_voltage_table(hwmgr,
907 &(data->mvdd_voltage_table.entries[count]),
908 &table->MvddLevel[count]);
909 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
910 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
911 table->MvddLevel[count].Smio = (uint8_t) count;
912 table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low;
913 table->SmioMaskMvddVid |= data->mvdd_voltage_table.entries[count].smio_low;
914 } else {
915 table->MvddLevel[count].Smio = 0;
916 }
917 }
918
919 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
920
921 return 0;
922 }
923
924
925 static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
926 SMU7_Discrete_DpmTable *table)
927 {
928 int result;
929
930 result = ci_populate_smc_vddc_table(hwmgr, table);
931 PP_ASSERT_WITH_CODE(0 == result,
932 "can not populate VDDC voltage table to SMC", return -EINVAL);
933
934 result = ci_populate_smc_vdd_ci_table(hwmgr, table);
935 PP_ASSERT_WITH_CODE(0 == result,
936 "can not populate VDDCI voltage table to SMC", return -EINVAL);
937
938 result = ci_populate_smc_mvdd_table(hwmgr, table);
939 PP_ASSERT_WITH_CODE(0 == result,
940 "can not populate MVDD voltage table to SMC", return -EINVAL);
941
942 return 0;
943 }
944
945 static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr,
946 struct SMU7_Discrete_Ulv *state)
947 {
948 uint32_t voltage_response_time, ulv_voltage;
949 int result;
950 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
951
952 state->CcPwrDynRm = 0;
953 state->CcPwrDynRm1 = 0;
954
955 result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
956 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
957
958 if (ulv_voltage == 0) {
959 data->ulv_supported = false;
960 return 0;
961 }
962
963 if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
964 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
965 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
966 state->VddcOffset = 0;
967 else
968 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
969 state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
970 } else {
971 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
972 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
973 state->VddcOffsetVid = 0;
974 else /* used in SVI2 Mode */
975 state->VddcOffsetVid = (uint8_t)(
976 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
977 * VOLTAGE_VID_OFFSET_SCALE2
978 / VOLTAGE_VID_OFFSET_SCALE1);
979 }
980 state->VddcPhase = 1;
981
982 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
983 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
984 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
985
986 return 0;
987 }
988
989 static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr,
990 SMU7_Discrete_Ulv *ulv_level)
991 {
992 return ci_populate_ulv_level(hwmgr, ulv_level);
993 }
994
995 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
996 {
997 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
998 struct smu7_dpm_table *dpm_table = &data->dpm_table;
999 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1000 uint32_t i;
1001
1002 /* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
1003 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1004 table->LinkLevel[i].PcieGenSpeed =
1005 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1006 table->LinkLevel[i].PcieLaneCount =
1007 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1008 table->LinkLevel[i].EnabledForActivity = 1;
1009 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
1010 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
1011 }
1012
1013 smu_data->smc_state_table.LinkLevelCount =
1014 (uint8_t)dpm_table->pcie_speed_table.count;
1015 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1016 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1017
1018 return 0;
1019 }
1020
1021 static int ci_calculate_mclk_params(
1022 struct pp_hwmgr *hwmgr,
1023 uint32_t memory_clock,
1024 SMU7_Discrete_MemoryLevel *mclk,
1025 bool strobe_mode,
1026 bool dllStateOn
1027 )
1028 {
1029 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1030 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1031 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1032 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1033 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1034 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1035 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1036 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1037 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1038 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1039
1040 pp_atomctrl_memory_clock_param mpll_param;
1041 int result;
1042
1043 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1044 memory_clock, &mpll_param, strobe_mode);
1045 PP_ASSERT_WITH_CODE(0 == result,
1046 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1047
1048 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1049
1050 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1051 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1052 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1053 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1054 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1055 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1056
1057 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1058 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1059
1060 if (data->is_memory_gddr5) {
1061 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1062 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1063 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1064 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1065 }
1066
1067 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1068 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1069 pp_atomctrl_internal_ss_info ss_info;
1070 uint32_t freq_nom;
1071 uint32_t tmp;
1072 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1073
1074 /* for GDDR5 for all modes and DDR3 */
1075 if (1 == mpll_param.qdr)
1076 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1077 else
1078 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1079
1080 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1081 tmp = (freq_nom / reference_clock);
1082 tmp = tmp * tmp;
1083
1084 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1085 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1086 uint32_t clkv =
1087 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1088 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1089
1090 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1091 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1092 }
1093 }
1094
1095 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1096 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1097 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1098 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1099 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1100 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1101
1102
1103 mclk->MclkFrequency = memory_clock;
1104 mclk->MpllFuncCntl = mpll_func_cntl;
1105 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1106 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1107 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1108 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1109 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1110 mclk->DllCntl = dll_cntl;
1111 mclk->MpllSs1 = mpll_ss1;
1112 mclk->MpllSs2 = mpll_ss2;
1113
1114 return 0;
1115 }
1116
1117 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,
1118 bool strobe_mode)
1119 {
1120 uint8_t mc_para_index;
1121
1122 if (strobe_mode) {
1123 if (memory_clock < 12500)
1124 mc_para_index = 0x00;
1125 else if (memory_clock > 47500)
1126 mc_para_index = 0x0f;
1127 else
1128 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1129 } else {
1130 if (memory_clock < 65000)
1131 mc_para_index = 0x00;
1132 else if (memory_clock > 135000)
1133 mc_para_index = 0x0f;
1134 else
1135 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1136 }
1137
1138 return mc_para_index;
1139 }
1140
1141 static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1142 {
1143 uint8_t mc_para_index;
1144
1145 if (memory_clock < 10000)
1146 mc_para_index = 0;
1147 else if (memory_clock >= 80000)
1148 mc_para_index = 0x0f;
1149 else
1150 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1151
1152 return mc_para_index;
1153 }
1154
1155 static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1156 uint32_t memory_clock, uint32_t *p_shed)
1157 {
1158 unsigned int i;
1159
1160 *p_shed = 1;
1161
1162 for (i = 0; i < pl->count; i++) {
1163 if (memory_clock < pl->entries[i].Mclk) {
1164 *p_shed = i;
1165 break;
1166 }
1167 }
1168
1169 return 0;
1170 }
1171
1172 static int ci_populate_single_memory_level(
1173 struct pp_hwmgr *hwmgr,
1174 uint32_t memory_clock,
1175 SMU7_Discrete_MemoryLevel *memory_level
1176 )
1177 {
1178 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1179 int result = 0;
1180 bool dll_state_on;
1181 uint32_t mclk_edc_wr_enable_threshold = 40000;
1182 uint32_t mclk_edc_enable_threshold = 40000;
1183 uint32_t mclk_strobe_mode_threshold = 40000;
1184
1185 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
1186 result = ci_get_dependency_volt_by_clk(hwmgr,
1187 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1188 PP_ASSERT_WITH_CODE((0 == result),
1189 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1190 }
1191
1192 if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1193 result = ci_get_dependency_volt_by_clk(hwmgr,
1194 hwmgr->dyn_state.vddci_dependency_on_mclk,
1195 memory_clock,
1196 &memory_level->MinVddci);
1197 PP_ASSERT_WITH_CODE((0 == result),
1198 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1199 }
1200
1201 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
1202 result = ci_get_dependency_volt_by_clk(hwmgr,
1203 hwmgr->dyn_state.mvdd_dependency_on_mclk,
1204 memory_clock,
1205 &memory_level->MinMvdd);
1206 PP_ASSERT_WITH_CODE((0 == result),
1207 "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result);
1208 }
1209
1210 memory_level->MinVddcPhases = 1;
1211
1212 if (data->vddc_phase_shed_control) {
1213 ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1214 memory_clock, &memory_level->MinVddcPhases);
1215 }
1216
1217 memory_level->EnabledForThrottle = 1;
1218 memory_level->EnabledForActivity = 1;
1219 memory_level->UpH = data->current_profile_setting.mclk_up_hyst;
1220 memory_level->DownH = data->current_profile_setting.mclk_down_hyst;
1221 memory_level->VoltageDownH = 0;
1222
1223 /* Indicates maximum activity level for this performance level.*/
1224 memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1225 memory_level->StutterEnable = 0;
1226 memory_level->StrobeEnable = 0;
1227 memory_level->EdcReadEnable = 0;
1228 memory_level->EdcWriteEnable = 0;
1229 memory_level->RttEnable = 0;
1230
1231 /* default set to low watermark. Highest level will be set to high later.*/
1232 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1233
1234 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1235 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1236
1237 /* stutter mode not support on ci */
1238
1239 /* decide strobe mode*/
1240 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1241 (memory_clock <= mclk_strobe_mode_threshold);
1242
1243 /* decide EDC mode and memory clock ratio*/
1244 if (data->is_memory_gddr5) {
1245 memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock,
1246 memory_level->StrobeEnable);
1247
1248 if ((mclk_edc_enable_threshold != 0) &&
1249 (memory_clock > mclk_edc_enable_threshold)) {
1250 memory_level->EdcReadEnable = 1;
1251 }
1252
1253 if ((mclk_edc_wr_enable_threshold != 0) &&
1254 (memory_clock > mclk_edc_wr_enable_threshold)) {
1255 memory_level->EdcWriteEnable = 1;
1256 }
1257
1258 if (memory_level->StrobeEnable) {
1259 if (ci_get_mclk_frequency_ratio(memory_clock, 1) >=
1260 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
1261 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1262 else
1263 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1264 } else
1265 dll_state_on = data->dll_default_on;
1266 } else {
1267 memory_level->StrobeRatio =
1268 ci_get_ddr3_mclk_frequency_ratio(memory_clock);
1269 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1270 }
1271
1272 result = ci_calculate_mclk_params(hwmgr,
1273 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1274
1275 if (0 == result) {
1276 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1277 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1278 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1279 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1280 /* MCLK frequency in units of 10KHz*/
1281 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1282 /* Indicates maximum activity level for this performance level.*/
1283 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1284 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1285 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1286 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1287 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1288 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1289 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1290 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1291 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1292 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1293 }
1294
1295 return result;
1296 }
1297
1298 static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1299 {
1300 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1301 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1302 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1303 int result;
1304 struct amdgpu_device *adev = hwmgr->adev;
1305 uint32_t dev_id;
1306
1307 uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
1308 uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY;
1309 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1310 uint32_t i;
1311
1312 memset(levels, 0x00, level_array_size);
1313
1314 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1315 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1316 "can not populate memory level as memory clock is zero", return -EINVAL);
1317 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1318 &(smu_data->smc_state_table.MemoryLevel[i]));
1319 if (0 != result)
1320 return result;
1321 }
1322
1323 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1324
1325 dev_id = adev->pdev->device;
1326
1327 if ((dpm_table->mclk_table.count >= 2)
1328 && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {
1329 smu_data->smc_state_table.MemoryLevel[1].MinVddci =
1330 smu_data->smc_state_table.MemoryLevel[0].MinVddci;
1331 smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
1332 smu_data->smc_state_table.MemoryLevel[0].MinMvdd;
1333 }
1334 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1335 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1336
1337 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1338 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1339 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1340
1341 result = ci_copy_bytes_to_smc(hwmgr,
1342 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
1343 SMC_RAM_END);
1344
1345 return result;
1346 }
1347
1348 static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
1349 SMU7_Discrete_VoltageLevel *voltage)
1350 {
1351 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1352
1353 uint32_t i = 0;
1354
1355 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1356 /* find mvdd value which clock is more than request */
1357 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
1358 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
1359 /* Always round to higher voltage. */
1360 voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
1361 break;
1362 }
1363 }
1364
1365 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
1366 "MVDD Voltage is outside the supported range.", return -EINVAL);
1367
1368 } else {
1369 return -EINVAL;
1370 }
1371
1372 return 0;
1373 }
1374
1375 static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1376 SMU7_Discrete_DpmTable *table)
1377 {
1378 int result = 0;
1379 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1380 struct pp_atomctrl_clock_dividers_vi dividers;
1381
1382 SMU7_Discrete_VoltageLevel voltage_level;
1383 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1384 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1385 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1386 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1387
1388
1389 /* The ACPI state should not do DPM on DC (or ever).*/
1390 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1391
1392 if (data->acpi_vddc)
1393 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1394 else
1395 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1396
1397 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
1398 /* assign zero for now*/
1399 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1400
1401 /* get the engine clock dividers for this clock value*/
1402 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1403 table->ACPILevel.SclkFrequency, &dividers);
1404
1405 PP_ASSERT_WITH_CODE(result == 0,
1406 "Error retrieving Engine Clock dividers from VBIOS.", return result);
1407
1408 /* divider ID for required SCLK*/
1409 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1410 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1411 table->ACPILevel.DeepSleepDivId = 0;
1412
1413 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1414 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
1415 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1416 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
1417 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
1418 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
1419
1420 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1421 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1422 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1423 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1424 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1425 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1426 table->ACPILevel.CcPwrDynRm = 0;
1427 table->ACPILevel.CcPwrDynRm1 = 0;
1428
1429 /* For various features to be enabled/disabled while this level is active.*/
1430 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1431 /* SCLK frequency in units of 10KHz*/
1432 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1433 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1434 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1435 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1436 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1437 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1438 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1439 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1440 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1441
1442
1443 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1444 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1445 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1446
1447 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1448 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1449 else {
1450 if (data->acpi_vddci != 0)
1451 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1452 else
1453 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1454 }
1455
1456 if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level))
1457 table->MemoryACPILevel.MinMvdd =
1458 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1459 else
1460 table->MemoryACPILevel.MinMvdd = 0;
1461
1462 /* Force reset on DLL*/
1463 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1464 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1465 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1466 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1467
1468 /* Disable DLL in ACPIState*/
1469 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1470 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1471 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1472 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1473
1474 /* Enable DLL bypass signal*/
1475 dll_cntl = PHM_SET_FIELD(dll_cntl,
1476 DLL_CNTL, MRDCK0_BYPASS, 0);
1477 dll_cntl = PHM_SET_FIELD(dll_cntl,
1478 DLL_CNTL, MRDCK1_BYPASS, 0);
1479
1480 table->MemoryACPILevel.DllCntl =
1481 PP_HOST_TO_SMC_UL(dll_cntl);
1482 table->MemoryACPILevel.MclkPwrmgtCntl =
1483 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1484 table->MemoryACPILevel.MpllAdFuncCntl =
1485 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1486 table->MemoryACPILevel.MpllDqFuncCntl =
1487 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1488 table->MemoryACPILevel.MpllFuncCntl =
1489 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1490 table->MemoryACPILevel.MpllFuncCntl_1 =
1491 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1492 table->MemoryACPILevel.MpllFuncCntl_2 =
1493 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1494 table->MemoryACPILevel.MpllSs1 =
1495 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1496 table->MemoryACPILevel.MpllSs2 =
1497 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1498
1499 table->MemoryACPILevel.EnabledForThrottle = 0;
1500 table->MemoryACPILevel.EnabledForActivity = 0;
1501 table->MemoryACPILevel.UpH = 0;
1502 table->MemoryACPILevel.DownH = 100;
1503 table->MemoryACPILevel.VoltageDownH = 0;
1504 /* Indicates maximum activity level for this performance level.*/
1505 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1506
1507 table->MemoryACPILevel.StutterEnable = 0;
1508 table->MemoryACPILevel.StrobeEnable = 0;
1509 table->MemoryACPILevel.EdcReadEnable = 0;
1510 table->MemoryACPILevel.EdcWriteEnable = 0;
1511 table->MemoryACPILevel.RttEnable = 0;
1512
1513 return result;
1514 }
1515
1516 static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1517 SMU7_Discrete_DpmTable *table)
1518 {
1519 int result = 0;
1520 uint8_t count;
1521 struct pp_atomctrl_clock_dividers_vi dividers;
1522 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1523 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1524
1525 table->UvdLevelCount = (uint8_t)(uvd_table->count);
1526
1527 for (count = 0; count < table->UvdLevelCount; count++) {
1528 table->UvdLevel[count].VclkFrequency =
1529 uvd_table->entries[count].vclk;
1530 table->UvdLevel[count].DclkFrequency =
1531 uvd_table->entries[count].dclk;
1532 table->UvdLevel[count].MinVddc =
1533 uvd_table->entries[count].v * VOLTAGE_SCALE;
1534 table->UvdLevel[count].MinVddcPhases = 1;
1535
1536 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1537 table->UvdLevel[count].VclkFrequency, &dividers);
1538 PP_ASSERT_WITH_CODE((0 == result),
1539 "can not find divide id for Vclk clock", return result);
1540
1541 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1542
1543 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1544 table->UvdLevel[count].DclkFrequency, &dividers);
1545 PP_ASSERT_WITH_CODE((0 == result),
1546 "can not find divide id for Dclk clock", return result);
1547
1548 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1549 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1551 CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);
1552 }
1553
1554 return result;
1555 }
1556
1557 static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1558 SMU7_Discrete_DpmTable *table)
1559 {
1560 int result = -EINVAL;
1561 uint8_t count;
1562 struct pp_atomctrl_clock_dividers_vi dividers;
1563 struct phm_vce_clock_voltage_dependency_table *vce_table =
1564 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1565
1566 table->VceLevelCount = (uint8_t)(vce_table->count);
1567 table->VceBootLevel = 0;
1568
1569 for (count = 0; count < table->VceLevelCount; count++) {
1570 table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
1571 table->VceLevel[count].MinVoltage =
1572 vce_table->entries[count].v * VOLTAGE_SCALE;
1573 table->VceLevel[count].MinPhases = 1;
1574
1575 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1576 table->VceLevel[count].Frequency, &dividers);
1577 PP_ASSERT_WITH_CODE((0 == result),
1578 "can not find divide id for VCE engine clock",
1579 return result);
1580
1581 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1582
1583 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1584 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
1585 }
1586 return result;
1587 }
1588
1589 static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1590 SMU7_Discrete_DpmTable *table)
1591 {
1592 int result = -EINVAL;
1593 uint8_t count;
1594 struct pp_atomctrl_clock_dividers_vi dividers;
1595 struct phm_acp_clock_voltage_dependency_table *acp_table =
1596 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
1597
1598 table->AcpLevelCount = (uint8_t)(acp_table->count);
1599 table->AcpBootLevel = 0;
1600
1601 for (count = 0; count < table->AcpLevelCount; count++) {
1602 table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;
1603 table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
1604 table->AcpLevel[count].MinPhases = 1;
1605
1606 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1607 table->AcpLevel[count].Frequency, &dividers);
1608 PP_ASSERT_WITH_CODE((0 == result),
1609 "can not find divide id for engine clock", return result);
1610
1611 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1612
1613 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1614 CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);
1615 }
1616 return result;
1617 }
1618
1619 static int ci_populate_memory_timing_parameters(
1620 struct pp_hwmgr *hwmgr,
1621 uint32_t engine_clock,
1622 uint32_t memory_clock,
1623 struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs
1624 )
1625 {
1626 uint32_t dramTiming;
1627 uint32_t dramTiming2;
1628 uint32_t burstTime;
1629 int result;
1630
1631 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1632 engine_clock, memory_clock);
1633
1634 PP_ASSERT_WITH_CODE(result == 0,
1635 "Error calling VBIOS to set DRAM_TIMING.", return result);
1636
1637 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1638 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1639 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1640
1641 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1642 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1643 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1644
1645 return 0;
1646 }
1647
1648 static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1649 {
1650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1651 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1652 int result = 0;
1653 SMU7_Discrete_MCArbDramTimingTable arb_regs;
1654 uint32_t i, j;
1655
1656 memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable));
1657
1658 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1659 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1660 result = ci_populate_memory_timing_parameters
1661 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1662 data->dpm_table.mclk_table.dpm_levels[j].value,
1663 &arb_regs.entries[i][j]);
1664
1665 if (0 != result)
1666 break;
1667 }
1668 }
1669
1670 if (0 == result) {
1671 result = ci_copy_bytes_to_smc(
1672 hwmgr,
1673 smu_data->arb_table_start,
1674 (uint8_t *)&arb_regs,
1675 sizeof(SMU7_Discrete_MCArbDramTimingTable),
1676 SMC_RAM_END
1677 );
1678 }
1679
1680 return result;
1681 }
1682
1683 static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1684 SMU7_Discrete_DpmTable *table)
1685 {
1686 int result = 0;
1687 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1688 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1689
1690 table->GraphicsBootLevel = 0;
1691 table->MemoryBootLevel = 0;
1692
1693 /* find boot level from dpm table*/
1694 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1695 data->vbios_boot_state.sclk_bootup_value,
1696 (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1697
1698 if (0 != result) {
1699 smu_data->smc_state_table.GraphicsBootLevel = 0;
1700 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1701 result = 0;
1702 }
1703
1704 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1705 data->vbios_boot_state.mclk_bootup_value,
1706 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1707
1708 if (0 != result) {
1709 smu_data->smc_state_table.MemoryBootLevel = 0;
1710 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1711 result = 0;
1712 }
1713
1714 table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1715 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1716 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1717
1718 return result;
1719 }
1720
1721 static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1722 SMU7_Discrete_MCRegisters *mc_reg_table)
1723 {
1724 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
1725
1726 uint32_t i, j;
1727
1728 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
1729 if (smu_data->mc_reg_table.validflag & 1<<j) {
1730 PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,
1731 "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
1732 mc_reg_table->address[i].s0 =
1733 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1734 mc_reg_table->address[i].s1 =
1735 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
1736 i++;
1737 }
1738 }
1739
1740 mc_reg_table->last = (uint8_t)i;
1741
1742 return 0;
1743 }
1744
1745 static void ci_convert_mc_registers(
1746 const struct ci_mc_reg_entry *entry,
1747 SMU7_Discrete_MCRegisterSet *data,
1748 uint32_t num_entries, uint32_t valid_flag)
1749 {
1750 uint32_t i, j;
1751
1752 for (i = 0, j = 0; j < num_entries; j++) {
1753 if (valid_flag & 1<<j) {
1754 data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
1755 i++;
1756 }
1757 }
1758 }
1759
1760 static int ci_convert_mc_reg_table_entry_to_smc(
1761 struct pp_hwmgr *hwmgr,
1762 const uint32_t memory_clock,
1763 SMU7_Discrete_MCRegisterSet *mc_reg_table_data
1764 )
1765 {
1766 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1767 uint32_t i = 0;
1768
1769 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
1770 if (memory_clock <=
1771 smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
1772 break;
1773 }
1774 }
1775
1776 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
1777 --i;
1778
1779 ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
1780 mc_reg_table_data, smu_data->mc_reg_table.last,
1781 smu_data->mc_reg_table.validflag);
1782
1783 return 0;
1784 }
1785
1786 static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1787 SMU7_Discrete_MCRegisters *mc_regs)
1788 {
1789 int result = 0;
1790 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1791 int res;
1792 uint32_t i;
1793
1794 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1795 res = ci_convert_mc_reg_table_entry_to_smc(
1796 hwmgr,
1797 data->dpm_table.mclk_table.dpm_levels[i].value,
1798 &mc_regs->data[i]
1799 );
1800
1801 if (0 != res)
1802 result = res;
1803 }
1804
1805 return result;
1806 }
1807
1808 static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1809 {
1810 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1811 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1812 uint32_t address;
1813 int32_t result;
1814
1815 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
1816 return 0;
1817
1818
1819 memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters));
1820
1821 result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
1822
1823 if (result != 0)
1824 return result;
1825
1826 address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
1827
1828 return ci_copy_bytes_to_smc(hwmgr, address,
1829 (uint8_t *)&smu_data->mc_regs.data[0],
1830 sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1831 SMC_RAM_END);
1832 }
1833
1834 static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1835 {
1836 int result;
1837 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1838
1839 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
1840 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1841 PP_ASSERT_WITH_CODE(0 == result,
1842 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1843
1844 result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
1845 PP_ASSERT_WITH_CODE(0 == result,
1846 "Failed to initialize MCRegTable for driver state!", return result;);
1847
1848 return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
1849 (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
1850 }
1851
1852 static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1853 {
1854 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1855 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1856 uint8_t count, level;
1857
1858 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
1859
1860 for (level = 0; level < count; level++) {
1861 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
1862 >= data->vbios_boot_state.sclk_bootup_value) {
1863 smu_data->smc_state_table.GraphicsBootLevel = level;
1864 break;
1865 }
1866 }
1867
1868 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
1869
1870 for (level = 0; level < count; level++) {
1871 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
1872 >= data->vbios_boot_state.mclk_bootup_value) {
1873 smu_data->smc_state_table.MemoryBootLevel = level;
1874 break;
1875 }
1876 }
1877
1878 return 0;
1879 }
1880
1881 static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1882 SMU7_Discrete_DpmTable *table)
1883 {
1884 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1885
1886 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1887 table->SVI2Enable = 1;
1888 else
1889 table->SVI2Enable = 0;
1890 return 0;
1891 }
1892
1893 static int ci_start_smc(struct pp_hwmgr *hwmgr)
1894 {
1895 /* set smc instruct start point at 0x0 */
1896 ci_program_jump_on_start(hwmgr);
1897
1898 /* enable smc clock */
1899 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
1900
1901 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
1902
1903 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
1904 INTERRUPTS_ENABLED, 1);
1905
1906 return 0;
1907 }
1908
1909 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
1910 {
1911 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1912 uint16_t config;
1913
1914 config = VR_SVI2_PLANE_1;
1915 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1916
1917 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1918 config = VR_SVI2_PLANE_2;
1919 table->VRConfig |= config;
1920 } else {
1921 pr_info("VDDCshould be on SVI2 controller!");
1922 }
1923
1924 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1925 config = VR_SVI2_PLANE_2;
1926 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1927 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1928 config = VR_SMIO_PATTERN_1;
1929 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1930 }
1931
1932 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1933 config = VR_SMIO_PATTERN_2;
1934 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1935 }
1936
1937 return 0;
1938 }
1939
1940 static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
1941 {
1942 int result;
1943 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1944 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1945 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1946 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1947 u32 i;
1948
1949 ci_initialize_power_tune_defaults(hwmgr);
1950 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
1951
1952 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
1953 ci_populate_smc_voltage_tables(hwmgr, table);
1954
1955 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1956 PHM_PlatformCaps_AutomaticDCTransition))
1957 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1958
1959
1960 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1961 PHM_PlatformCaps_StepVddc))
1962 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1963
1964 if (data->is_memory_gddr5)
1965 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1966
1967 if (data->ulv_supported) {
1968 result = ci_populate_ulv_state(hwmgr, &(table->Ulv));
1969 PP_ASSERT_WITH_CODE(0 == result,
1970 "Failed to initialize ULV state!", return result);
1971
1972 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1973 ixCG_ULV_PARAMETER, 0x40035);
1974 }
1975
1976 result = ci_populate_all_graphic_levels(hwmgr);
1977 PP_ASSERT_WITH_CODE(0 == result,
1978 "Failed to initialize Graphics Level!", return result);
1979
1980 result = ci_populate_all_memory_levels(hwmgr);
1981 PP_ASSERT_WITH_CODE(0 == result,
1982 "Failed to initialize Memory Level!", return result);
1983
1984 result = ci_populate_smc_link_level(hwmgr, table);
1985 PP_ASSERT_WITH_CODE(0 == result,
1986 "Failed to initialize Link Level!", return result);
1987
1988 result = ci_populate_smc_acpi_level(hwmgr, table);
1989 PP_ASSERT_WITH_CODE(0 == result,
1990 "Failed to initialize ACPI Level!", return result);
1991
1992 result = ci_populate_smc_vce_level(hwmgr, table);
1993 PP_ASSERT_WITH_CODE(0 == result,
1994 "Failed to initialize VCE Level!", return result);
1995
1996 result = ci_populate_smc_acp_level(hwmgr, table);
1997 PP_ASSERT_WITH_CODE(0 == result,
1998 "Failed to initialize ACP Level!", return result);
1999
2000 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2001 /* need to populate the ARB settings for the initial state. */
2002 result = ci_program_memory_timing_parameters(hwmgr);
2003 PP_ASSERT_WITH_CODE(0 == result,
2004 "Failed to Write ARB settings for the initial state.", return result);
2005
2006 result = ci_populate_smc_uvd_level(hwmgr, table);
2007 PP_ASSERT_WITH_CODE(0 == result,
2008 "Failed to initialize UVD Level!", return result);
2009
2010 table->UvdBootLevel = 0;
2011 table->VceBootLevel = 0;
2012 table->AcpBootLevel = 0;
2013 table->SamuBootLevel = 0;
2014
2015 table->GraphicsBootLevel = 0;
2016 table->MemoryBootLevel = 0;
2017
2018 result = ci_populate_smc_boot_level(hwmgr, table);
2019 PP_ASSERT_WITH_CODE(0 == result,
2020 "Failed to initialize Boot Level!", return result);
2021
2022 result = ci_populate_smc_initial_state(hwmgr);
2023 PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2024
2025 result = ci_populate_bapm_parameters_in_dpm_table(hwmgr);
2026 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2027
2028 table->UVDInterval = 1;
2029 table->VCEInterval = 1;
2030 table->ACPInterval = 1;
2031 table->SAMUInterval = 1;
2032 table->GraphicsVoltageChangeEnable = 1;
2033 table->GraphicsThermThrottleEnable = 1;
2034 table->GraphicsInterval = 1;
2035 table->VoltageInterval = 1;
2036 table->ThermalInterval = 1;
2037
2038 table->TemperatureLimitHigh =
2039 (data->thermal_temp_setting.temperature_high *
2040 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2041 table->TemperatureLimitLow =
2042 (data->thermal_temp_setting.temperature_low *
2043 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2044
2045 table->MemoryVoltageChangeEnable = 1;
2046 table->MemoryInterval = 1;
2047 table->VoltageResponseTime = 0;
2048 table->VddcVddciDelta = 4000;
2049 table->PhaseResponseTime = 0;
2050 table->MemoryThermThrottleEnable = 1;
2051
2052 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2053 "There must be 1 or more PCIE levels defined in PPTable.",
2054 return -EINVAL);
2055
2056 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
2057 table->PCIeGenInterval = 1;
2058
2059 result = ci_populate_vr_config(hwmgr, table);
2060 PP_ASSERT_WITH_CODE(0 == result,
2061 "Failed to populate VRConfig setting!", return result);
2062 data->vr_config = table->VRConfig;
2063
2064 ci_populate_smc_svi2_config(hwmgr, table);
2065
2066 for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
2067 CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]);
2068
2069 table->ThermGpio = 17;
2070 table->SclkStepSize = 0x4000;
2071 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2072 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2073 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2074 PHM_PlatformCaps_RegulatorHot);
2075 } else {
2076 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2077 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2078 PHM_PlatformCaps_RegulatorHot);
2079 }
2080
2081 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2082
2083 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2084 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2086 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2087 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2088 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2089 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2090 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2091 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2092 table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta);
2093 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2094 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2095
2096 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2097 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2098 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2099
2100 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2101 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
2102 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
2103 (uint8_t *)&(table->SystemFlags),
2104 sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
2105 SMC_RAM_END);
2106
2107 PP_ASSERT_WITH_CODE(0 == result,
2108 "Failed to upload dpm data to SMC memory!", return result;);
2109
2110 result = ci_populate_initial_mc_reg_table(hwmgr);
2111 PP_ASSERT_WITH_CODE((0 == result),
2112 "Failed to populate initialize MC Reg table!", return result);
2113
2114 result = ci_populate_pm_fuses(hwmgr);
2115 PP_ASSERT_WITH_CODE(0 == result,
2116 "Failed to populate PM fuses to SMC memory!", return result);
2117
2118 ci_start_smc(hwmgr);
2119
2120 return 0;
2121 }
2122
2123 static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2124 {
2125 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2126 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2127 uint32_t duty100;
2128 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2129 uint16_t fdo_min, slope1, slope2;
2130 uint32_t reference_clock;
2131 int res;
2132 uint64_t tmp64;
2133
2134 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2135 return 0;
2136
2137 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2138 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2139 PHM_PlatformCaps_MicrocodeFanControl);
2140 return 0;
2141 }
2142
2143 if (0 == ci_data->fan_table_start) {
2144 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2145 return 0;
2146 }
2147
2148 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
2149
2150 if (0 == duty100) {
2151 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2152 return 0;
2153 }
2154
2155 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2156 do_div(tmp64, 10000);
2157 fdo_min = (uint16_t)tmp64;
2158
2159 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2160 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2161
2162 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2163 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2164
2165 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2166 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2167
2168 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2169 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2170 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2171
2172 fan_table.Slope1 = cpu_to_be16(slope1);
2173 fan_table.Slope2 = cpu_to_be16(slope2);
2174
2175 fan_table.FdoMin = cpu_to_be16(fdo_min);
2176
2177 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2178
2179 fan_table.HystUp = cpu_to_be16(1);
2180
2181 fan_table.HystSlope = cpu_to_be16(1);
2182
2183 fan_table.TempRespLim = cpu_to_be16(5);
2184
2185 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2186
2187 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2188
2189 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2190
2191 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2192
2193 res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2194
2195 return 0;
2196 }
2197
2198 static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2199 {
2200 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2201
2202 if (data->need_update_smu7_dpm_table &
2203 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2204 return ci_program_memory_timing_parameters(hwmgr);
2205
2206 return 0;
2207 }
2208
2209 static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2210 {
2211 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2212 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2213
2214 int result = 0;
2215 uint32_t low_sclk_interrupt_threshold = 0;
2216
2217 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2218 PHM_PlatformCaps_SclkThrottleLowNotification)
2219 && (data->low_sclk_interrupt_threshold != 0)) {
2220 low_sclk_interrupt_threshold =
2221 data->low_sclk_interrupt_threshold;
2222
2223 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2224
2225 result = ci_copy_bytes_to_smc(
2226 hwmgr,
2227 smu_data->dpm_table_start +
2228 offsetof(SMU7_Discrete_DpmTable,
2229 LowSclkInterruptT),
2230 (uint8_t *)&low_sclk_interrupt_threshold,
2231 sizeof(uint32_t),
2232 SMC_RAM_END);
2233 }
2234
2235 result = ci_update_and_upload_mc_reg_table(hwmgr);
2236
2237 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2238
2239 result = ci_program_mem_timing_parameters(hwmgr);
2240 PP_ASSERT_WITH_CODE((result == 0),
2241 "Failed to program memory timing parameters!",
2242 );
2243
2244 return result;
2245 }
2246
2247 static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
2248 {
2249 switch (type) {
2250 case SMU_SoftRegisters:
2251 switch (member) {
2252 case HandshakeDisables:
2253 return offsetof(SMU7_SoftRegisters, HandshakeDisables);
2254 case VoltageChangeTimeout:
2255 return offsetof(SMU7_SoftRegisters, VoltageChangeTimeout);
2256 case AverageGraphicsActivity:
2257 return offsetof(SMU7_SoftRegisters, AverageGraphicsA);
2258 case AverageMemoryActivity:
2259 return offsetof(SMU7_SoftRegisters, AverageMemoryA);
2260 case PreVBlankGap:
2261 return offsetof(SMU7_SoftRegisters, PreVBlankGap);
2262 case VBlankTimeout:
2263 return offsetof(SMU7_SoftRegisters, VBlankTimeout);
2264 case DRAM_LOG_ADDR_H:
2265 return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
2266 case DRAM_LOG_ADDR_L:
2267 return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
2268 case DRAM_LOG_PHY_ADDR_H:
2269 return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2270 case DRAM_LOG_PHY_ADDR_L:
2271 return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2272 case DRAM_LOG_BUFF_SIZE:
2273 return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2274 }
2275 break;
2276 case SMU_Discrete_DpmTable:
2277 switch (member) {
2278 case LowSclkInterruptThreshold:
2279 return offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT);
2280 }
2281 break;
2282 }
2283 pr_debug("can't get the offset of type %x member %x\n", type, member);
2284 return 0;
2285 }
2286
2287 static uint32_t ci_get_mac_definition(uint32_t value)
2288 {
2289 switch (value) {
2290 case SMU_MAX_LEVELS_GRAPHICS:
2291 return SMU7_MAX_LEVELS_GRAPHICS;
2292 case SMU_MAX_LEVELS_MEMORY:
2293 return SMU7_MAX_LEVELS_MEMORY;
2294 case SMU_MAX_LEVELS_LINK:
2295 return SMU7_MAX_LEVELS_LINK;
2296 case SMU_MAX_ENTRIES_SMIO:
2297 return SMU7_MAX_ENTRIES_SMIO;
2298 case SMU_MAX_LEVELS_VDDC:
2299 return SMU7_MAX_LEVELS_VDDC;
2300 case SMU_MAX_LEVELS_VDDCI:
2301 return SMU7_MAX_LEVELS_VDDCI;
2302 case SMU_MAX_LEVELS_MVDD:
2303 return SMU7_MAX_LEVELS_MVDD;
2304 }
2305
2306 pr_debug("can't get the mac of %x\n", value);
2307 return 0;
2308 }
2309
2310 static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
2311 {
2312 uint32_t byte_count, start_addr;
2313 uint8_t *src;
2314 uint32_t data;
2315
2316 struct cgs_firmware_info info = {0};
2317
2318 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
2319
2320 hwmgr->is_kicker = info.is_kicker;
2321 hwmgr->smu_version = info.version;
2322 byte_count = info.image_size;
2323 src = (uint8_t *)info.kptr;
2324 start_addr = info.ucode_start_address;
2325
2326 if (byte_count > SMC_RAM_END) {
2327 pr_err("SMC address is beyond the SMC RAM area.\n");
2328 return -EINVAL;
2329 }
2330
2331 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
2332 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
2333
2334 for (; byte_count >= 4; byte_count -= 4) {
2335 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
2336 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
2337 src += 4;
2338 }
2339 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
2340
2341 if (0 != byte_count) {
2342 pr_err("SMC size must be divisible by 4\n");
2343 return -EINVAL;
2344 }
2345
2346 return 0;
2347 }
2348
2349 static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
2350 {
2351 if (ci_is_smc_ram_running(hwmgr)) {
2352 pr_info("smc is running, no need to load smc firmware\n");
2353 return 0;
2354 }
2355 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
2356 boot_seq_done, 1);
2357 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
2358 pre_fetcher_en, 1);
2359
2360 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
2361 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
2362 return ci_load_smc_ucode(hwmgr);
2363 }
2364
2365 static int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2366 {
2367 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2368 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2369
2370 uint32_t tmp = 0;
2371 int result;
2372 bool error = false;
2373
2374 if (ci_upload_firmware(hwmgr))
2375 return -EINVAL;
2376
2377 result = ci_read_smc_sram_dword(hwmgr,
2378 SMU7_FIRMWARE_HEADER_LOCATION +
2379 offsetof(SMU7_Firmware_Header, DpmTable),
2380 &tmp, SMC_RAM_END);
2381
2382 if (0 == result)
2383 ci_data->dpm_table_start = tmp;
2384
2385 error |= (0 != result);
2386
2387 result = ci_read_smc_sram_dword(hwmgr,
2388 SMU7_FIRMWARE_HEADER_LOCATION +
2389 offsetof(SMU7_Firmware_Header, SoftRegisters),
2390 &tmp, SMC_RAM_END);
2391
2392 if (0 == result) {
2393 data->soft_regs_start = tmp;
2394 ci_data->soft_regs_start = tmp;
2395 }
2396
2397 error |= (0 != result);
2398
2399 result = ci_read_smc_sram_dword(hwmgr,
2400 SMU7_FIRMWARE_HEADER_LOCATION +
2401 offsetof(SMU7_Firmware_Header, mcRegisterTable),
2402 &tmp, SMC_RAM_END);
2403
2404 if (0 == result)
2405 ci_data->mc_reg_table_start = tmp;
2406
2407 result = ci_read_smc_sram_dword(hwmgr,
2408 SMU7_FIRMWARE_HEADER_LOCATION +
2409 offsetof(SMU7_Firmware_Header, FanTable),
2410 &tmp, SMC_RAM_END);
2411
2412 if (0 == result)
2413 ci_data->fan_table_start = tmp;
2414
2415 error |= (0 != result);
2416
2417 result = ci_read_smc_sram_dword(hwmgr,
2418 SMU7_FIRMWARE_HEADER_LOCATION +
2419 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
2420 &tmp, SMC_RAM_END);
2421
2422 if (0 == result)
2423 ci_data->arb_table_start = tmp;
2424
2425 error |= (0 != result);
2426
2427 result = ci_read_smc_sram_dword(hwmgr,
2428 SMU7_FIRMWARE_HEADER_LOCATION +
2429 offsetof(SMU7_Firmware_Header, Version),
2430 &tmp, SMC_RAM_END);
2431
2432 if (0 == result)
2433 hwmgr->microcode_version_info.SMC = tmp;
2434
2435 error |= (0 != result);
2436
2437 return error ? 1 : 0;
2438 }
2439
2440 static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2441 {
2442 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2443 }
2444
2445 static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2446 {
2447 bool result = true;
2448
2449 switch (in_reg) {
2450 case mmMC_SEQ_RAS_TIMING:
2451 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2452 break;
2453
2454 case mmMC_SEQ_DLL_STBY:
2455 *out_reg = mmMC_SEQ_DLL_STBY_LP;
2456 break;
2457
2458 case mmMC_SEQ_G5PDX_CMD0:
2459 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2460 break;
2461
2462 case mmMC_SEQ_G5PDX_CMD1:
2463 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2464 break;
2465
2466 case mmMC_SEQ_G5PDX_CTRL:
2467 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2468 break;
2469
2470 case mmMC_SEQ_CAS_TIMING:
2471 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2472 break;
2473
2474 case mmMC_SEQ_MISC_TIMING:
2475 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2476 break;
2477
2478 case mmMC_SEQ_MISC_TIMING2:
2479 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2480 break;
2481
2482 case mmMC_SEQ_PMG_DVS_CMD:
2483 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2484 break;
2485
2486 case mmMC_SEQ_PMG_DVS_CTL:
2487 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2488 break;
2489
2490 case mmMC_SEQ_RD_CTL_D0:
2491 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2492 break;
2493
2494 case mmMC_SEQ_RD_CTL_D1:
2495 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2496 break;
2497
2498 case mmMC_SEQ_WR_CTL_D0:
2499 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2500 break;
2501
2502 case mmMC_SEQ_WR_CTL_D1:
2503 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2504 break;
2505
2506 case mmMC_PMG_CMD_EMRS:
2507 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2508 break;
2509
2510 case mmMC_PMG_CMD_MRS:
2511 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2512 break;
2513
2514 case mmMC_PMG_CMD_MRS1:
2515 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2516 break;
2517
2518 case mmMC_SEQ_PMG_TIMING:
2519 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2520 break;
2521
2522 case mmMC_PMG_CMD_MRS2:
2523 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2524 break;
2525
2526 case mmMC_SEQ_WR_CTL_2:
2527 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2528 break;
2529
2530 default:
2531 result = false;
2532 break;
2533 }
2534
2535 return result;
2536 }
2537
2538 static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
2539 {
2540 uint32_t i;
2541 uint16_t address;
2542
2543 for (i = 0; i < table->last; i++) {
2544 table->mc_reg_address[i].s0 =
2545 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2546 ? address : table->mc_reg_address[i].s1;
2547 }
2548 return 0;
2549 }
2550
2551 static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2552 struct ci_mc_reg_table *ni_table)
2553 {
2554 uint8_t i, j;
2555
2556 PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2557 "Invalid VramInfo table.", return -EINVAL);
2558 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2559 "Invalid VramInfo table.", return -EINVAL);
2560
2561 for (i = 0; i < table->last; i++)
2562 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2563
2564 ni_table->last = table->last;
2565
2566 for (i = 0; i < table->num_entries; i++) {
2567 ni_table->mc_reg_table_entry[i].mclk_max =
2568 table->mc_reg_table_entry[i].mclk_max;
2569 for (j = 0; j < table->last; j++) {
2570 ni_table->mc_reg_table_entry[i].mc_data[j] =
2571 table->mc_reg_table_entry[i].mc_data[j];
2572 }
2573 }
2574
2575 ni_table->num_entries = table->num_entries;
2576
2577 return 0;
2578 }
2579
2580 static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2581 struct ci_mc_reg_table *table)
2582 {
2583 uint8_t i, j, k;
2584 uint32_t temp_reg;
2585 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2586
2587 for (i = 0, j = table->last; i < table->last; i++) {
2588 PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2589 "Invalid VramInfo table.", return -EINVAL);
2590
2591 switch (table->mc_reg_address[i].s1) {
2592
2593 case mmMC_SEQ_MISC1:
2594 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
2595 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2596 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2597 for (k = 0; k < table->num_entries; k++) {
2598 table->mc_reg_table_entry[k].mc_data[j] =
2599 ((temp_reg & 0xffff0000)) |
2600 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2601 }
2602 j++;
2603
2604 PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2605 "Invalid VramInfo table.", return -EINVAL);
2606 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
2607 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2608 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2609 for (k = 0; k < table->num_entries; k++) {
2610 table->mc_reg_table_entry[k].mc_data[j] =
2611 (temp_reg & 0xffff0000) |
2612 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2613
2614 if (!data->is_memory_gddr5)
2615 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2616 }
2617 j++;
2618
2619 if (!data->is_memory_gddr5) {
2620 PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2621 "Invalid VramInfo table.", return -EINVAL);
2622 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2623 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2624 for (k = 0; k < table->num_entries; k++) {
2625 table->mc_reg_table_entry[k].mc_data[j] =
2626 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2627 }
2628 j++;
2629 }
2630
2631 break;
2632
2633 case mmMC_SEQ_RESERVE_M:
2634 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
2635 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2636 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2637 for (k = 0; k < table->num_entries; k++) {
2638 table->mc_reg_table_entry[k].mc_data[j] =
2639 (temp_reg & 0xffff0000) |
2640 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2641 }
2642 j++;
2643 break;
2644
2645 default:
2646 break;
2647 }
2648
2649 }
2650
2651 table->last = j;
2652
2653 return 0;
2654 }
2655
2656 static int ci_set_valid_flag(struct ci_mc_reg_table *table)
2657 {
2658 uint8_t i, j;
2659
2660 for (i = 0; i < table->last; i++) {
2661 for (j = 1; j < table->num_entries; j++) {
2662 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2663 table->mc_reg_table_entry[j].mc_data[i]) {
2664 table->validflag |= (1 << i);
2665 break;
2666 }
2667 }
2668 }
2669
2670 return 0;
2671 }
2672
2673 static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2674 {
2675 int result;
2676 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2677 pp_atomctrl_mc_reg_table *table;
2678 struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2679 uint8_t module_index = ci_get_memory_modile_index(hwmgr);
2680
2681 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2682
2683 if (NULL == table)
2684 return -ENOMEM;
2685
2686 /* Program additional LP registers that are no longer programmed by VBIOS */
2687 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2688 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2689 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2690 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2691 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2692 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2693 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2694 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
2695 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
2696 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2697 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
2698 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
2699 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
2700 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
2701 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2702 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2703 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2704 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2705 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
2706 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
2707
2708 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2709
2710 if (0 == result)
2711 result = ci_copy_vbios_smc_reg_table(table, ni_table);
2712
2713 if (0 == result) {
2714 ci_set_s0_mc_reg_index(ni_table);
2715 result = ci_set_mc_special_registers(hwmgr, ni_table);
2716 }
2717
2718 if (0 == result)
2719 ci_set_valid_flag(ni_table);
2720
2721 kfree(table);
2722
2723 return result;
2724 }
2725
2726 static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
2727 {
2728 return ci_is_smc_ram_running(hwmgr);
2729 }
2730
2731 static int ci_smu_init(struct pp_hwmgr *hwmgr)
2732 {
2733 struct ci_smumgr *ci_priv = NULL;
2734
2735 ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
2736
2737 if (ci_priv == NULL)
2738 return -ENOMEM;
2739
2740 hwmgr->smu_backend = ci_priv;
2741
2742 return 0;
2743 }
2744
2745 static int ci_smu_fini(struct pp_hwmgr *hwmgr)
2746 {
2747 kfree(hwmgr->smu_backend);
2748 hwmgr->smu_backend = NULL;
2749 return 0;
2750 }
2751
2752 static int ci_start_smu(struct pp_hwmgr *hwmgr)
2753 {
2754 return 0;
2755 }
2756
2757 static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr,
2758 void *profile_setting)
2759 {
2760 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2761 struct ci_smumgr *smu_data = (struct ci_smumgr *)
2762 (hwmgr->smu_backend);
2763 struct profile_mode_setting *setting;
2764 struct SMU7_Discrete_GraphicsLevel *levels =
2765 smu_data->smc_state_table.GraphicsLevel;
2766 uint32_t array = smu_data->dpm_table_start +
2767 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2768
2769 uint32_t mclk_array = smu_data->dpm_table_start +
2770 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2771 struct SMU7_Discrete_MemoryLevel *mclk_levels =
2772 smu_data->smc_state_table.MemoryLevel;
2773 uint32_t i;
2774 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2775
2776 if (profile_setting == NULL)
2777 return -EINVAL;
2778
2779 setting = (struct profile_mode_setting *)profile_setting;
2780
2781 if (setting->bupdate_sclk) {
2782 if (!data->sclk_dpm_key_disabled)
2783 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
2784 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2785 if (levels[i].ActivityLevel !=
2786 cpu_to_be16(setting->sclk_activity)) {
2787 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2788
2789 clk_activity_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
2790 + offsetof(SMU7_Discrete_GraphicsLevel, ActivityLevel);
2791 offset = clk_activity_offset & ~0x3;
2792 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2793 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2794 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2795
2796 }
2797 if (levels[i].UpH != setting->sclk_up_hyst ||
2798 levels[i].DownH != setting->sclk_down_hyst) {
2799 levels[i].UpH = setting->sclk_up_hyst;
2800 levels[i].DownH = setting->sclk_down_hyst;
2801 up_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
2802 + offsetof(SMU7_Discrete_GraphicsLevel, UpH);
2803 down_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
2804 + offsetof(SMU7_Discrete_GraphicsLevel, DownH);
2805 offset = up_hyst_offset & ~0x3;
2806 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2807 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
2808 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
2809 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2810 }
2811 }
2812 if (!data->sclk_dpm_key_disabled)
2813 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
2814 }
2815
2816 if (setting->bupdate_mclk) {
2817 if (!data->mclk_dpm_key_disabled)
2818 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
2819 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2820 if (mclk_levels[i].ActivityLevel !=
2821 cpu_to_be16(setting->mclk_activity)) {
2822 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2823
2824 clk_activity_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
2825 + offsetof(SMU7_Discrete_MemoryLevel, ActivityLevel);
2826 offset = clk_activity_offset & ~0x3;
2827 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2828 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2829 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2830
2831 }
2832 if (mclk_levels[i].UpH != setting->mclk_up_hyst ||
2833 mclk_levels[i].DownH != setting->mclk_down_hyst) {
2834 mclk_levels[i].UpH = setting->mclk_up_hyst;
2835 mclk_levels[i].DownH = setting->mclk_down_hyst;
2836 up_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
2837 + offsetof(SMU7_Discrete_MemoryLevel, UpH);
2838 down_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
2839 + offsetof(SMU7_Discrete_MemoryLevel, DownH);
2840 offset = up_hyst_offset & ~0x3;
2841 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2842 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
2843 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
2844 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2845 }
2846 }
2847 if (!data->mclk_dpm_key_disabled)
2848 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
2849 }
2850 return 0;
2851 }
2852
2853 static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2854 {
2855 struct amdgpu_device *adev = hwmgr->adev;
2856 struct smu7_hwmgr *data = hwmgr->backend;
2857 struct ci_smumgr *smu_data = hwmgr->smu_backend;
2858 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
2859 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
2860 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2861 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2862 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2863 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2864 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :
2865 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc;
2866 int32_t i;
2867
2868 if (PP_CAP(PHM_PlatformCaps_UVDDPM) || uvd_table->count <= 0)
2869 smu_data->smc_state_table.UvdBootLevel = 0;
2870 else
2871 smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1;
2872
2873 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475,
2874 UvdBootLevel, smu_data->smc_state_table.UvdBootLevel);
2875
2876 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
2877
2878 for (i = uvd_table->count - 1; i >= 0; i--) {
2879 if (uvd_table->entries[i].v <= max_vddc)
2880 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
2881 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM))
2882 break;
2883 }
2884 ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask,
2885 data->dpm_level_enable_mask.uvd_dpm_enable_mask);
2886
2887 return 0;
2888 }
2889
2890 static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2891 {
2892 struct amdgpu_device *adev = hwmgr->adev;
2893 struct smu7_hwmgr *data = hwmgr->backend;
2894 struct phm_vce_clock_voltage_dependency_table *vce_table =
2895 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
2896 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2897 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2898 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2899 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2900 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :
2901 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc;
2902 int32_t i;
2903
2904 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475,
2905 VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/
2906
2907 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
2908
2909 for (i = vce_table->count - 1; i >= 0; i--) {
2910 if (vce_table->entries[i].v <= max_vddc)
2911 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
2912 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM))
2913 break;
2914 }
2915 ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask,
2916 data->dpm_level_enable_mask.vce_dpm_enable_mask);
2917
2918 return 0;
2919 }
2920
2921 static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2922 {
2923 switch (type) {
2924 case SMU_UVD_TABLE:
2925 ci_update_uvd_smc_table(hwmgr);
2926 break;
2927 case SMU_VCE_TABLE:
2928 ci_update_vce_smc_table(hwmgr);
2929 break;
2930 default:
2931 break;
2932 }
2933 return 0;
2934 }
2935
2936 const struct pp_smumgr_func ci_smu_funcs = {
2937 .name = "ci_smu",
2938 .smu_init = ci_smu_init,
2939 .smu_fini = ci_smu_fini,
2940 .start_smu = ci_start_smu,
2941 .check_fw_load_finish = NULL,
2942 .request_smu_load_fw = NULL,
2943 .request_smu_load_specific_fw = NULL,
2944 .send_msg_to_smc = ci_send_msg_to_smc,
2945 .send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,
2946 .download_pptable_settings = NULL,
2947 .upload_pptable_settings = NULL,
2948 .get_offsetof = ci_get_offsetof,
2949 .process_firmware_header = ci_process_firmware_header,
2950 .init_smc_table = ci_init_smc_table,
2951 .update_sclk_threshold = ci_update_sclk_threshold,
2952 .thermal_setup_fan_table = ci_thermal_setup_fan_table,
2953 .populate_all_graphic_levels = ci_populate_all_graphic_levels,
2954 .populate_all_memory_levels = ci_populate_all_memory_levels,
2955 .get_mac_definition = ci_get_mac_definition,
2956 .initialize_mc_reg_table = ci_initialize_mc_reg_table,
2957 .is_dpm_running = ci_is_dpm_running,
2958 .update_dpm_settings = ci_update_dpm_settings,
2959 .update_smc_table = ci_update_smc_table,
2960 };
Linux with added FPC-III support