drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25
  26 #include "smumgr.h"
  27 #include "smu10_inc.h"
  28 #include "soc15_common.h"
  29 #include "smu10_smumgr.h"
  30 #include "ppatomctrl.h"
  31 #include "rv_ppsmc.h"
  32 #include "smu10_driver_if.h"
  33 #include "smu10.h"
  34 #include "pp_debug.h"
  35
  36
  37 #define BUFFER_SIZE                 80000
  38 #define MAX_STRING_SIZE             15
  39 #define BUFFER_SIZETWO              131072
  40
  41 #define MP0_Public                  0x03800000
  42 #define MP0_SRAM                    0x03900000
  43 #define MP1_Public                  0x03b00000
  44 #define MP1_SRAM                    0x03c00004
  45
  46 #define smnMP1_FIRMWARE_FLAGS       0x3010028
  47
  48
  49 static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
  50 {
  51         struct amdgpu_device *adev = hwmgr->adev;
  52         uint32_t reg;
  53
  54         reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  55
  56         phm_wait_for_register_unequal(hwmgr, reg,
  57                         0, MP1_C2PMSG_90__CONTENT_MASK);
  58
  59         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  60 }
  61
  62 static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  63                 uint16_t msg)
  64 {
  65         struct amdgpu_device *adev = hwmgr->adev;
  66
  67         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  68
  69         return 0;
  70 }
  71
  72 static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
  73 {
  74         struct amdgpu_device *adev = hwmgr->adev;
  75
  76         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  77 }
  78
  79 static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
  80 {
  81         struct amdgpu_device *adev = hwmgr->adev;
  82
  83         smu10_wait_for_response(hwmgr);
  84
  85         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
  86
  87         smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
  88
  89         if (smu10_wait_for_response(hwmgr) == 0)
  90                 printk("Failed to send Message %x.\n", msg);
  91
  92         return 0;
  93 }
  94
  95
  96 static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
  97                 uint16_t msg, uint32_t parameter)
  98 {
  99         struct amdgpu_device *adev = hwmgr->adev;
 100
 101         smu10_wait_for_response(hwmgr);
 102
 103         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 104
 105         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 106
 107         smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
 108
 109
 110         if (smu10_wait_for_response(hwmgr) == 0)
 111                 printk("Failed to send Message %x.\n", msg);
 112
 113         return 0;
 114 }
 115
 116 static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
 117                 uint8_t *table, int16_t table_id)
 118 {
 119         struct smu10_smumgr *priv =
 120                         (struct smu10_smumgr *)(hwmgr->smu_backend);
 121         struct amdgpu_device *adev = hwmgr->adev;
 122
 123         PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 124                         "Invalid SMU Table ID!", return -EINVAL;);
 125         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 126                         "Invalid SMU Table version!", return -EINVAL;);
 127         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 128                         "Invalid SMU Table Length!", return -EINVAL;);
 129         smu10_send_msg_to_smc_with_parameter(hwmgr,
 130                         PPSMC_MSG_SetDriverDramAddrHigh,
 131                         upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 132         smu10_send_msg_to_smc_with_parameter(hwmgr,
 133                         PPSMC_MSG_SetDriverDramAddrLow,
 134                         lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 135         smu10_send_msg_to_smc_with_parameter(hwmgr,
 136                         PPSMC_MSG_TransferTableSmu2Dram,
 137                         priv->smu_tables.entry[table_id].table_id);
 138
 139         /* flush hdp cache */
 140         amdgpu_asic_flush_hdp(adev, NULL);
 141
 142         memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
 143                         priv->smu_tables.entry[table_id].size);
 144
 145         return 0;
 146 }
 147
 148 static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 149                 uint8_t *table, int16_t table_id)
 150 {
 151         struct smu10_smumgr *priv =
 152                         (struct smu10_smumgr *)(hwmgr->smu_backend);
 153         struct amdgpu_device *adev = hwmgr->adev;
 154
 155         PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 156                         "Invalid SMU Table ID!", return -EINVAL;);
 157         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 158                         "Invalid SMU Table version!", return -EINVAL;);
 159         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 160                         "Invalid SMU Table Length!", return -EINVAL;);
 161
 162         memcpy(priv->smu_tables.entry[table_id].table, table,
 163                         priv->smu_tables.entry[table_id].size);
 164
 165         amdgpu_asic_flush_hdp(adev, NULL);
 166
 167         smu10_send_msg_to_smc_with_parameter(hwmgr,
 168                         PPSMC_MSG_SetDriverDramAddrHigh,
 169                         upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 170         smu10_send_msg_to_smc_with_parameter(hwmgr,
 171                         PPSMC_MSG_SetDriverDramAddrLow,
 172                         lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 173         smu10_send_msg_to_smc_with_parameter(hwmgr,
 174                         PPSMC_MSG_TransferTableDram2Smu,
 175                         priv->smu_tables.entry[table_id].table_id);
 176
 177         return 0;
 178 }
 179
 180 static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
 181 {
 182         uint32_t smc_driver_if_version;
 183
 184         smu10_send_msg_to_smc(hwmgr,
 185                         PPSMC_MSG_GetDriverIfVersion);
 186         smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
 187
 188         if ((smc_driver_if_version != SMU10_DRIVER_IF_VERSION) &&
 189             (smc_driver_if_version != SMU10_DRIVER_IF_VERSION + 1)) {
 190                 pr_err("Attempt to read SMC IF Version Number Failed!\n");
 191                 return -EINVAL;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
 198 {
 199         struct smu10_smumgr *priv =
 200                         (struct smu10_smumgr *)(hwmgr->smu_backend);
 201
 202         if (priv) {
 203                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
 204                                         &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 205                                         &priv->smu_tables.entry[SMU10_WMTABLE].table);
 206                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
 207                                         &priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
 208                                         &priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
 209                 kfree(hwmgr->smu_backend);
 210                 hwmgr->smu_backend = NULL;
 211         }
 212
 213         return 0;
 214 }
 215
 216 static int smu10_start_smu(struct pp_hwmgr *hwmgr)
 217 {
 218         struct amdgpu_device *adev = hwmgr->adev;
 219
 220         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 221         hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
 222         adev->pm.fw_version = hwmgr->smu_version >> 8;
 223
 224         if (adev->rev_id < 0x8 && adev->pdev->device != 0x15d8 &&
 225             adev->pm.fw_version < 0x1e45)
 226                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 227
 228         if (smu10_verify_smc_interface(hwmgr))
 229                 return -EINVAL;
 230
 231         return 0;
 232 }
 233
 234 static int smu10_smu_init(struct pp_hwmgr *hwmgr)
 235 {
 236         struct smu10_smumgr *priv;
 237         int r;
 238
 239         priv = kzalloc(sizeof(struct smu10_smumgr), GFP_KERNEL);
 240
 241         if (!priv)
 242                 return -ENOMEM;
 243
 244         hwmgr->smu_backend = priv;
 245
 246         /* allocate space for watermarks table */
 247         r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 248                         sizeof(Watermarks_t),
 249                         PAGE_SIZE,
 250                         AMDGPU_GEM_DOMAIN_VRAM,
 251                         &priv->smu_tables.entry[SMU10_WMTABLE].handle,
 252                         &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 253                         &priv->smu_tables.entry[SMU10_WMTABLE].table);
 254
 255         if (r)
 256                 goto err0;
 257
 258         priv->smu_tables.entry[SMU10_WMTABLE].version = 0x01;
 259         priv->smu_tables.entry[SMU10_WMTABLE].size = sizeof(Watermarks_t);
 260         priv->smu_tables.entry[SMU10_WMTABLE].table_id = TABLE_WATERMARKS;
 261
 262         /* allocate space for watermarks table */
 263         r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 264                         sizeof(DpmClocks_t),
 265                         PAGE_SIZE,
 266                         AMDGPU_GEM_DOMAIN_VRAM,
 267                         &priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
 268                         &priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
 269                         &priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
 270
 271         if (r)
 272                 goto err1;
 273
 274         priv->smu_tables.entry[SMU10_CLOCKTABLE].version = 0x01;
 275         priv->smu_tables.entry[SMU10_CLOCKTABLE].size = sizeof(DpmClocks_t);
 276         priv->smu_tables.entry[SMU10_CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
 277
 278         return 0;
 279
 280 err1:
 281         amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
 282                                 &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 283                                 &priv->smu_tables.entry[SMU10_WMTABLE].table);
 284 err0:
 285         kfree(priv);
 286         return -EINVAL;
 287 }
 288
 289 static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
 290 {
 291         int ret;
 292
 293         if (rw)
 294                 ret = smu10_copy_table_from_smc(hwmgr, table, table_id);
 295         else
 296                 ret = smu10_copy_table_to_smc(hwmgr, table, table_id);
 297
 298         return ret;
 299 }
 300
 301
 302 const struct pp_smumgr_func smu10_smu_funcs = {
 303         .name = "smu10_smu",
 304         .smu_init = &smu10_smu_init,
 305         .smu_fini = &smu10_smu_fini,
 306         .start_smu = &smu10_start_smu,
 307         .request_smu_load_specific_fw = NULL,
 308         .send_msg_to_smc = &smu10_send_msg_to_smc,
 309         .send_msg_to_smc_with_parameter = &smu10_send_msg_to_smc_with_parameter,
 310         .download_pptable_settings = NULL,
 311         .upload_pptable_settings = NULL,
 312         .get_argument = smu10_read_arg_from_smc,
 313         .smc_table_manager = smu10_smc_table_manager,
 314 };
 315
 316