drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "smumgr.h"
  25 #include "vega20_inc.h"
  26 #include "soc15_common.h"
  27 #include "vega20_smumgr.h"
  28 #include "vega20_ppsmc.h"
  29 #include "smu11_driver_if.h"
  30 #include "ppatomctrl.h"
  31 #include "pp_debug.h"
  32 #include "smu_ucode_xfer_vi.h"
  33 #include "smu7_smumgr.h"
  34 #include "vega20_hwmgr.h"
  35
  36 /* MP Apertures */
  37 #define MP0_Public                      0x03800000
  38 #define MP0_SRAM                        0x03900000
  39 #define MP1_Public                      0x03b00000
  40 #define MP1_SRAM                        0x03c00004
  41
  42 /* address block */
  43 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  44 #define smnMP0_FW_INTF                  0x30101c0
  45 #define smnMP1_PUB_CTRL                 0x3010b14
  46
  47 bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  48 {
  49         struct amdgpu_device *adev = hwmgr->adev;
  50         uint32_t mp1_fw_flags;
  51
  52         mp1_fw_flags = RREG32_PCIE(MP1_Public |
  53                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
  54
  55         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
  56             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
  57                 return true;
  58
  59         return false;
  60 }
  61
  62 /*
  63  * Check if SMC has responded to previous message.
  64  *
  65  * @param    smumgr  the address of the powerplay hardware manager.
  66  * @return   TRUE    SMC has responded, FALSE otherwise.
  67  */
  68 static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr)
  69 {
  70         struct amdgpu_device *adev = hwmgr->adev;
  71         uint32_t reg;
  72
  73         reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  74
  75         phm_wait_for_register_unequal(hwmgr, reg,
  76                         0, MP1_C2PMSG_90__CONTENT_MASK);
  77
  78         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  79 }
  80
  81 /*
  82  * Send a message to the SMC, and do not wait for its response.
  83  * @param    smumgr  the address of the powerplay hardware manager.
  84  * @param    msg the message to send.
  85  * @return   Always return 0.
  86  */
  87 static int vega20_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  88                 uint16_t msg)
  89 {
  90         struct amdgpu_device *adev = hwmgr->adev;
  91
  92         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  93
  94         return 0;
  95 }
  96
  97 /*
  98  * Send a message to the SMC, and wait for its response.
  99  * @param    hwmgr  the address of the powerplay hardware manager.
 100  * @param    msg the message to send.
 101  * @return   Always return 0.
 102  */
 103 static int vega20_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 104 {
 105         struct amdgpu_device *adev = hwmgr->adev;
 106         int ret = 0;
 107
 108         vega20_wait_for_response(hwmgr);
 109
 110         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 111
 112         vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
 113
 114         ret = vega20_wait_for_response(hwmgr);
 115         if (ret != PPSMC_Result_OK)
 116                 pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
 117
 118         return (ret == PPSMC_Result_OK) ? 0 : -EIO;
 119 }
 120
 121 /*
 122  * Send a message to the SMC with parameter
 123  * @param    hwmgr:  the address of the powerplay hardware manager.
 124  * @param    msg: the message to send.
 125  * @param    parameter: the parameter to send
 126  * @return   Always return 0.
 127  */
 128 static int vega20_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 129                 uint16_t msg, uint32_t parameter)
 130 {
 131         struct amdgpu_device *adev = hwmgr->adev;
 132         int ret = 0;
 133
 134         vega20_wait_for_response(hwmgr);
 135
 136         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 137
 138         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 139
 140         vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
 141
 142         ret = vega20_wait_for_response(hwmgr);
 143         if (ret != PPSMC_Result_OK)
 144                 pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
 145
 146         return (ret == PPSMC_Result_OK) ? 0 : -EIO;
 147 }
 148
 149 static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
 150 {
 151         struct amdgpu_device *adev = hwmgr->adev;
 152
 153         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 154 }
 155
 156 /*
 157  * Copy table from SMC into driver FB
 158  * @param   hwmgr    the address of the HW manager
 159  * @param   table_id    the driver's table ID to copy from
 160  */
 161 static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
 162                                       uint8_t *table, int16_t table_id)
 163 {
 164         struct vega20_smumgr *priv =
 165                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 166         struct amdgpu_device *adev = hwmgr->adev;
 167         int ret = 0;
 168
 169         PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
 170                         "Invalid SMU Table ID!", return -EINVAL);
 171         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 172                         "Invalid SMU Table version!", return -EINVAL);
 173         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 174                         "Invalid SMU Table Length!", return -EINVAL);
 175
 176         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 177                         PPSMC_MSG_SetDriverDramAddrHigh,
 178                         upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 179                         "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!",
 180                         return ret);
 181         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 182                         PPSMC_MSG_SetDriverDramAddrLow,
 183                         lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 184                         "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
 185                         return ret);
 186         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 187                         PPSMC_MSG_TransferTableSmu2Dram, table_id)) == 0,
 188                         "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
 189                         return ret);
 190
 191         /* flush hdp cache */
 192         amdgpu_asic_flush_hdp(adev, NULL);
 193
 194         memcpy(table, priv->smu_tables.entry[table_id].table,
 195                         priv->smu_tables.entry[table_id].size);
 196
 197         return 0;
 198 }
 199
 200 /*
 201  * Copy table from Driver FB into SMC
 202  * @param   hwmgr    the address of the HW manager
 203  * @param   table_id    the table to copy from
 204  */
 205 static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 206                                     uint8_t *table, int16_t table_id)
 207 {
 208         struct vega20_smumgr *priv =
 209                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 210         struct amdgpu_device *adev = hwmgr->adev;
 211         int ret = 0;
 212
 213         PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
 214                         "Invalid SMU Table ID!", return -EINVAL);
 215         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 216                         "Invalid SMU Table version!", return -EINVAL);
 217         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 218                         "Invalid SMU Table Length!", return -EINVAL);
 219
 220         memcpy(priv->smu_tables.entry[table_id].table, table,
 221                         priv->smu_tables.entry[table_id].size);
 222
 223         amdgpu_asic_flush_hdp(adev, NULL);
 224
 225         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 226                         PPSMC_MSG_SetDriverDramAddrHigh,
 227                         upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 228                         "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
 229                         return ret);
 230         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 231                         PPSMC_MSG_SetDriverDramAddrLow,
 232                         lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 233                         "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
 234                         return ret);
 235         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 236                         PPSMC_MSG_TransferTableDram2Smu, table_id)) == 0,
 237                         "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
 238                         return ret);
 239
 240         return 0;
 241 }
 242
 243 int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
 244                 uint8_t *table, uint16_t workload_type)
 245 {
 246         struct vega20_smumgr *priv =
 247                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 248         struct amdgpu_device *adev = hwmgr->adev;
 249         int ret = 0;
 250
 251         memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table,
 252                         priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
 253
 254         amdgpu_asic_flush_hdp(adev, NULL);
 255
 256         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 257                         PPSMC_MSG_SetDriverDramAddrHigh,
 258                         upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 259                         "[SetActivityMonitor] Attempt to Set Dram Addr High Failed!",
 260                         return ret);
 261         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 262                         PPSMC_MSG_SetDriverDramAddrLow,
 263                         lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 264                         "[SetActivityMonitor] Attempt to Set Dram Addr Low Failed!",
 265                         return ret);
 266         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 267                         PPSMC_MSG_TransferTableDram2Smu, TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16))) == 0,
 268                         "[SetActivityMonitor] Attempt to Transfer Table To SMU Failed!",
 269                         return ret);
 270
 271         return 0;
 272 }
 273
 274 int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
 275                 uint8_t *table, uint16_t workload_type)
 276 {
 277         struct vega20_smumgr *priv =
 278                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 279         struct amdgpu_device *adev = hwmgr->adev;
 280         int ret = 0;
 281
 282         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 283                         PPSMC_MSG_SetDriverDramAddrHigh,
 284                         upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 285                         "[GetActivityMonitor] Attempt to Set Dram Addr High Failed!",
 286                         return ret);
 287         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 288                         PPSMC_MSG_SetDriverDramAddrLow,
 289                         lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 290                         "[GetActivityMonitor] Attempt to Set Dram Addr Low Failed!",
 291                         return ret);
 292         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 293                         PPSMC_MSG_TransferTableSmu2Dram,
 294                         TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16))) == 0,
 295                         "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!",
 296                         return ret);
 297
 298         /* flush hdp cache */
 299         amdgpu_asic_flush_hdp(adev, NULL);
 300
 301         memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
 302                         priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
 303
 304         return 0;
 305 }
 306
 307 int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
 308                 bool enable, uint64_t feature_mask)
 309 {
 310         uint32_t smu_features_low, smu_features_high;
 311         int ret = 0;
 312
 313         smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
 314         smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
 315
 316         if (enable) {
 317                 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 318                                 PPSMC_MSG_EnableSmuFeaturesLow, smu_features_low)) == 0,
 319                                 "[EnableDisableSMCFeatures] Attemp to enable SMU features Low failed!",
 320                                 return ret);
 321                 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 322                                 PPSMC_MSG_EnableSmuFeaturesHigh, smu_features_high)) == 0,
 323                                 "[EnableDisableSMCFeatures] Attemp to enable SMU features High failed!",
 324                                 return ret);
 325         } else {
 326                 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 327                                 PPSMC_MSG_DisableSmuFeaturesLow, smu_features_low)) == 0,
 328                                 "[EnableDisableSMCFeatures] Attemp to disable SMU features Low failed!",
 329                                 return ret);
 330                 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 331                                 PPSMC_MSG_DisableSmuFeaturesHigh, smu_features_high)) == 0,
 332                                 "[EnableDisableSMCFeatures] Attemp to disable SMU features High failed!",
 333                                 return ret);
 334         }
 335
 336         return 0;
 337 }
 338
 339 int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
 340                 uint64_t *features_enabled)
 341 {
 342         uint32_t smc_features_low, smc_features_high;
 343         int ret = 0;
 344
 345         if (features_enabled == NULL)
 346                 return -EINVAL;
 347
 348         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
 349                         PPSMC_MSG_GetEnabledSmuFeaturesLow)) == 0,
 350                         "[GetEnabledSMCFeatures] Attemp to get SMU features Low failed!",
 351                         return ret);
 352         smc_features_low = vega20_get_argument(hwmgr);
 353         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
 354                         PPSMC_MSG_GetEnabledSmuFeaturesHigh)) == 0,
 355                         "[GetEnabledSMCFeatures] Attemp to get SMU features High failed!",
 356                         return ret);
 357         smc_features_high = vega20_get_argument(hwmgr);
 358
 359         *features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
 360                         (((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
 361
 362         return 0;
 363 }
 364
 365 static int vega20_set_tools_address(struct pp_hwmgr *hwmgr)
 366 {
 367         struct vega20_smumgr *priv =
 368                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 369         int ret = 0;
 370
 371         if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr) {
 372                 ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 373                                 PPSMC_MSG_SetToolsDramAddrHigh,
 374                                 upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
 375                 if (!ret)
 376                         ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 377                                         PPSMC_MSG_SetToolsDramAddrLow,
 378                                         lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
 379         }
 380
 381         return ret;
 382 }
 383
 384 int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr)
 385 {
 386         struct vega20_smumgr *priv =
 387                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 388         int ret = 0;
 389
 390         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 391                         PPSMC_MSG_SetDriverDramAddrHigh,
 392                         upper_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr))) == 0,
 393                         "[SetPPtabeDriverAddress] Attempt to Set Dram Addr High Failed!",
 394                         return ret);
 395         PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 396                         PPSMC_MSG_SetDriverDramAddrLow,
 397                         lower_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr))) == 0,
 398                         "[SetPPtabeDriverAddress] Attempt to Set Dram Addr Low Failed!",
 399                         return ret);
 400
 401         return ret;
 402 }
 403
 404 static int vega20_smu_init(struct pp_hwmgr *hwmgr)
 405 {
 406         struct vega20_smumgr *priv;
 407         unsigned long tools_size = 0x19000;
 408         int ret = 0;
 409
 410         struct cgs_firmware_info info = {0};
 411
 412         ret = cgs_get_firmware_info(hwmgr->device,
 413                                 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
 414                                 &info);
 415         if (ret || !info.kptr)
 416                 return -EINVAL;
 417
 418         priv = kzalloc(sizeof(struct vega20_smumgr), GFP_KERNEL);
 419         if (!priv)
 420                 return -ENOMEM;
 421
 422         hwmgr->smu_backend = priv;
 423
 424         /* allocate space for pptable */
 425         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 426                         sizeof(PPTable_t),
 427                         PAGE_SIZE,
 428                         AMDGPU_GEM_DOMAIN_VRAM,
 429                         &priv->smu_tables.entry[TABLE_PPTABLE].handle,
 430                         &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 431                         &priv->smu_tables.entry[TABLE_PPTABLE].table);
 432         if (ret)
 433                 goto free_backend;
 434
 435         priv->smu_tables.entry[TABLE_PPTABLE].version = 0x01;
 436         priv->smu_tables.entry[TABLE_PPTABLE].size = sizeof(PPTable_t);
 437
 438         /* allocate space for watermarks table */
 439         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 440                         sizeof(Watermarks_t),
 441                         PAGE_SIZE,
 442                         AMDGPU_GEM_DOMAIN_VRAM,
 443                         &priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 444                         &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 445                         &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 446         if (ret)
 447                 goto err0;
 448
 449         priv->smu_tables.entry[TABLE_WATERMARKS].version = 0x01;
 450         priv->smu_tables.entry[TABLE_WATERMARKS].size = sizeof(Watermarks_t);
 451
 452         /* allocate space for pmstatuslog table */
 453         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 454                         tools_size,
 455                         PAGE_SIZE,
 456                         AMDGPU_GEM_DOMAIN_VRAM,
 457                         &priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 458                         &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 459                         &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 460         if (ret)
 461                 goto err1;
 462
 463         priv->smu_tables.entry[TABLE_PMSTATUSLOG].version = 0x01;
 464         priv->smu_tables.entry[TABLE_PMSTATUSLOG].size = tools_size;
 465
 466         /* allocate space for OverDrive table */
 467         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 468                         sizeof(OverDriveTable_t),
 469                         PAGE_SIZE,
 470                         AMDGPU_GEM_DOMAIN_VRAM,
 471                         &priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 472                         &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 473                         &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 474         if (ret)
 475                 goto err2;
 476
 477         priv->smu_tables.entry[TABLE_OVERDRIVE].version = 0x01;
 478         priv->smu_tables.entry[TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t);
 479
 480         /* allocate space for SmuMetrics table */
 481         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 482                         sizeof(SmuMetrics_t),
 483                         PAGE_SIZE,
 484                         AMDGPU_GEM_DOMAIN_VRAM,
 485                         &priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 486                         &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 487                         &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 488         if (ret)
 489                 goto err3;
 490
 491         priv->smu_tables.entry[TABLE_SMU_METRICS].version = 0x01;
 492         priv->smu_tables.entry[TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t);
 493
 494         /* allocate space for ActivityMonitor table */
 495         ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 496                         sizeof(DpmActivityMonitorCoeffInt_t),
 497                         PAGE_SIZE,
 498                         AMDGPU_GEM_DOMAIN_VRAM,
 499                         &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
 500                         &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
 501                         &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
 502         if (ret)
 503                 goto err4;
 504
 505         priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].version = 0x01;
 506         priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t);
 507
 508         return 0;
 509
 510 err4:
 511         amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 512                         &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 513                         &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 514 err3:
 515         amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 516                         &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 517                         &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 518 err2:
 519         amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 520                         &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 521                         &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 522 err1:
 523         amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 524                         &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 525                         &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 526 err0:
 527         amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
 528                         &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 529                         &priv->smu_tables.entry[TABLE_PPTABLE].table);
 530 free_backend:
 531         kfree(hwmgr->smu_backend);
 532
 533         return -EINVAL;
 534 }
 535
 536 static int vega20_smu_fini(struct pp_hwmgr *hwmgr)
 537 {
 538         struct vega20_smumgr *priv =
 539                         (struct vega20_smumgr *)(hwmgr->smu_backend);
 540
 541         if (priv) {
 542                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
 543                                 &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 544                                 &priv->smu_tables.entry[TABLE_PPTABLE].table);
 545                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 546                                 &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 547                                 &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 548                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 549                                 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 550                                 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 551                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 552                                 &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 553                                 &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 554                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 555                                 &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 556                                 &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 557                 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
 558                                 &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
 559                                 &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
 560                 kfree(hwmgr->smu_backend);
 561                 hwmgr->smu_backend = NULL;
 562         }
 563         return 0;
 564 }
 565
 566 static int vega20_start_smu(struct pp_hwmgr *hwmgr)
 567 {
 568         int ret;
 569
 570         ret = vega20_is_smc_ram_running(hwmgr);
 571         PP_ASSERT_WITH_CODE(ret,
 572                         "[Vega20StartSmu] SMC is not running!",
 573                         return -EINVAL);
 574
 575         ret = vega20_set_tools_address(hwmgr);
 576         PP_ASSERT_WITH_CODE(!ret,
 577                         "[Vega20StartSmu] Failed to set tools address!",
 578                         return ret);
 579
 580         return 0;
 581 }
 582
 583 static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
 584 {
 585         uint64_t features_enabled = 0;
 586
 587         vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 588
 589         if (features_enabled & SMC_DPM_FEATURES)
 590                 return true;
 591         else
 592                 return false;
 593 }
 594
 595 static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
 596                                     uint16_t table_id, bool rw)
 597 {
 598         int ret;
 599
 600         if (rw)
 601                 ret = vega20_copy_table_from_smc(hwmgr, table, table_id);
 602         else
 603                 ret = vega20_copy_table_to_smc(hwmgr, table, table_id);
 604
 605         return ret;
 606 }
 607
 608 const struct pp_smumgr_func vega20_smu_funcs = {
 609         .name = "vega20_smu",
 610         .smu_init = &vega20_smu_init,
 611         .smu_fini = &vega20_smu_fini,
 612         .start_smu = &vega20_start_smu,
 613         .request_smu_load_specific_fw = NULL,
 614         .send_msg_to_smc = &vega20_send_msg_to_smc,
 615         .send_msg_to_smc_with_parameter = &vega20_send_msg_to_smc_with_parameter,
 616         .download_pptable_settings = NULL,
 617         .upload_pptable_settings = NULL,
 618         .is_dpm_running = vega20_is_dpm_running,
 619         .get_argument = vega20_get_argument,
 620         .smc_table_manager = vega20_smc_table_manager,
 621 };