drivers/gpu/drm/amd/powerplay/vega20_ppt.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __VEGA20_PPT_H__
  24 #define __VEGA20_PPT_H__
  25
  26 #define VEGA20_UMD_PSTATE_GFXCLK_LEVEL         0x3
  27 #define VEGA20_UMD_PSTATE_SOCCLK_LEVEL         0x3
  28 #define VEGA20_UMD_PSTATE_MCLK_LEVEL           0x2
  29 #define VEGA20_UMD_PSTATE_UVDCLK_LEVEL         0x3
  30 #define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL        0x3
  31
  32 #define MAX_REGULAR_DPM_NUMBER 16
  33 #define MAX_PCIE_CONF 2
  34
  35 #define VOLTAGE_SCALE 4
  36 #define AVFS_CURVE 0
  37 #define OD8_HOTCURVE_TEMPERATURE 85
  38
  39 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  40 #define SMU_FEATURES_LOW_SHIFT       0
  41 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  42 #define SMU_FEATURES_HIGH_SHIFT      32
  43
  44 enum {
  45         GNLD_DPM_PREFETCHER = 0,
  46         GNLD_DPM_GFXCLK,
  47         GNLD_DPM_UCLK,
  48         GNLD_DPM_SOCCLK,
  49         GNLD_DPM_UVD,
  50         GNLD_DPM_VCE,
  51         GNLD_ULV,
  52         GNLD_DPM_MP0CLK,
  53         GNLD_DPM_LINK,
  54         GNLD_DPM_DCEFCLK,
  55         GNLD_DS_GFXCLK,
  56         GNLD_DS_SOCCLK,
  57         GNLD_DS_LCLK,
  58         GNLD_PPT,
  59         GNLD_TDC,
  60         GNLD_THERMAL,
  61         GNLD_GFX_PER_CU_CG,
  62         GNLD_RM,
  63         GNLD_DS_DCEFCLK,
  64         GNLD_ACDC,
  65         GNLD_VR0HOT,
  66         GNLD_VR1HOT,
  67         GNLD_FW_CTF,
  68         GNLD_LED_DISPLAY,
  69         GNLD_FAN_CONTROL,
  70         GNLD_DIDT,
  71         GNLD_GFXOFF,
  72         GNLD_CG,
  73         GNLD_DPM_FCLK,
  74         GNLD_DS_FCLK,
  75         GNLD_DS_MP1CLK,
  76         GNLD_DS_MP0CLK,
  77         GNLD_XGMI,
  78         GNLD_ECC,
  79
  80         GNLD_FEATURES_MAX
  81 };
  82
  83 struct vega20_dpm_level {
  84         bool            enabled;
  85         uint32_t        value;
  86         uint32_t        param1;
  87 };
  88
  89 struct vega20_dpm_state {
  90         uint32_t  soft_min_level;
  91         uint32_t  soft_max_level;
  92         uint32_t  hard_min_level;
  93         uint32_t  hard_max_level;
  94 };
  95
  96 struct vega20_single_dpm_table {
  97         uint32_t                count;
  98         struct vega20_dpm_state dpm_state;
  99         struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
 100 };
 101
 102 struct vega20_pcie_table {
 103         uint16_t count;
 104         uint8_t  pcie_gen[MAX_PCIE_CONF];
 105         uint8_t  pcie_lane[MAX_PCIE_CONF];
 106         uint32_t lclk[MAX_PCIE_CONF];
 107 };
 108
 109 struct vega20_dpm_table {
 110         struct vega20_single_dpm_table  soc_table;
 111         struct vega20_single_dpm_table  gfx_table;
 112         struct vega20_single_dpm_table  mem_table;
 113         struct vega20_single_dpm_table  eclk_table;
 114         struct vega20_single_dpm_table  vclk_table;
 115         struct vega20_single_dpm_table  dclk_table;
 116         struct vega20_single_dpm_table  dcef_table;
 117         struct vega20_single_dpm_table  pixel_table;
 118         struct vega20_single_dpm_table  display_table;
 119         struct vega20_single_dpm_table  phy_table;
 120         struct vega20_single_dpm_table  fclk_table;
 121         struct vega20_pcie_table        pcie_table;
 122 };
 123
 124 enum OD8_FEATURE_ID
 125 {
 126         OD8_GFXCLK_LIMITS               = 1 << 0,
 127         OD8_GFXCLK_CURVE                = 1 << 1,
 128         OD8_UCLK_MAX                    = 1 << 2,
 129         OD8_POWER_LIMIT                 = 1 << 3,
 130         OD8_ACOUSTIC_LIMIT_SCLK         = 1 << 4,   //FanMaximumRpm
 131         OD8_FAN_SPEED_MIN               = 1 << 5,   //FanMinimumPwm
 132         OD8_TEMPERATURE_FAN             = 1 << 6,   //FanTargetTemperature
 133         OD8_TEMPERATURE_SYSTEM          = 1 << 7,   //MaxOpTemp
 134         OD8_MEMORY_TIMING_TUNE          = 1 << 8,
 135         OD8_FAN_ZERO_RPM_CONTROL        = 1 << 9
 136 };
 137
 138 enum OD8_SETTING_ID
 139 {
 140         OD8_SETTING_GFXCLK_FMIN = 0,
 141         OD8_SETTING_GFXCLK_FMAX,
 142         OD8_SETTING_GFXCLK_FREQ1,
 143         OD8_SETTING_GFXCLK_VOLTAGE1,
 144         OD8_SETTING_GFXCLK_FREQ2,
 145         OD8_SETTING_GFXCLK_VOLTAGE2,
 146         OD8_SETTING_GFXCLK_FREQ3,
 147         OD8_SETTING_GFXCLK_VOLTAGE3,
 148         OD8_SETTING_UCLK_FMAX,
 149         OD8_SETTING_POWER_PERCENTAGE,
 150         OD8_SETTING_FAN_ACOUSTIC_LIMIT,
 151         OD8_SETTING_FAN_MIN_SPEED,
 152         OD8_SETTING_FAN_TARGET_TEMP,
 153         OD8_SETTING_OPERATING_TEMP_MAX,
 154         OD8_SETTING_AC_TIMING,
 155         OD8_SETTING_FAN_ZERO_RPM_CONTROL,
 156         OD8_SETTING_COUNT
 157 };
 158
 159 struct vega20_od8_single_setting {
 160         uint32_t        feature_id;
 161         int32_t         min_value;
 162         int32_t         max_value;
 163         int32_t         current_value;
 164         int32_t         default_value;
 165 };
 166
 167 struct vega20_od8_settings {
 168         struct vega20_od8_single_setting        od8_settings_array[OD8_SETTING_COUNT];
 169         uint8_t                         *od_feature_capabilities;
 170         uint32_t                        *od_settings_max;
 171         uint32_t                        *od_settings_min;
 172         void                            *od8_settings;
 173         bool                            od_gfxclk_update;
 174         bool                            od_memclk_update;
 175 };
 176
 177 extern void vega20_set_ppt_funcs(struct smu_context *smu);
 178
 179 #endif