treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / arc / arcpgu_crtc.c
blob8ae1e1f97a735a40391adb2e772b0ba19f4dde58
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ARC PGU DRM driver.
5 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
6 */
8 #include <drm/drm_atomic_helper.h>
9 #include <drm/drm_device.h>
10 #include <drm/drm_fb_cma_helper.h>
11 #include <drm/drm_gem_cma_helper.h>
12 #include <drm/drm_vblank.h>
13 #include <drm/drm_plane_helper.h>
14 #include <drm/drm_probe_helper.h>
15 #include <linux/clk.h>
16 #include <linux/platform_data/simplefb.h>
18 #include "arcpgu.h"
19 #include "arcpgu_regs.h"
21 #define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
23 static const u32 arc_pgu_supported_formats[] = {
24 DRM_FORMAT_RGB565,
25 DRM_FORMAT_XRGB8888,
26 DRM_FORMAT_ARGB8888,
29 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
31 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
32 const struct drm_framebuffer *fb = crtc->primary->state->fb;
33 uint32_t pixel_format = fb->format->format;
34 u32 format = DRM_FORMAT_INVALID;
35 int i;
36 u32 reg_ctrl;
38 for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) {
39 if (arc_pgu_supported_formats[i] == pixel_format)
40 format = arc_pgu_supported_formats[i];
43 if (WARN_ON(format == DRM_FORMAT_INVALID))
44 return;
46 reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
47 if (format == DRM_FORMAT_RGB565)
48 reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
49 else
50 reg_ctrl |= ARCPGU_MODE_XRGB8888;
51 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
54 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
55 .destroy = drm_crtc_cleanup,
56 .set_config = drm_atomic_helper_set_config,
57 .page_flip = drm_atomic_helper_page_flip,
58 .reset = drm_atomic_helper_crtc_reset,
59 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
60 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
63 static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
64 const struct drm_display_mode *mode)
66 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
67 long rate, clk_rate = mode->clock * 1000;
68 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
70 rate = clk_round_rate(arcpgu->clk, clk_rate);
71 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
72 return MODE_OK;
74 return MODE_NOCLOCK;
77 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
79 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
80 struct drm_display_mode *m = &crtc->state->adjusted_mode;
81 u32 val;
83 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
84 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
86 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
87 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
88 m->crtc_hsync_end - m->crtc_hdisplay));
90 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
91 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
92 m->crtc_vsync_end - m->crtc_vdisplay));
94 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
95 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
96 m->crtc_vblank_end - m->crtc_vblank_start));
98 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
100 if (m->flags & DRM_MODE_FLAG_PVSYNC)
101 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
102 else
103 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
105 if (m->flags & DRM_MODE_FLAG_PHSYNC)
106 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
107 else
108 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
110 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
111 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
112 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
114 arc_pgu_set_pxl_fmt(crtc);
116 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
119 static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
120 struct drm_crtc_state *old_state)
122 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
124 clk_prepare_enable(arcpgu->clk);
125 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
126 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
127 ARCPGU_CTRL_ENABLE_MASK);
130 static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
131 struct drm_crtc_state *old_state)
133 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
135 clk_disable_unprepare(arcpgu->clk);
136 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
137 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
138 ~ARCPGU_CTRL_ENABLE_MASK);
141 static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
142 struct drm_crtc_state *state)
144 struct drm_pending_vblank_event *event = crtc->state->event;
146 if (event) {
147 crtc->state->event = NULL;
149 spin_lock_irq(&crtc->dev->event_lock);
150 drm_crtc_send_vblank_event(crtc, event);
151 spin_unlock_irq(&crtc->dev->event_lock);
155 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
156 .mode_valid = arc_pgu_crtc_mode_valid,
157 .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
158 .atomic_begin = arc_pgu_crtc_atomic_begin,
159 .atomic_enable = arc_pgu_crtc_atomic_enable,
160 .atomic_disable = arc_pgu_crtc_atomic_disable,
163 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
164 struct drm_plane_state *state)
166 struct arcpgu_drm_private *arcpgu;
167 struct drm_gem_cma_object *gem;
169 if (!plane->state->crtc || !plane->state->fb)
170 return;
172 arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
173 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
174 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
177 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
178 .atomic_update = arc_pgu_plane_atomic_update,
181 static void arc_pgu_plane_destroy(struct drm_plane *plane)
183 drm_plane_cleanup(plane);
186 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
187 .update_plane = drm_atomic_helper_update_plane,
188 .disable_plane = drm_atomic_helper_disable_plane,
189 .destroy = arc_pgu_plane_destroy,
190 .reset = drm_atomic_helper_plane_reset,
191 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
192 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
195 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
197 struct arcpgu_drm_private *arcpgu = drm->dev_private;
198 struct drm_plane *plane = NULL;
199 int ret;
201 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
202 if (!plane)
203 return ERR_PTR(-ENOMEM);
205 ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
206 arc_pgu_supported_formats,
207 ARRAY_SIZE(arc_pgu_supported_formats),
208 NULL,
209 DRM_PLANE_TYPE_PRIMARY, NULL);
210 if (ret)
211 return ERR_PTR(ret);
213 drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
214 arcpgu->plane = plane;
216 return plane;
219 int arc_pgu_setup_crtc(struct drm_device *drm)
221 struct arcpgu_drm_private *arcpgu = drm->dev_private;
222 struct drm_plane *primary;
223 int ret;
225 primary = arc_pgu_plane_init(drm);
226 if (IS_ERR(primary))
227 return PTR_ERR(primary);
229 ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
230 &arc_pgu_crtc_funcs, NULL);
231 if (ret) {
232 arc_pgu_plane_destroy(primary);
233 return ret;
236 drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
237 return 0;