drivers/gpu/drm/armada/armada_crtc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 Russell King
   4  */
   5 #ifndef ARMADA_CRTC_H
   6 #define ARMADA_CRTC_H
   7
   8 #include <drm/drm_crtc.h>
   9
  10 struct armada_gem_object;
  11
  12 struct armada_regs {
  13         uint32_t offset;
  14         uint32_t mask;
  15         uint32_t val;
  16 };
  17
  18 #define armada_reg_queue_mod(_r, _i, _v, _m, _o)        \
  19         do {                                    \
  20                 struct armada_regs *__reg = _r; \
  21                 __reg[_i].offset = _o;          \
  22                 __reg[_i].mask = ~(_m);         \
  23                 __reg[_i].val = _v;             \
  24                 _i++;                           \
  25         } while (0)
  26
  27 #define armada_reg_queue_set(_r, _i, _v, _o)    \
  28         armada_reg_queue_mod(_r, _i, _v, ~0, _o)
  29
  30 #define armada_reg_queue_end(_r, _i)            \
  31         armada_reg_queue_mod(_r, _i, 0, 0, ~0)
  32
  33 struct armada_crtc;
  34 struct armada_variant;
  35
  36 struct armada_crtc {
  37         struct drm_crtc         crtc;
  38         const struct armada_variant *variant;
  39         void                    *variant_data;
  40         unsigned                num;
  41         void __iomem            *base;
  42         struct clk              *clk;
  43         struct {
  44                 uint32_t        spu_v_h_total;
  45                 uint32_t        spu_v_porch;
  46                 uint32_t        spu_adv_reg;
  47         } v[2];
  48         bool                    interlaced;
  49         bool                    cursor_update;
  50
  51         struct armada_gem_object        *cursor_obj;
  52         int                     cursor_x;
  53         int                     cursor_y;
  54         uint32_t                cursor_hw_pos;
  55         uint32_t                cursor_hw_sz;
  56         uint32_t                cursor_w;
  57         uint32_t                cursor_h;
  58
  59         uint32_t                cfg_dumb_ctrl;
  60         uint32_t                spu_iopad_ctrl;
  61
  62         spinlock_t              irq_lock;
  63         uint32_t                irq_ena;
  64
  65         bool                    update_pending;
  66         struct drm_pending_vblank_event *event;
  67         struct armada_regs      atomic_regs[32];
  68         struct armada_regs      *regs;
  69         unsigned int            regs_idx;
  70 };
  71 #define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)
  72
  73 void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);
  74
  75 struct armada_clocking_params {
  76         unsigned long permillage_min;
  77         unsigned long permillage_max;
  78         u32 settable;
  79         u32 div_max;
  80 };
  81
  82 struct armada_clk_result {
  83         unsigned long desired_clk_hz;
  84         struct clk *clk;
  85         u32 div;
  86 };
  87
  88 int armada_crtc_select_clock(struct armada_crtc *dcrtc,
  89                              struct armada_clk_result *res,
  90                              const struct armada_clocking_params *params,
  91                              struct clk *clks[], size_t num_clks,
  92                              unsigned long desired_khz);
  93
  94 extern struct platform_driver armada_lcd_platform_driver;
  95
  96 #endif