drivers/gpu/drm/bochs/bochs_hw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  */
   4
   5 #include <linux/pci.h>
   6
   7 #include <drm/drm_fourcc.h>
   8
   9 #include "bochs.h"
  10
  11 /* ---------------------------------------------------------------------- */
  12
  13 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
  14 {
  15         if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
  16                 return;
  17
  18         if (bochs->mmio) {
  19                 int offset = ioport - 0x3c0 + 0x400;
  20                 writeb(val, bochs->mmio + offset);
  21         } else {
  22                 outb(val, ioport);
  23         }
  24 }
  25
  26 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
  27 {
  28         u16 ret = 0;
  29
  30         if (bochs->mmio) {
  31                 int offset = 0x500 + (reg << 1);
  32                 ret = readw(bochs->mmio + offset);
  33         } else {
  34                 outw(reg, VBE_DISPI_IOPORT_INDEX);
  35                 ret = inw(VBE_DISPI_IOPORT_DATA);
  36         }
  37         return ret;
  38 }
  39
  40 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
  41 {
  42         if (bochs->mmio) {
  43                 int offset = 0x500 + (reg << 1);
  44                 writew(val, bochs->mmio + offset);
  45         } else {
  46                 outw(reg, VBE_DISPI_IOPORT_INDEX);
  47                 outw(val, VBE_DISPI_IOPORT_DATA);
  48         }
  49 }
  50
  51 static void bochs_hw_set_big_endian(struct bochs_device *bochs)
  52 {
  53         if (bochs->qext_size < 8)
  54                 return;
  55
  56         writel(0xbebebebe, bochs->mmio + 0x604);
  57 }
  58
  59 static void bochs_hw_set_little_endian(struct bochs_device *bochs)
  60 {
  61         if (bochs->qext_size < 8)
  62                 return;
  63
  64         writel(0x1e1e1e1e, bochs->mmio + 0x604);
  65 }
  66
  67 #ifdef __BIG_ENDIAN
  68 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
  69 #else
  70 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
  71 #endif
  72
  73 static int bochs_get_edid_block(void *data, u8 *buf,
  74                                 unsigned int block, size_t len)
  75 {
  76         struct bochs_device *bochs = data;
  77         size_t i, start = block * EDID_LENGTH;
  78
  79         if (start + len > 0x400 /* vga register offset */)
  80                 return -1;
  81
  82         for (i = 0; i < len; i++) {
  83                 buf[i] = readb(bochs->mmio + start + i);
  84         }
  85         return 0;
  86 }
  87
  88 int bochs_hw_load_edid(struct bochs_device *bochs)
  89 {
  90         u8 header[8];
  91
  92         if (!bochs->mmio)
  93                 return -1;
  94
  95         /* check header to detect whenever edid support is enabled in qemu */
  96         bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
  97         if (drm_edid_header_is_valid(header) != 8)
  98                 return -1;
  99
 100         kfree(bochs->edid);
 101         bochs->edid = drm_do_get_edid(&bochs->connector,
 102                                       bochs_get_edid_block, bochs);
 103         if (bochs->edid == NULL)
 104                 return -1;
 105
 106         return 0;
 107 }
 108
 109 int bochs_hw_init(struct drm_device *dev)
 110 {
 111         struct bochs_device *bochs = dev->dev_private;
 112         struct pci_dev *pdev = dev->pdev;
 113         unsigned long addr, size, mem, ioaddr, iosize;
 114         u16 id;
 115
 116         if (pdev->resource[2].flags & IORESOURCE_MEM) {
 117                 /* mmio bar with vga and bochs registers present */
 118                 if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
 119                         DRM_ERROR("Cannot request mmio region\n");
 120                         return -EBUSY;
 121                 }
 122                 ioaddr = pci_resource_start(pdev, 2);
 123                 iosize = pci_resource_len(pdev, 2);
 124                 bochs->mmio = ioremap(ioaddr, iosize);
 125                 if (bochs->mmio == NULL) {
 126                         DRM_ERROR("Cannot map mmio region\n");
 127                         return -ENOMEM;
 128                 }
 129         } else {
 130                 ioaddr = VBE_DISPI_IOPORT_INDEX;
 131                 iosize = 2;
 132                 if (!request_region(ioaddr, iosize, "bochs-drm")) {
 133                         DRM_ERROR("Cannot request ioports\n");
 134                         return -EBUSY;
 135                 }
 136                 bochs->ioports = 1;
 137         }
 138
 139         id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
 140         mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
 141                 * 64 * 1024;
 142         if ((id & 0xfff0) != VBE_DISPI_ID0) {
 143                 DRM_ERROR("ID mismatch\n");
 144                 return -ENODEV;
 145         }
 146
 147         if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
 148                 return -ENODEV;
 149         addr = pci_resource_start(pdev, 0);
 150         size = pci_resource_len(pdev, 0);
 151         if (addr == 0)
 152                 return -ENODEV;
 153         if (size != mem) {
 154                 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
 155                         size, mem);
 156                 size = min(size, mem);
 157         }
 158
 159         if (pci_request_region(pdev, 0, "bochs-drm") != 0) {
 160                 DRM_ERROR("Cannot request framebuffer\n");
 161                 return -EBUSY;
 162         }
 163
 164         bochs->fb_map = ioremap(addr, size);
 165         if (bochs->fb_map == NULL) {
 166                 DRM_ERROR("Cannot map framebuffer\n");
 167                 return -ENOMEM;
 168         }
 169         bochs->fb_base = addr;
 170         bochs->fb_size = size;
 171
 172         DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
 173         DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
 174                  size / 1024, addr,
 175                  bochs->ioports ? "ioports" : "mmio",
 176                  ioaddr);
 177
 178         if (bochs->mmio && pdev->revision >= 2) {
 179                 bochs->qext_size = readl(bochs->mmio + 0x600);
 180                 if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
 181                         bochs->qext_size = 0;
 182                         goto noext;
 183                 }
 184                 DRM_DEBUG("Found qemu ext regs, size %ld\n",
 185                           bochs->qext_size);
 186                 bochs_hw_set_native_endian(bochs);
 187         }
 188
 189 noext:
 190         return 0;
 191 }
 192
 193 void bochs_hw_fini(struct drm_device *dev)
 194 {
 195         struct bochs_device *bochs = dev->dev_private;
 196
 197         if (bochs->mmio)
 198                 iounmap(bochs->mmio);
 199         if (bochs->ioports)
 200                 release_region(VBE_DISPI_IOPORT_INDEX, 2);
 201         if (bochs->fb_map)
 202                 iounmap(bochs->fb_map);
 203         pci_release_regions(dev->pdev);
 204         kfree(bochs->edid);
 205 }
 206
 207 void bochs_hw_setmode(struct bochs_device *bochs,
 208                       struct drm_display_mode *mode)
 209 {
 210         bochs->xres = mode->hdisplay;
 211         bochs->yres = mode->vdisplay;
 212         bochs->bpp = 32;
 213         bochs->stride = mode->hdisplay * (bochs->bpp / 8);
 214         bochs->yres_virtual = bochs->fb_size / bochs->stride;
 215
 216         DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
 217                          bochs->xres, bochs->yres, bochs->bpp,
 218                          bochs->yres_virtual);
 219
 220         bochs_vga_writeb(bochs, 0x3c0, 0x20); /* unblank */
 221
 222         bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,      0);
 223         bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP,         bochs->bpp);
 224         bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES,        bochs->xres);
 225         bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES,        bochs->yres);
 226         bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK,        0);
 227         bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH,  bochs->xres);
 228         bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
 229                           bochs->yres_virtual);
 230         bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET,    0);
 231         bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET,    0);
 232
 233         bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
 234                           VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
 235 }
 236
 237 void bochs_hw_setformat(struct bochs_device *bochs,
 238                         const struct drm_format_info *format)
 239 {
 240         DRM_DEBUG_DRIVER("format %c%c%c%c\n",
 241                          (format->format >>  0) & 0xff,
 242                          (format->format >>  8) & 0xff,
 243                          (format->format >> 16) & 0xff,
 244                          (format->format >> 24) & 0xff);
 245
 246         switch (format->format) {
 247         case DRM_FORMAT_XRGB8888:
 248                 bochs_hw_set_little_endian(bochs);
 249                 break;
 250         case DRM_FORMAT_BGRX8888:
 251                 bochs_hw_set_big_endian(bochs);
 252                 break;
 253         default:
 254                 /* should not happen */
 255                 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
 256                           __func__, format->format);
 257                 break;
 258         }
 259 }
 260
 261 void bochs_hw_setbase(struct bochs_device *bochs,
 262                       int x, int y, int stride, u64 addr)
 263 {
 264         unsigned long offset;
 265         unsigned int vx, vy, vwidth;
 266
 267         bochs->stride = stride;
 268         offset = (unsigned long)addr +
 269                 y * bochs->stride +
 270                 x * (bochs->bpp / 8);
 271         vy = offset / bochs->stride;
 272         vx = (offset % bochs->stride) * 8 / bochs->bpp;
 273         vwidth = stride * 8 / bochs->bpp;
 274
 275         DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
 276                          x, y, addr, offset, vx, vy);
 277         bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
 278         bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
 279         bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
 280 }