drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
   4  */
   5 #ifndef _ANALOGIX_I2C_TXCOMMON_H_
   6 #define _ANALOGIX_I2C_TXCOMMON_H_
   7
   8 /***************************************************************/
   9 /* Register definitions for TX_P2                              */
  10 /***************************************************************/
  11
  12 /*
  13  * Core Register Definitions
  14  */
  15
  16 /* Device ID Low Byte Register */
  17 #define SP_DEVICE_IDL_REG               0x02
  18
  19 /* Device ID High Byte Register */
  20 #define SP_DEVICE_IDH_REG               0x03
  21
  22 /* Device version register */
  23 #define SP_DEVICE_VERSION_REG           0x04
  24
  25 /* Power Down Control Register */
  26 #define SP_POWERDOWN_CTRL_REG           0x05
  27 #define SP_REGISTER_PD                  BIT(7)
  28 #define SP_HDCP_PD                      BIT(5)
  29 #define SP_AUDIO_PD                     BIT(4)
  30 #define SP_VIDEO_PD                     BIT(3)
  31 #define SP_LINK_PD                      BIT(2)
  32 #define SP_TOTAL_PD                     BIT(1)
  33
  34 /* Reset Control Register 1 */
  35 #define SP_RESET_CTRL1_REG              0x06
  36 #define SP_MISC_RST                     BIT(7)
  37 #define SP_VIDCAP_RST                   BIT(6)
  38 #define SP_VIDFIF_RST                   BIT(5)
  39 #define SP_AUDFIF_RST                   BIT(4)
  40 #define SP_AUDCAP_RST                   BIT(3)
  41 #define SP_HDCP_RST                     BIT(2)
  42 #define SP_SW_RST                       BIT(1)
  43 #define SP_HW_RST                       BIT(0)
  44
  45 /* Reset Control Register 2 */
  46 #define SP_RESET_CTRL2_REG              0x07
  47 #define SP_AUX_RST                      BIT(2)
  48 #define SP_SERDES_FIFO_RST              BIT(1)
  49 #define SP_I2C_REG_RST                  BIT(0)
  50
  51 /* Video Control Register 1 */
  52 #define SP_VID_CTRL1_REG                0x08
  53 #define SP_VIDEO_EN                     BIT(7)
  54 #define SP_VIDEO_MUTE                   BIT(2)
  55 #define SP_DE_GEN                       BIT(1)
  56 #define SP_DEMUX                        BIT(0)
  57
  58 /* Video Control Register 2 */
  59 #define SP_VID_CTRL2_REG                0x09
  60 #define SP_IN_COLOR_F_MASK              0x03
  61 #define SP_IN_YC_BIT_SEL                BIT(2)
  62 #define SP_IN_BPC_MASK                  0x70
  63 #define SP_IN_BPC_SHIFT                 4
  64 #  define SP_IN_BPC_12BIT               0x03
  65 #  define SP_IN_BPC_10BIT               0x02
  66 #  define SP_IN_BPC_8BIT                0x01
  67 #  define SP_IN_BPC_6BIT                0x00
  68 #define SP_IN_D_RANGE                   BIT(7)
  69
  70 /* Video Control Register 3 */
  71 #define SP_VID_CTRL3_REG                0x0a
  72 #define SP_HPD_OUT                      BIT(6)
  73
  74 /* Video Control Register 5 */
  75 #define SP_VID_CTRL5_REG                0x0c
  76 #define SP_CSC_STD_SEL                  BIT(7)
  77 #define SP_XVYCC_RNG_LMT                BIT(6)
  78 #define SP_RANGE_Y2R                    BIT(5)
  79 #define SP_CSPACE_Y2R                   BIT(4)
  80 #define SP_RGB_RNG_LMT                  BIT(3)
  81 #define SP_Y_RNG_LMT                    BIT(2)
  82 #define SP_RANGE_R2Y                    BIT(1)
  83 #define SP_CSPACE_R2Y                   BIT(0)
  84
  85 /* Video Control Register 6 */
  86 #define SP_VID_CTRL6_REG                0x0d
  87 #define SP_TEST_PATTERN_EN              BIT(7)
  88 #define SP_VIDEO_PROCESS_EN             BIT(6)
  89 #define SP_VID_US_MODE                  BIT(3)
  90 #define SP_VID_DS_MODE                  BIT(2)
  91 #define SP_UP_SAMPLE                    BIT(1)
  92 #define SP_DOWN_SAMPLE                  BIT(0)
  93
  94 /* Video Control Register 8 */
  95 #define SP_VID_CTRL8_REG                0x0f
  96 #define SP_VID_VRES_TH                  BIT(0)
  97
  98 /* Total Line Status Low Byte Register */
  99 #define SP_TOTAL_LINE_STAL_REG          0x24
 100
 101 /* Total Line Status High Byte Register */
 102 #define SP_TOTAL_LINE_STAH_REG          0x25
 103
 104 /* Active Line Status Low Byte Register */
 105 #define SP_ACT_LINE_STAL_REG            0x26
 106
 107 /* Active Line Status High Byte Register */
 108 #define SP_ACT_LINE_STAH_REG            0x27
 109
 110 /* Vertical Front Porch Status Register */
 111 #define SP_V_F_PORCH_STA_REG            0x28
 112
 113 /* Vertical SYNC Width Status Register */
 114 #define SP_V_SYNC_STA_REG               0x29
 115
 116 /* Vertical Back Porch Status Register */
 117 #define SP_V_B_PORCH_STA_REG            0x2a
 118
 119 /* Total Pixel Status Low Byte Register */
 120 #define SP_TOTAL_PIXEL_STAL_REG         0x2b
 121
 122 /* Total Pixel Status High Byte Register */
 123 #define SP_TOTAL_PIXEL_STAH_REG         0x2c
 124
 125 /* Active Pixel Status Low Byte Register */
 126 #define SP_ACT_PIXEL_STAL_REG           0x2d
 127
 128 /* Active Pixel Status High Byte Register */
 129 #define SP_ACT_PIXEL_STAH_REG           0x2e
 130
 131 /* Horizontal Front Porch Status Low Byte Register */
 132 #define SP_H_F_PORCH_STAL_REG           0x2f
 133
 134 /* Horizontal Front Porch Statys High Byte Register */
 135 #define SP_H_F_PORCH_STAH_REG           0x30
 136
 137 /* Horizontal SYNC Width Status Low Byte Register */
 138 #define SP_H_SYNC_STAL_REG              0x31
 139
 140 /* Horizontal SYNC Width Status High Byte Register */
 141 #define SP_H_SYNC_STAH_REG              0x32
 142
 143 /* Horizontal Back Porch Status Low Byte Register */
 144 #define SP_H_B_PORCH_STAL_REG           0x33
 145
 146 /* Horizontal Back Porch Status High Byte Register */
 147 #define SP_H_B_PORCH_STAH_REG           0x34
 148
 149 /* InfoFrame AVI Packet DB1 Register */
 150 #define SP_INFOFRAME_AVI_DB1_REG        0x70
 151
 152 /* Bit Control Specific Register */
 153 #define SP_BIT_CTRL_SPECIFIC_REG        0x80
 154 #define SP_BIT_CTRL_SELECT_SHIFT        1
 155 #define SP_ENABLE_BIT_CTRL              BIT(0)
 156
 157 /* InfoFrame Audio Packet DB1 Register */
 158 #define SP_INFOFRAME_AUD_DB1_REG        0x83
 159
 160 /* InfoFrame MPEG Packet DB1 Register */
 161 #define SP_INFOFRAME_MPEG_DB1_REG       0xb0
 162
 163 /* Audio Channel Status Registers */
 164 #define SP_AUD_CH_STATUS_BASE           0xd0
 165
 166 /* Audio Channel Num Register 5 */
 167 #define SP_I2S_CHANNEL_NUM_MASK         0xe0
 168 #  define SP_I2S_CH_NUM_1               (0x00 << 5)
 169 #  define SP_I2S_CH_NUM_2               (0x01 << 5)
 170 #  define SP_I2S_CH_NUM_3               (0x02 << 5)
 171 #  define SP_I2S_CH_NUM_4               (0x03 << 5)
 172 #  define SP_I2S_CH_NUM_5               (0x04 << 5)
 173 #  define SP_I2S_CH_NUM_6               (0x05 << 5)
 174 #  define SP_I2S_CH_NUM_7               (0x06 << 5)
 175 #  define SP_I2S_CH_NUM_8               (0x07 << 5)
 176 #define SP_EXT_VUCP                     BIT(2)
 177 #define SP_VBIT                         BIT(1)
 178 #define SP_AUDIO_LAYOUT                 BIT(0)
 179
 180 /* Analog Debug Register 1 */
 181 #define SP_ANALOG_DEBUG1_REG            0xdc
 182
 183 /* Analog Debug Register 2 */
 184 #define SP_ANALOG_DEBUG2_REG            0xdd
 185 #define SP_FORCE_SW_OFF_BYPASS          0x20
 186 #define SP_XTAL_FRQ                     0x1c
 187 #  define SP_XTAL_FRQ_19M2              (0x00 << 2)
 188 #  define SP_XTAL_FRQ_24M               (0x01 << 2)
 189 #  define SP_XTAL_FRQ_25M               (0x02 << 2)
 190 #  define SP_XTAL_FRQ_26M               (0x03 << 2)
 191 #  define SP_XTAL_FRQ_27M               (0x04 << 2)
 192 #  define SP_XTAL_FRQ_38M4              (0x05 << 2)
 193 #  define SP_XTAL_FRQ_52M               (0x06 << 2)
 194 #define SP_POWERON_TIME_1P5MS           0x03
 195
 196 /* Analog Control 0 Register */
 197 #define SP_ANALOG_CTRL0_REG             0xe1
 198
 199 /* Common Interrupt Status Register 1 */
 200 #define SP_COMMON_INT_STATUS_BASE       (0xf1 - 1)
 201 #define SP_PLL_LOCK_CHG                 0x40
 202
 203 /* Common Interrupt Status Register 2 */
 204 #define SP_COMMON_INT_STATUS2           0xf2
 205 #define SP_HDCP_AUTH_CHG                BIT(1)
 206 #define SP_HDCP_AUTH_DONE               BIT(0)
 207
 208 #define SP_HDCP_LINK_CHECK_FAIL         BIT(0)
 209
 210 /* Common Interrupt Status Register 4 */
 211 #define SP_COMMON_INT_STATUS4_REG       0xf4
 212 #define SP_HPD_IRQ                      BIT(6)
 213 #define SP_HPD_ESYNC_ERR                BIT(4)
 214 #define SP_HPD_CHG                      BIT(2)
 215 #define SP_HPD_LOST                     BIT(1)
 216 #define SP_HPD_PLUG                     BIT(0)
 217
 218 /* DP Interrupt Status Register */
 219 #define SP_DP_INT_STATUS1_REG           0xf7
 220 #define SP_TRAINING_FINISH              BIT(5)
 221 #define SP_POLLING_ERR                  BIT(4)
 222
 223 /* Common Interrupt Mask Register */
 224 #define SP_COMMON_INT_MASK_BASE         (0xf8 - 1)
 225
 226 #define SP_COMMON_INT_MASK4_REG         0xfb
 227
 228 /* DP Interrupts Mask Register */
 229 #define SP_DP_INT_MASK1_REG             0xfe
 230
 231 /* Interrupt Control Register */
 232 #define SP_INT_CTRL_REG                 0xff
 233
 234 #endif /* _ANALOGIX_I2C_TXCOMMON_H_ */