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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
blob67fca439bbfb476f442262bd1094e7f59a27aad2
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
21
22 #include <media/cec-notifier.h>
23
24 #include <uapi/linux/media-bus-format.h>
25 #include <uapi/linux/videodev2.h>
26
27 #include <drm/bridge/dw_hdmi.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_of.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/drm_scdc_helper.h>
36
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39 #include "dw-hdmi.h"
40
41 #define DDC_CI_ADDR 0x37
42 #define DDC_SEGMENT_ADDR 0x30
43
44 #define HDMI_EDID_LEN 512
45
46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
47 #define SCDC_MIN_SOURCE_VERSION 0x1
48
49 #define HDMI14_MAX_TMDSCLK 340000000
50
51 enum hdmi_datamap {
52 RGB444_8B = 0x01,
53 RGB444_10B = 0x03,
54 RGB444_12B = 0x05,
55 RGB444_16B = 0x07,
56 YCbCr444_8B = 0x09,
57 YCbCr444_10B = 0x0B,
58 YCbCr444_12B = 0x0D,
59 YCbCr444_16B = 0x0F,
60 YCbCr422_8B = 0x16,
61 YCbCr422_10B = 0x14,
62 YCbCr422_12B = 0x12,
63 };
64
65 static const u16 csc_coeff_default[3][4] = {
66 { 0x2000, 0x0000, 0x0000, 0x0000 },
67 { 0x0000, 0x2000, 0x0000, 0x0000 },
68 { 0x0000, 0x0000, 0x2000, 0x0000 }
69 };
70
71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
72 { 0x2000, 0x6926, 0x74fd, 0x010e },
73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
74 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
75 };
76
77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
78 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
79 { 0x2000, 0x3264, 0x0000, 0x7e6d },
80 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
81 };
82
83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
84 { 0x2591, 0x1322, 0x074b, 0x0000 },
85 { 0x6535, 0x2000, 0x7acc, 0x0200 },
86 { 0x6acd, 0x7534, 0x2000, 0x0200 }
87 };
88
89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
91 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
92 { 0x6756, 0x78ab, 0x2000, 0x0200 }
93 };
94
95 struct hdmi_vmode {
96 bool mdataenablepolarity;
97
98 unsigned int mpixelclock;
99 unsigned int mpixelrepetitioninput;
100 unsigned int mpixelrepetitionoutput;
101 unsigned int mtmdsclock;
102 };
103
104 struct hdmi_data_info {
105 unsigned int enc_in_bus_format;
106 unsigned int enc_out_bus_format;
107 unsigned int enc_in_encoding;
108 unsigned int enc_out_encoding;
109 unsigned int pix_repet_factor;
110 unsigned int hdcp_enable;
111 struct hdmi_vmode video_mode;
112 };
113
114 struct dw_hdmi_i2c {
115 struct i2c_adapter adap;
116
117 struct mutex lock; /* used to serialize data transfers */
118 struct completion cmp;
119 u8 stat;
120
121 u8 slave_reg;
122 bool is_regaddr;
123 bool is_segment;
124 };
125
126 struct dw_hdmi_phy_data {
127 enum dw_hdmi_phy_type type;
128 const char *name;
129 unsigned int gen;
130 bool has_svsret;
131 int (*configure)(struct dw_hdmi *hdmi,
132 const struct dw_hdmi_plat_data *pdata,
133 unsigned long mpixelclock);
134 };
135
136 struct dw_hdmi {
137 struct drm_connector connector;
138 struct drm_bridge bridge;
139
140 unsigned int version;
141
142 struct platform_device *audio;
143 struct platform_device *cec;
144 struct device *dev;
145 struct clk *isfr_clk;
146 struct clk *iahb_clk;
147 struct clk *cec_clk;
148 struct dw_hdmi_i2c *i2c;
149
150 struct hdmi_data_info hdmi_data;
151 const struct dw_hdmi_plat_data *plat_data;
152
153 int vic;
154
155 u8 edid[HDMI_EDID_LEN];
156
157 struct {
158 const struct dw_hdmi_phy_ops *ops;
159 const char *name;
160 void *data;
161 bool enabled;
162 } phy;
163
164 struct drm_display_mode previous_mode;
165
166 struct i2c_adapter *ddc;
167 void __iomem *regs;
168 bool sink_is_hdmi;
169 bool sink_has_audio;
170
171 struct pinctrl *pinctrl;
172 struct pinctrl_state *default_state;
173 struct pinctrl_state *unwedge_state;
174
175 struct mutex mutex; /* for state below and previous_mode */
176 enum drm_connector_force force; /* mutex-protected force state */
177 bool disabled; /* DRM has disabled our bridge */
178 bool bridge_is_on; /* indicates the bridge is on */
179 bool rxsense; /* rxsense state */
180 u8 phy_mask; /* desired phy int mask settings */
181 u8 mc_clkdis; /* clock disable register */
182
183 spinlock_t audio_lock;
184 struct mutex audio_mutex;
185 unsigned int sample_rate;
186 unsigned int audio_cts;
187 unsigned int audio_n;
188 bool audio_enable;
189
190 unsigned int reg_shift;
191 struct regmap *regm;
192 void (*enable_audio)(struct dw_hdmi *hdmi);
193 void (*disable_audio)(struct dw_hdmi *hdmi);
194
195 struct mutex cec_notifier_mutex;
196 struct cec_notifier *cec_notifier;
197
198 hdmi_codec_plugged_cb plugged_cb;
199 struct device *codec_dev;
200 enum drm_connector_status last_connector_result;
201 };
202
203 #define HDMI_IH_PHY_STAT0_RX_SENSE \
204 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
205 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
206
207 #define HDMI_PHY_RX_SENSE \
208 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
209 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
210
211 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
212 {
213 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
214 }
215
216 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
217 {
218 unsigned int val = 0;
219
220 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
221
222 return val;
223 }
224
225 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
226 {
227 if (hdmi->plugged_cb && hdmi->codec_dev)
228 hdmi->plugged_cb(hdmi->codec_dev, plugged);
229 }
230
231 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
232 struct device *codec_dev)
233 {
234 bool plugged;
235
236 mutex_lock(&hdmi->mutex);
237 hdmi->plugged_cb = fn;
238 hdmi->codec_dev = codec_dev;
239 plugged = hdmi->last_connector_result == connector_status_connected;
240 handle_plugged_change(hdmi, plugged);
241 mutex_unlock(&hdmi->mutex);
242
243 return 0;
244 }
245 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
246
247 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
248 {
249 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
250 }
251
252 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
253 u8 shift, u8 mask)
254 {
255 hdmi_modb(hdmi, data << shift, mask, reg);
256 }
257
258 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
259 {
260 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
261 HDMI_PHY_I2CM_INT_ADDR);
262
263 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
264 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
265 HDMI_PHY_I2CM_CTLINT_ADDR);
266
267 /* Software reset */
268 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
269
270 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
271 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
272
273 /* Set done, not acknowledged and arbitration interrupt polarities */
274 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
275 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
276 HDMI_I2CM_CTLINT);
277
278 /* Clear DONE and ERROR interrupts */
279 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
280 HDMI_IH_I2CM_STAT0);
281
282 /* Mute DONE and ERROR interrupts */
283 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
284 HDMI_IH_MUTE_I2CM_STAT0);
285 }
286
287 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
288 {
289 /* If no unwedge state then give up */
290 if (!hdmi->unwedge_state)
291 return false;
292
293 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
294
295 /*
296 * This is a huge hack to workaround a problem where the dw_hdmi i2c
297 * bus could sometimes get wedged. Once wedged there doesn't appear
298 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
299 * other than pulsing the SDA line.
300 *
301 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
302 * by:
303 * 1. Remux the pin as a GPIO output, driven low.
304 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
305 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
306 *
307 * At the moment of remuxing, the line will still be low due to its
308 * recent stint as an output, but then it will be pulled high by the
309 * (presumed) external pullup. dw_hdmi seems to see this as a rising
310 * edge and that seems to get it out of its jam.
311 *
312 * This wedging was only ever seen on one TV, and only on one of
313 * its HDMI ports. It happened when the TV was powered on while the
314 * device was plugged in. A scope trace shows the TV bringing both SDA
315 * and SCL low, then bringing them both back up at roughly the same
316 * time. Presumably this confuses dw_hdmi because it saw activity but
317 * no real STOP (maybe it thinks there's another master on the bus?).
318 * Giving it a clean rising edge of SDA while SCL is already high
319 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
320 * of its stupor.
321 *
322 * Note that after coming back alive, transfers seem to immediately
323 * resume, so if we unwedge due to a timeout we should wait a little
324 * longer for our transfer to finish, since it might have just started
325 * now.
326 */
327 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
328 msleep(10);
329 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
330
331 return true;
332 }
333
334 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
335 {
336 struct dw_hdmi_i2c *i2c = hdmi->i2c;
337 int stat;
338
339 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
340 if (!stat) {
341 /* If we can't unwedge, return timeout */
342 if (!dw_hdmi_i2c_unwedge(hdmi))
343 return -EAGAIN;
344
345 /* We tried to unwedge; give it another chance */
346 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
347 if (!stat)
348 return -EAGAIN;
349 }
350
351 /* Check for error condition on the bus */
352 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
353 return -EIO;
354
355 return 0;
356 }
357
358 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
359 unsigned char *buf, unsigned int length)
360 {
361 struct dw_hdmi_i2c *i2c = hdmi->i2c;
362 int ret;
363
364 if (!i2c->is_regaddr) {
365 dev_dbg(hdmi->dev, "set read register address to 0\n");
366 i2c->slave_reg = 0x00;
367 i2c->is_regaddr = true;
368 }
369
370 while (length--) {
371 reinit_completion(&i2c->cmp);
372
373 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
374 if (i2c->is_segment)
375 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
376 HDMI_I2CM_OPERATION);
377 else
378 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
379 HDMI_I2CM_OPERATION);
380
381 ret = dw_hdmi_i2c_wait(hdmi);
382 if (ret)
383 return ret;
384
385 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
386 }
387 i2c->is_segment = false;
388
389 return 0;
390 }
391
392 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
393 unsigned char *buf, unsigned int length)
394 {
395 struct dw_hdmi_i2c *i2c = hdmi->i2c;
396 int ret;
397
398 if (!i2c->is_regaddr) {
399 /* Use the first write byte as register address */
400 i2c->slave_reg = buf[0];
401 length--;
402 buf++;
403 i2c->is_regaddr = true;
404 }
405
406 while (length--) {
407 reinit_completion(&i2c->cmp);
408
409 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
410 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
411 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
412 HDMI_I2CM_OPERATION);
413
414 ret = dw_hdmi_i2c_wait(hdmi);
415 if (ret)
416 return ret;
417 }
418
419 return 0;
420 }
421
422 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
423 struct i2c_msg *msgs, int num)
424 {
425 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
426 struct dw_hdmi_i2c *i2c = hdmi->i2c;
427 u8 addr = msgs[0].addr;
428 int i, ret = 0;
429
430 if (addr == DDC_CI_ADDR)
431 /*
432 * The internal I2C controller does not support the multi-byte
433 * read and write operations needed for DDC/CI.
434 * TOFIX: Blacklist the DDC/CI address until we filter out
435 * unsupported I2C operations.
436 */
437 return -EOPNOTSUPP;
438
439 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
440
441 for (i = 0; i < num; i++) {
442 if (msgs[i].len == 0) {
443 dev_dbg(hdmi->dev,
444 "unsupported transfer %d/%d, no data\n",
445 i + 1, num);
446 return -EOPNOTSUPP;
447 }
448 }
449
450 mutex_lock(&i2c->lock);
451
452 /* Unmute DONE and ERROR interrupts */
453 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
454
455 /* Set slave device address taken from the first I2C message */
456 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
457
458 /* Set slave device register address on transfer */
459 i2c->is_regaddr = false;
460
461 /* Set segment pointer for I2C extended read mode operation */
462 i2c->is_segment = false;
463
464 for (i = 0; i < num; i++) {
465 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
466 i + 1, num, msgs[i].len, msgs[i].flags);
467 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
468 i2c->is_segment = true;
469 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
470 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
471 } else {
472 if (msgs[i].flags & I2C_M_RD)
473 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
474 msgs[i].len);
475 else
476 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
477 msgs[i].len);
478 }
479 if (ret < 0)
480 break;
481 }
482
483 if (!ret)
484 ret = num;
485
486 /* Mute DONE and ERROR interrupts */
487 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
488 HDMI_IH_MUTE_I2CM_STAT0);
489
490 mutex_unlock(&i2c->lock);
491
492 return ret;
493 }
494
495 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
496 {
497 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
498 }
499
500 static const struct i2c_algorithm dw_hdmi_algorithm = {
501 .master_xfer = dw_hdmi_i2c_xfer,
502 .functionality = dw_hdmi_i2c_func,
503 };
504
505 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
506 {
507 struct i2c_adapter *adap;
508 struct dw_hdmi_i2c *i2c;
509 int ret;
510
511 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
512 if (!i2c)
513 return ERR_PTR(-ENOMEM);
514
515 mutex_init(&i2c->lock);
516 init_completion(&i2c->cmp);
517
518 adap = &i2c->adap;
519 adap->class = I2C_CLASS_DDC;
520 adap->owner = THIS_MODULE;
521 adap->dev.parent = hdmi->dev;
522 adap->algo = &dw_hdmi_algorithm;
523 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
524 i2c_set_adapdata(adap, hdmi);
525
526 ret = i2c_add_adapter(adap);
527 if (ret) {
528 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
529 devm_kfree(hdmi->dev, i2c);
530 return ERR_PTR(ret);
531 }
532
533 hdmi->i2c = i2c;
534
535 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
536
537 return adap;
538 }
539
540 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
541 unsigned int n)
542 {
543 /* Must be set/cleared first */
544 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
545
546 /* nshift factor = 0 */
547 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
548
549 /* Use automatic CTS generation mode when CTS is not set */
550 if (cts)
551 hdmi_writeb(hdmi, ((cts >> 16) &
552 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
553 HDMI_AUD_CTS3_CTS_MANUAL,
554 HDMI_AUD_CTS3);
555 else
556 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
557 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
558 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
559
560 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
561 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
562 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
563 }
564
565 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
566 {
567 unsigned int n = (128 * freq) / 1000;
568 unsigned int mult = 1;
569
570 while (freq > 48000) {
571 mult *= 2;
572 freq /= 2;
573 }
574
575 switch (freq) {
576 case 32000:
577 if (pixel_clk == 25175000)
578 n = 4576;
579 else if (pixel_clk == 27027000)
580 n = 4096;
581 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
582 n = 11648;
583 else
584 n = 4096;
585 n *= mult;
586 break;
587
588 case 44100:
589 if (pixel_clk == 25175000)
590 n = 7007;
591 else if (pixel_clk == 74176000)
592 n = 17836;
593 else if (pixel_clk == 148352000)
594 n = 8918;
595 else
596 n = 6272;
597 n *= mult;
598 break;
599
600 case 48000:
601 if (pixel_clk == 25175000)
602 n = 6864;
603 else if (pixel_clk == 27027000)
604 n = 6144;
605 else if (pixel_clk == 74176000)
606 n = 11648;
607 else if (pixel_clk == 148352000)
608 n = 5824;
609 else
610 n = 6144;
611 n *= mult;
612 break;
613
614 default:
615 break;
616 }
617
618 return n;
619 }
620
621 /*
622 * When transmitting IEC60958 linear PCM audio, these registers allow to
623 * configure the channel status information of all the channel status
624 * bits in the IEC60958 frame. For the moment this configuration is only
625 * used when the I2S audio interface, General Purpose Audio (GPA),
626 * or AHB audio DMA (AHBAUDDMA) interface is active
627 * (for S/PDIF interface this information comes from the stream).
628 */
629 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
630 u8 *channel_status)
631 {
632 /*
633 * Set channel status register for frequency and word length.
634 * Use default values for other registers.
635 */
636 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
637 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
638 }
639 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
640
641 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
642 unsigned long pixel_clk, unsigned int sample_rate)
643 {
644 unsigned long ftdms = pixel_clk;
645 unsigned int n, cts;
646 u8 config3;
647 u64 tmp;
648
649 n = hdmi_compute_n(sample_rate, pixel_clk);
650
651 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
652
653 /* Only compute CTS when using internal AHB audio */
654 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
655 /*
656 * Compute the CTS value from the N value. Note that CTS and N
657 * can be up to 20 bits in total, so we need 64-bit math. Also
658 * note that our TDMS clock is not fully accurate; it is
659 * accurate to kHz. This can introduce an unnecessary remainder
660 * in the calculation below, so we don't try to warn about that.
661 */
662 tmp = (u64)ftdms * n;
663 do_div(tmp, 128 * sample_rate);
664 cts = tmp;
665
666 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
667 __func__, sample_rate,
668 ftdms / 1000000, (ftdms / 1000) % 1000,
669 n, cts);
670 } else {
671 cts = 0;
672 }
673
674 spin_lock_irq(&hdmi->audio_lock);
675 hdmi->audio_n = n;
676 hdmi->audio_cts = cts;
677 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
678 spin_unlock_irq(&hdmi->audio_lock);
679 }
680
681 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
682 {
683 mutex_lock(&hdmi->audio_mutex);
684 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
685 mutex_unlock(&hdmi->audio_mutex);
686 }
687
688 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
689 {
690 mutex_lock(&hdmi->audio_mutex);
691 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
692 hdmi->sample_rate);
693 mutex_unlock(&hdmi->audio_mutex);
694 }
695
696 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
697 {
698 mutex_lock(&hdmi->audio_mutex);
699 hdmi->sample_rate = rate;
700 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
701 hdmi->sample_rate);
702 mutex_unlock(&hdmi->audio_mutex);
703 }
704 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
705
706 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
707 {
708 u8 layout;
709
710 mutex_lock(&hdmi->audio_mutex);
711
712 /*
713 * For >2 channel PCM audio, we need to select layout 1
714 * and set an appropriate channel map.
715 */
716 if (cnt > 2)
717 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
718 else
719 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
720
721 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
722 HDMI_FC_AUDSCONF);
723
724 /* Set the audio infoframes channel count */
725 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
726 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
727
728 mutex_unlock(&hdmi->audio_mutex);
729 }
730 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
731
732 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
733 {
734 mutex_lock(&hdmi->audio_mutex);
735
736 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
737
738 mutex_unlock(&hdmi->audio_mutex);
739 }
740 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
741
742 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
743 {
744 if (enable)
745 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
746 else
747 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
748 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
749 }
750
751 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
752 {
753 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
754 }
755
756 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
757 {
758 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
759 }
760
761 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
762 {
763 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
764 hdmi_enable_audio_clk(hdmi, true);
765 }
766
767 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
768 {
769 hdmi_enable_audio_clk(hdmi, false);
770 }
771
772 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
773 {
774 unsigned long flags;
775
776 spin_lock_irqsave(&hdmi->audio_lock, flags);
777 hdmi->audio_enable = true;
778 if (hdmi->enable_audio)
779 hdmi->enable_audio(hdmi);
780 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
781 }
782 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
783
784 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
785 {
786 unsigned long flags;
787
788 spin_lock_irqsave(&hdmi->audio_lock, flags);
789 hdmi->audio_enable = false;
790 if (hdmi->disable_audio)
791 hdmi->disable_audio(hdmi);
792 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
793 }
794 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
795
796 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
797 {
798 switch (bus_format) {
799 case MEDIA_BUS_FMT_RGB888_1X24:
800 case MEDIA_BUS_FMT_RGB101010_1X30:
801 case MEDIA_BUS_FMT_RGB121212_1X36:
802 case MEDIA_BUS_FMT_RGB161616_1X48:
803 return true;
804
805 default:
806 return false;
807 }
808 }
809
810 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
811 {
812 switch (bus_format) {
813 case MEDIA_BUS_FMT_YUV8_1X24:
814 case MEDIA_BUS_FMT_YUV10_1X30:
815 case MEDIA_BUS_FMT_YUV12_1X36:
816 case MEDIA_BUS_FMT_YUV16_1X48:
817 return true;
818
819 default:
820 return false;
821 }
822 }
823
824 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
825 {
826 switch (bus_format) {
827 case MEDIA_BUS_FMT_UYVY8_1X16:
828 case MEDIA_BUS_FMT_UYVY10_1X20:
829 case MEDIA_BUS_FMT_UYVY12_1X24:
830 return true;
831
832 default:
833 return false;
834 }
835 }
836
837 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
838 {
839 switch (bus_format) {
840 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
841 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
842 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
843 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
844 return true;
845
846 default:
847 return false;
848 }
849 }
850
851 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
852 {
853 switch (bus_format) {
854 case MEDIA_BUS_FMT_RGB888_1X24:
855 case MEDIA_BUS_FMT_YUV8_1X24:
856 case MEDIA_BUS_FMT_UYVY8_1X16:
857 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
858 return 8;
859
860 case MEDIA_BUS_FMT_RGB101010_1X30:
861 case MEDIA_BUS_FMT_YUV10_1X30:
862 case MEDIA_BUS_FMT_UYVY10_1X20:
863 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
864 return 10;
865
866 case MEDIA_BUS_FMT_RGB121212_1X36:
867 case MEDIA_BUS_FMT_YUV12_1X36:
868 case MEDIA_BUS_FMT_UYVY12_1X24:
869 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
870 return 12;
871
872 case MEDIA_BUS_FMT_RGB161616_1X48:
873 case MEDIA_BUS_FMT_YUV16_1X48:
874 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
875 return 16;
876
877 default:
878 return 0;
879 }
880 }
881
882 /*
883 * this submodule is responsible for the video data synchronization.
884 * for example, for RGB 4:4:4 input, the data map is defined as
885 * pin{47~40} <==> R[7:0]
886 * pin{31~24} <==> G[7:0]
887 * pin{15~8} <==> B[7:0]
888 */
889 static void hdmi_video_sample(struct dw_hdmi *hdmi)
890 {
891 int color_format = 0;
892 u8 val;
893
894 switch (hdmi->hdmi_data.enc_in_bus_format) {
895 case MEDIA_BUS_FMT_RGB888_1X24:
896 color_format = 0x01;
897 break;
898 case MEDIA_BUS_FMT_RGB101010_1X30:
899 color_format = 0x03;
900 break;
901 case MEDIA_BUS_FMT_RGB121212_1X36:
902 color_format = 0x05;
903 break;
904 case MEDIA_BUS_FMT_RGB161616_1X48:
905 color_format = 0x07;
906 break;
907
908 case MEDIA_BUS_FMT_YUV8_1X24:
909 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
910 color_format = 0x09;
911 break;
912 case MEDIA_BUS_FMT_YUV10_1X30:
913 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
914 color_format = 0x0B;
915 break;
916 case MEDIA_BUS_FMT_YUV12_1X36:
917 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
918 color_format = 0x0D;
919 break;
920 case MEDIA_BUS_FMT_YUV16_1X48:
921 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
922 color_format = 0x0F;
923 break;
924
925 case MEDIA_BUS_FMT_UYVY8_1X16:
926 color_format = 0x16;
927 break;
928 case MEDIA_BUS_FMT_UYVY10_1X20:
929 color_format = 0x14;
930 break;
931 case MEDIA_BUS_FMT_UYVY12_1X24:
932 color_format = 0x12;
933 break;
934
935 default:
936 return;
937 }
938
939 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
940 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
941 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
942 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
943
944 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
945 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
946 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
947 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
948 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
949 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
950 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
951 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
952 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
953 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
954 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
955 }
956
957 static int is_color_space_conversion(struct dw_hdmi *hdmi)
958 {
959 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
960 }
961
962 static int is_color_space_decimation(struct dw_hdmi *hdmi)
963 {
964 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
965 return 0;
966
967 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
968 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
969 return 1;
970
971 return 0;
972 }
973
974 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
975 {
976 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
977 return 0;
978
979 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
980 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
981 return 1;
982
983 return 0;
984 }
985
986 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
987 {
988 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
989 unsigned i;
990 u32 csc_scale = 1;
991
992 if (is_color_space_conversion(hdmi)) {
993 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
994 if (hdmi->hdmi_data.enc_out_encoding ==
995 V4L2_YCBCR_ENC_601)
996 csc_coeff = &csc_coeff_rgb_out_eitu601;
997 else
998 csc_coeff = &csc_coeff_rgb_out_eitu709;
999 } else if (hdmi_bus_fmt_is_rgb(
1000 hdmi->hdmi_data.enc_in_bus_format)) {
1001 if (hdmi->hdmi_data.enc_out_encoding ==
1002 V4L2_YCBCR_ENC_601)
1003 csc_coeff = &csc_coeff_rgb_in_eitu601;
1004 else
1005 csc_coeff = &csc_coeff_rgb_in_eitu709;
1006 csc_scale = 0;
1007 }
1008 }
1009
1010 /* The CSC registers are sequential, alternating MSB then LSB */
1011 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1012 u16 coeff_a = (*csc_coeff)[0][i];
1013 u16 coeff_b = (*csc_coeff)[1][i];
1014 u16 coeff_c = (*csc_coeff)[2][i];
1015
1016 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1017 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1018 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1019 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1020 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1021 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1022 }
1023
1024 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1025 HDMI_CSC_SCALE);
1026 }
1027
1028 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1029 {
1030 int color_depth = 0;
1031 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1032 int decimation = 0;
1033
1034 /* YCC422 interpolation to 444 mode */
1035 if (is_color_space_interpolation(hdmi))
1036 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1037 else if (is_color_space_decimation(hdmi))
1038 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1039
1040 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1041 case 8:
1042 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1043 break;
1044 case 10:
1045 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1046 break;
1047 case 12:
1048 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1049 break;
1050 case 16:
1051 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1052 break;
1053
1054 default:
1055 return;
1056 }
1057
1058 /* Configure the CSC registers */
1059 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1060 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1061 HDMI_CSC_SCALE);
1062
1063 dw_hdmi_update_csc_coeffs(hdmi);
1064 }
1065
1066 /*
1067 * HDMI video packetizer is used to packetize the data.
1068 * for example, if input is YCC422 mode or repeater is used,
1069 * data should be repacked this module can be bypassed.
1070 */
1071 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1072 {
1073 unsigned int color_depth = 0;
1074 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1075 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1076 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1077 u8 val, vp_conf;
1078
1079 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1080 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1081 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1082 switch (hdmi_bus_fmt_color_depth(
1083 hdmi->hdmi_data.enc_out_bus_format)) {
1084 case 8:
1085 color_depth = 4;
1086 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1087 break;
1088 case 10:
1089 color_depth = 5;
1090 break;
1091 case 12:
1092 color_depth = 6;
1093 break;
1094 case 16:
1095 color_depth = 7;
1096 break;
1097 default:
1098 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1099 }
1100 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1101 switch (hdmi_bus_fmt_color_depth(
1102 hdmi->hdmi_data.enc_out_bus_format)) {
1103 case 0:
1104 case 8:
1105 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1106 break;
1107 case 10:
1108 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1109 break;
1110 case 12:
1111 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1112 break;
1113
1114 default:
1115 return;
1116 }
1117 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1118 } else {
1119 return;
1120 }
1121
1122 /* set the packetizer registers */
1123 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1124 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1125 ((hdmi_data->pix_repet_factor <<
1126 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1127 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1128 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1129
1130 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1131 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1132
1133 /* Data from pixel repeater block */
1134 if (hdmi_data->pix_repet_factor > 1) {
1135 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1136 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1137 } else { /* data from packetizer block */
1138 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1139 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1140 }
1141
1142 hdmi_modb(hdmi, vp_conf,
1143 HDMI_VP_CONF_PR_EN_MASK |
1144 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1145
1146 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1147 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1148
1149 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1150
1151 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1152 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1153 HDMI_VP_CONF_PP_EN_ENABLE |
1154 HDMI_VP_CONF_YCC422_EN_DISABLE;
1155 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1156 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1157 HDMI_VP_CONF_PP_EN_DISABLE |
1158 HDMI_VP_CONF_YCC422_EN_ENABLE;
1159 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1160 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1161 HDMI_VP_CONF_PP_EN_DISABLE |
1162 HDMI_VP_CONF_YCC422_EN_DISABLE;
1163 } else {
1164 return;
1165 }
1166
1167 hdmi_modb(hdmi, vp_conf,
1168 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1169 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1170
1171 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1172 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1173 HDMI_VP_STUFF_PP_STUFFING_MASK |
1174 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1175
1176 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1177 HDMI_VP_CONF);
1178 }
1179
1180 /* -----------------------------------------------------------------------------
1181 * Synopsys PHY Handling
1182 */
1183
1184 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1185 unsigned char bit)
1186 {
1187 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1188 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1189 }
1190
1191 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1192 {
1193 u32 val;
1194
1195 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1196 if (msec-- == 0)
1197 return false;
1198 udelay(1000);
1199 }
1200 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1201
1202 return true;
1203 }
1204
1205 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1206 unsigned char addr)
1207 {
1208 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1209 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1210 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1211 HDMI_PHY_I2CM_DATAO_1_ADDR);
1212 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1213 HDMI_PHY_I2CM_DATAO_0_ADDR);
1214 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1215 HDMI_PHY_I2CM_OPERATION_ADDR);
1216 hdmi_phy_wait_i2c_done(hdmi, 1000);
1217 }
1218 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1219
1220 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1221 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1222 {
1223 struct drm_display_info *display = &hdmi->connector.display_info;
1224
1225 /* Completely disable SCDC support for older controllers */
1226 if (hdmi->version < 0x200a)
1227 return false;
1228
1229 /* Disable if no DDC bus */
1230 if (!hdmi->ddc)
1231 return false;
1232
1233 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1234 if (!display->hdmi.scdc.supported ||
1235 !display->hdmi.scdc.scrambling.supported)
1236 return false;
1237
1238 /*
1239 * Disable if display only support low TMDS rates and scrambling
1240 * for low rates is not supported either
1241 */
1242 if (!display->hdmi.scdc.scrambling.low_rates &&
1243 display->max_tmds_clock <= 340000)
1244 return false;
1245
1246 return true;
1247 }
1248
1249 /*
1250 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1251 * - The Source shall suspend transmission of the TMDS clock and data
1252 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1253 * from a 0 to a 1 or from a 1 to a 0
1254 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1255 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1256 * transmission of TMDS clock and data
1257 *
1258 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1259 * helper should called right before enabling the TMDS Clock and Data in
1260 * the PHY configuration callback.
1261 */
1262 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1263 {
1264 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1265
1266 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1267 if (dw_hdmi_support_scdc(hdmi)) {
1268 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1269 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1270 else
1271 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1272 }
1273 }
1274 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1275
1276 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1277 {
1278 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1279 HDMI_PHY_CONF0_PDZ_OFFSET,
1280 HDMI_PHY_CONF0_PDZ_MASK);
1281 }
1282
1283 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1284 {
1285 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1286 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1287 HDMI_PHY_CONF0_ENTMDS_MASK);
1288 }
1289
1290 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1291 {
1292 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1293 HDMI_PHY_CONF0_SVSRET_OFFSET,
1294 HDMI_PHY_CONF0_SVSRET_MASK);
1295 }
1296
1297 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1298 {
1299 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1300 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1301 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1302 }
1303 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1304
1305 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1306 {
1307 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1308 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1309 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1310 }
1311 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1312
1313 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1314 {
1315 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1316 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1317 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1318 }
1319
1320 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1321 {
1322 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1323 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1324 HDMI_PHY_CONF0_SELDIPIF_MASK);
1325 }
1326
1327 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1328 {
1329 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1330 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1331 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1332 }
1333 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1334
1335 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1336 {
1337 hdmi_phy_test_clear(hdmi, 1);
1338 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1339 hdmi_phy_test_clear(hdmi, 0);
1340 }
1341 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1342
1343 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1344 {
1345 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1346 unsigned int i;
1347 u16 val;
1348
1349 if (phy->gen == 1) {
1350 dw_hdmi_phy_enable_tmds(hdmi, 0);
1351 dw_hdmi_phy_enable_powerdown(hdmi, true);
1352 return;
1353 }
1354
1355 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1356
1357 /*
1358 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1359 * to low power mode.
1360 */
1361 for (i = 0; i < 5; ++i) {
1362 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1363 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1364 break;
1365
1366 usleep_range(1000, 2000);
1367 }
1368
1369 if (val & HDMI_PHY_TX_PHY_LOCK)
1370 dev_warn(hdmi->dev, "PHY failed to power down\n");
1371 else
1372 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1373
1374 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1375 }
1376
1377 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1378 {
1379 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1380 unsigned int i;
1381 u8 val;
1382
1383 if (phy->gen == 1) {
1384 dw_hdmi_phy_enable_powerdown(hdmi, false);
1385
1386 /* Toggle TMDS enable. */
1387 dw_hdmi_phy_enable_tmds(hdmi, 0);
1388 dw_hdmi_phy_enable_tmds(hdmi, 1);
1389 return 0;
1390 }
1391
1392 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1393 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1394
1395 /* Wait for PHY PLL lock */
1396 for (i = 0; i < 5; ++i) {
1397 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1398 if (val)
1399 break;
1400
1401 usleep_range(1000, 2000);
1402 }
1403
1404 if (!val) {
1405 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1406 return -ETIMEDOUT;
1407 }
1408
1409 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1410 return 0;
1411 }
1412
1413 /*
1414 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1415 * information the DWC MHL PHY has the same register layout and is thus also
1416 * supported by this function.
1417 */
1418 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1419 const struct dw_hdmi_plat_data *pdata,
1420 unsigned long mpixelclock)
1421 {
1422 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1423 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1424 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1425
1426 /* TOFIX Will need 420 specific PHY configuration tables */
1427
1428 /* PLL/MPLL Cfg - always match on final entry */
1429 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1430 if (mpixelclock <= mpll_config->mpixelclock)
1431 break;
1432
1433 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1434 if (mpixelclock <= curr_ctrl->mpixelclock)
1435 break;
1436
1437 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1438 if (mpixelclock <= phy_config->mpixelclock)
1439 break;
1440
1441 if (mpll_config->mpixelclock == ~0UL ||
1442 curr_ctrl->mpixelclock == ~0UL ||
1443 phy_config->mpixelclock == ~0UL)
1444 return -EINVAL;
1445
1446 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1447 HDMI_3D_TX_PHY_CPCE_CTRL);
1448 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1449 HDMI_3D_TX_PHY_GMPCTRL);
1450 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1451 HDMI_3D_TX_PHY_CURRCTRL);
1452
1453 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1454 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1455 HDMI_3D_TX_PHY_MSM_CTRL);
1456
1457 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1458 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1459 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1460 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1461 HDMI_3D_TX_PHY_VLEVCTRL);
1462
1463 /* Override and disable clock termination. */
1464 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1465 HDMI_3D_TX_PHY_CKCALCTRL);
1466
1467 return 0;
1468 }
1469
1470 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1471 {
1472 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1473 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1474 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1475 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1476 int ret;
1477
1478 dw_hdmi_phy_power_off(hdmi);
1479
1480 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1481
1482 /* Leave low power consumption mode by asserting SVSRET. */
1483 if (phy->has_svsret)
1484 dw_hdmi_phy_enable_svsret(hdmi, 1);
1485
1486 dw_hdmi_phy_reset(hdmi);
1487
1488 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1489
1490 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1491
1492 /* Write to the PHY as configured by the platform */
1493 if (pdata->configure_phy)
1494 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1495 else
1496 ret = phy->configure(hdmi, pdata, mpixelclock);
1497 if (ret) {
1498 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1499 mpixelclock);
1500 return ret;
1501 }
1502
1503 /* Wait for resuming transmission of TMDS clock and data */
1504 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1505 msleep(100);
1506
1507 return dw_hdmi_phy_power_on(hdmi);
1508 }
1509
1510 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1511 struct drm_display_mode *mode)
1512 {
1513 int i, ret;
1514
1515 /* HDMI Phy spec says to do the phy initialization sequence twice */
1516 for (i = 0; i < 2; i++) {
1517 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1518 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1519
1520 ret = hdmi_phy_configure(hdmi);
1521 if (ret)
1522 return ret;
1523 }
1524
1525 return 0;
1526 }
1527
1528 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1529 {
1530 dw_hdmi_phy_power_off(hdmi);
1531 }
1532
1533 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1534 void *data)
1535 {
1536 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1537 connector_status_connected : connector_status_disconnected;
1538 }
1539 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1540
1541 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1542 bool force, bool disabled, bool rxsense)
1543 {
1544 u8 old_mask = hdmi->phy_mask;
1545
1546 if (force || disabled || !rxsense)
1547 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1548 else
1549 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1550
1551 if (old_mask != hdmi->phy_mask)
1552 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1553 }
1554 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1555
1556 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1557 {
1558 /*
1559 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1560 * any pending interrupt.
1561 */
1562 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1563 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1564 HDMI_IH_PHY_STAT0);
1565
1566 /* Enable cable hot plug irq. */
1567 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1568
1569 /* Clear and unmute interrupts. */
1570 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1571 HDMI_IH_PHY_STAT0);
1572 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1573 HDMI_IH_MUTE_PHY_STAT0);
1574 }
1575 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1576
1577 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1578 .init = dw_hdmi_phy_init,
1579 .disable = dw_hdmi_phy_disable,
1580 .read_hpd = dw_hdmi_phy_read_hpd,
1581 .update_hpd = dw_hdmi_phy_update_hpd,
1582 .setup_hpd = dw_hdmi_phy_setup_hpd,
1583 };
1584
1585 /* -----------------------------------------------------------------------------
1586 * HDMI TX Setup
1587 */
1588
1589 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1590 {
1591 u8 de;
1592
1593 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1594 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1595 else
1596 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1597
1598 /* disable rx detect */
1599 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1600 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1601
1602 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1603
1604 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1605 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1606 }
1607
1608 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1609 {
1610 struct hdmi_avi_infoframe frame;
1611 u8 val;
1612
1613 /* Initialise info frame from DRM mode */
1614 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1615 &hdmi->connector, mode);
1616
1617 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1618 frame.colorspace = HDMI_COLORSPACE_YUV444;
1619 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1620 frame.colorspace = HDMI_COLORSPACE_YUV422;
1621 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1622 frame.colorspace = HDMI_COLORSPACE_YUV420;
1623 else
1624 frame.colorspace = HDMI_COLORSPACE_RGB;
1625
1626 /* Set up colorimetry */
1627 switch (hdmi->hdmi_data.enc_out_encoding) {
1628 case V4L2_YCBCR_ENC_601:
1629 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1630 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1631 else
1632 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1633 frame.extended_colorimetry =
1634 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1635 break;
1636 case V4L2_YCBCR_ENC_709:
1637 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1638 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1639 else
1640 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1641 frame.extended_colorimetry =
1642 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1643 break;
1644 default: /* Carries no data */
1645 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1646 frame.extended_colorimetry =
1647 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1648 break;
1649 }
1650
1651 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1652
1653 /*
1654 * The Designware IP uses a different byte format from standard
1655 * AVI info frames, though generally the bits are in the correct
1656 * bytes.
1657 */
1658
1659 /*
1660 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1661 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1662 * bit 6 rather than 4.
1663 */
1664 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1665 if (frame.active_aspect & 15)
1666 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1667 if (frame.top_bar || frame.bottom_bar)
1668 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1669 if (frame.left_bar || frame.right_bar)
1670 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1671 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1672
1673 /* AVI data byte 2 differences: none */
1674 val = ((frame.colorimetry & 0x3) << 6) |
1675 ((frame.picture_aspect & 0x3) << 4) |
1676 (frame.active_aspect & 0xf);
1677 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1678
1679 /* AVI data byte 3 differences: none */
1680 val = ((frame.extended_colorimetry & 0x7) << 4) |
1681 ((frame.quantization_range & 0x3) << 2) |
1682 (frame.nups & 0x3);
1683 if (frame.itc)
1684 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1685 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1686
1687 /* AVI data byte 4 differences: none */
1688 val = frame.video_code & 0x7f;
1689 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1690
1691 /* AVI Data Byte 5- set up input and output pixel repetition */
1692 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1693 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1694 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1695 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1696 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1697 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1698 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1699
1700 /*
1701 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1702 * ycc range in bits 2,3 rather than 6,7
1703 */
1704 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1705 (frame.content_type & 0x3);
1706 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1707
1708 /* AVI Data Bytes 6-13 */
1709 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1710 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1711 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1712 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1713 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1714 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1715 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1716 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1717 }
1718
1719 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1720 struct drm_display_mode *mode)
1721 {
1722 struct hdmi_vendor_infoframe frame;
1723 u8 buffer[10];
1724 ssize_t err;
1725
1726 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1727 &hdmi->connector,
1728 mode);
1729 if (err < 0)
1730 /*
1731 * Going into that statement does not means vendor infoframe
1732 * fails. It just informed us that vendor infoframe is not
1733 * needed for the selected mode. Only 4k or stereoscopic 3D
1734 * mode requires vendor infoframe. So just simply return.
1735 */
1736 return;
1737
1738 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1739 if (err < 0) {
1740 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1741 err);
1742 return;
1743 }
1744 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1745 HDMI_FC_DATAUTO0_VSD_MASK);
1746
1747 /* Set the length of HDMI vendor specific InfoFrame payload */
1748 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1749
1750 /* Set 24bit IEEE Registration Identifier */
1751 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1752 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1753 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1754
1755 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1756 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1757 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1758
1759 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1760 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1761
1762 /* Packet frame interpolation */
1763 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1764
1765 /* Auto packets per frame and line spacing */
1766 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1767
1768 /* Configures the Frame Composer On RDRB mode */
1769 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1770 HDMI_FC_DATAUTO0_VSD_MASK);
1771 }
1772
1773 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi)
1774 {
1775 const struct drm_connector_state *conn_state = hdmi->connector.state;
1776 struct hdmi_drm_infoframe frame;
1777 u8 buffer[30];
1778 ssize_t err;
1779 int i;
1780
1781 if (!hdmi->plat_data->use_drm_infoframe)
1782 return;
1783
1784 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1785 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1786
1787 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1788 if (err < 0)
1789 return;
1790
1791 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1792 if (err < 0) {
1793 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1794 return;
1795 }
1796
1797 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1798 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1799
1800 for (i = 0; i < frame.length; i++)
1801 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1802
1803 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1804 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1805 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1806 }
1807
1808 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1809 const struct drm_display_mode *mode)
1810 {
1811 u8 inv_val, bytes;
1812 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
1813 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1814 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1815 unsigned int vdisplay, hdisplay;
1816
1817 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
1818
1819 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1820
1821 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1822 vmode->mtmdsclock /= 2;
1823
1824 /* Set up HDMI_FC_INVIDCONF */
1825 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1826 (dw_hdmi_support_scdc(hdmi) &&
1827 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1828 hdmi_info->scdc.scrambling.low_rates)) ?
1829 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1830 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1831
1832 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1833 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1834 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1835
1836 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1837 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1838 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1839
1840 inv_val |= (vmode->mdataenablepolarity ?
1841 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1842 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1843
1844 if (hdmi->vic == 39)
1845 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1846 else
1847 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1848 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1849 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1850
1851 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1852 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1853 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1854
1855 inv_val |= hdmi->sink_is_hdmi ?
1856 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1857 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1858
1859 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1860
1861 hdisplay = mode->hdisplay;
1862 hblank = mode->htotal - mode->hdisplay;
1863 h_de_hs = mode->hsync_start - mode->hdisplay;
1864 hsync_len = mode->hsync_end - mode->hsync_start;
1865
1866 /*
1867 * When we're setting a YCbCr420 mode, we need
1868 * to adjust the horizontal timing to suit.
1869 */
1870 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1871 hdisplay /= 2;
1872 hblank /= 2;
1873 h_de_hs /= 2;
1874 hsync_len /= 2;
1875 }
1876
1877 vdisplay = mode->vdisplay;
1878 vblank = mode->vtotal - mode->vdisplay;
1879 v_de_vs = mode->vsync_start - mode->vdisplay;
1880 vsync_len = mode->vsync_end - mode->vsync_start;
1881
1882 /*
1883 * When we're setting an interlaced mode, we need
1884 * to adjust the vertical timing to suit.
1885 */
1886 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1887 vdisplay /= 2;
1888 vblank /= 2;
1889 v_de_vs /= 2;
1890 vsync_len /= 2;
1891 }
1892
1893 /* Scrambling Control */
1894 if (dw_hdmi_support_scdc(hdmi)) {
1895 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1896 hdmi_info->scdc.scrambling.low_rates) {
1897 /*
1898 * HDMI2.0 Specifies the following procedure:
1899 * After the Source Device has determined that
1900 * SCDC_Present is set (=1), the Source Device should
1901 * write the accurate Version of the Source Device
1902 * to the Source Version field in the SCDCS.
1903 * Source Devices compliant shall set the
1904 * Source Version = 1.
1905 */
1906 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1907 &bytes);
1908 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1909 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1910
1911 /* Enabled Scrambling in the Sink */
1912 drm_scdc_set_scrambling(hdmi->ddc, 1);
1913
1914 /*
1915 * To activate the scrambler feature, you must ensure
1916 * that the quasi-static configuration bit
1917 * fc_invidconf.HDCP_keepout is set at configuration
1918 * time, before the required mc_swrstzreq.tmdsswrst_req
1919 * reset request is issued.
1920 */
1921 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1922 HDMI_MC_SWRSTZ);
1923 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1924 } else {
1925 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1926 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1927 HDMI_MC_SWRSTZ);
1928 drm_scdc_set_scrambling(hdmi->ddc, 0);
1929 }
1930 }
1931
1932 /* Set up horizontal active pixel width */
1933 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1934 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1935
1936 /* Set up vertical active lines */
1937 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1938 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1939
1940 /* Set up horizontal blanking pixel region width */
1941 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1942 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1943
1944 /* Set up vertical blanking pixel region width */
1945 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1946
1947 /* Set up HSYNC active edge delay width (in pixel clks) */
1948 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1949 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1950
1951 /* Set up VSYNC active edge delay (in lines) */
1952 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1953
1954 /* Set up HSYNC active pulse width (in pixel clks) */
1955 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1956 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1957
1958 /* Set up VSYNC active edge delay (in lines) */
1959 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1960 }
1961
1962 /* HDMI Initialization Step B.4 */
1963 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1964 {
1965 /* control period minimum duration */
1966 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1967 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1968 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1969
1970 /* Set to fill TMDS data channels */
1971 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1972 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1973 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1974
1975 /* Enable pixel clock and tmds data path */
1976 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1977 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1978 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1979 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1980 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1981 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1982 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1983
1984 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1985 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1986
1987 /* Enable csc path */
1988 if (is_color_space_conversion(hdmi)) {
1989 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1990 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1991 }
1992
1993 /* Enable color space conversion if needed */
1994 if (is_color_space_conversion(hdmi))
1995 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1996 HDMI_MC_FLOWCTRL);
1997 else
1998 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1999 HDMI_MC_FLOWCTRL);
2000 }
2001
2002 /* Workaround to clear the overflow condition */
2003 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2004 {
2005 unsigned int count;
2006 unsigned int i;
2007 u8 val;
2008
2009 /*
2010 * Under some circumstances the Frame Composer arithmetic unit can miss
2011 * an FC register write due to being busy processing the previous one.
2012 * The issue can be worked around by issuing a TMDS software reset and
2013 * then write one of the FC registers several times.
2014 *
2015 * The number of iterations matters and depends on the HDMI TX revision
2016 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2017 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2018 * as needing the workaround, with 4 iterations for v1.30a and 1
2019 * iteration for others.
2020 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2021 * the workaround with a single iteration.
2022 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2023 * been identified as needing the workaround with a single iteration.
2024 */
2025
2026 switch (hdmi->version) {
2027 case 0x130a:
2028 count = 4;
2029 break;
2030 case 0x131a:
2031 case 0x132a:
2032 case 0x200a:
2033 case 0x201a:
2034 case 0x211a:
2035 case 0x212a:
2036 count = 1;
2037 break;
2038 default:
2039 return;
2040 }
2041
2042 /* TMDS software reset */
2043 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2044
2045 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2046 for (i = 0; i < count; i++)
2047 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2048 }
2049
2050 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2051 {
2052 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2053 HDMI_IH_MUTE_FC_STAT2);
2054 }
2055
2056 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
2057 {
2058 int ret;
2059
2060 hdmi_disable_overflow_interrupts(hdmi);
2061
2062 hdmi->vic = drm_match_cea_mode(mode);
2063
2064 if (!hdmi->vic) {
2065 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2066 } else {
2067 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2068 }
2069
2070 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2071 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2072 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2073 (hdmi->vic == 17) || (hdmi->vic == 18))
2074 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2075 else
2076 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2077
2078 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2079 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2080
2081 /* TOFIX: Get input format from plat data or fallback to RGB888 */
2082 if (hdmi->plat_data->input_bus_format)
2083 hdmi->hdmi_data.enc_in_bus_format =
2084 hdmi->plat_data->input_bus_format;
2085 else
2086 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2087
2088 /* TOFIX: Get input encoding from plat data or fallback to none */
2089 if (hdmi->plat_data->input_bus_encoding)
2090 hdmi->hdmi_data.enc_in_encoding =
2091 hdmi->plat_data->input_bus_encoding;
2092 else
2093 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2094
2095 /* TOFIX: Default to RGB888 output format */
2096 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2097
2098 hdmi->hdmi_data.pix_repet_factor = 0;
2099 hdmi->hdmi_data.hdcp_enable = 0;
2100 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2101
2102 /* HDMI Initialization Step B.1 */
2103 hdmi_av_composer(hdmi, mode);
2104
2105 /* HDMI Initializateion Step B.2 */
2106 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
2107 if (ret)
2108 return ret;
2109 hdmi->phy.enabled = true;
2110
2111 /* HDMI Initialization Step B.3 */
2112 dw_hdmi_enable_video_path(hdmi);
2113
2114 if (hdmi->sink_has_audio) {
2115 dev_dbg(hdmi->dev, "sink has audio support\n");
2116
2117 /* HDMI Initialization Step E - Configure audio */
2118 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2119 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2120 }
2121
2122 /* not for DVI mode */
2123 if (hdmi->sink_is_hdmi) {
2124 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2125
2126 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2127 hdmi_config_AVI(hdmi, mode);
2128 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2129 hdmi_config_drm_infoframe(hdmi);
2130 } else {
2131 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2132 }
2133
2134 hdmi_video_packetize(hdmi);
2135 hdmi_video_csc(hdmi);
2136 hdmi_video_sample(hdmi);
2137 hdmi_tx_hdcp_config(hdmi);
2138
2139 dw_hdmi_clear_overflow(hdmi);
2140
2141 return 0;
2142 }
2143
2144 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2145 {
2146 u8 ih_mute;
2147
2148 /*
2149 * Boot up defaults are:
2150 * HDMI_IH_MUTE = 0x03 (disabled)
2151 * HDMI_IH_MUTE_* = 0x00 (enabled)
2152 *
2153 * Disable top level interrupt bits in HDMI block
2154 */
2155 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2156 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2157 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2158
2159 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2160
2161 /* by default mask all interrupts */
2162 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2163 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2164 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2165 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2166 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2167 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2168 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2169 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2170 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2171 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2172 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2173 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2174 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2175 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2176
2177 /* Disable interrupts in the IH_MUTE_* registers */
2178 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2179 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2180 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2181 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2182 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2183 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2184 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2185 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2186 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2187 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2188
2189 /* Enable top level interrupt bits in HDMI block */
2190 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2191 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2192 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2193 }
2194
2195 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2196 {
2197 hdmi->bridge_is_on = true;
2198 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2199 }
2200
2201 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2202 {
2203 if (hdmi->phy.enabled) {
2204 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2205 hdmi->phy.enabled = false;
2206 }
2207
2208 hdmi->bridge_is_on = false;
2209 }
2210
2211 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2212 {
2213 int force = hdmi->force;
2214
2215 if (hdmi->disabled) {
2216 force = DRM_FORCE_OFF;
2217 } else if (force == DRM_FORCE_UNSPECIFIED) {
2218 if (hdmi->rxsense)
2219 force = DRM_FORCE_ON;
2220 else
2221 force = DRM_FORCE_OFF;
2222 }
2223
2224 if (force == DRM_FORCE_OFF) {
2225 if (hdmi->bridge_is_on)
2226 dw_hdmi_poweroff(hdmi);
2227 } else {
2228 if (!hdmi->bridge_is_on)
2229 dw_hdmi_poweron(hdmi);
2230 }
2231 }
2232
2233 /*
2234 * Adjust the detection of RXSENSE according to whether we have a forced
2235 * connection mode enabled, or whether we have been disabled. There is
2236 * no point processing RXSENSE interrupts if we have a forced connection
2237 * state, or DRM has us disabled.
2238 *
2239 * We also disable rxsense interrupts when we think we're disconnected
2240 * to avoid floating TDMS signals giving false rxsense interrupts.
2241 *
2242 * Note: we still need to listen for HPD interrupts even when DRM has us
2243 * disabled so that we can detect a connect event.
2244 */
2245 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2246 {
2247 if (hdmi->phy.ops->update_hpd)
2248 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2249 hdmi->force, hdmi->disabled,
2250 hdmi->rxsense);
2251 }
2252
2253 static enum drm_connector_status
2254 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2255 {
2256 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2257 connector);
2258 enum drm_connector_status result;
2259
2260 mutex_lock(&hdmi->mutex);
2261 hdmi->force = DRM_FORCE_UNSPECIFIED;
2262 dw_hdmi_update_power(hdmi);
2263 dw_hdmi_update_phy_mask(hdmi);
2264 mutex_unlock(&hdmi->mutex);
2265
2266 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2267
2268 mutex_lock(&hdmi->mutex);
2269 if (result != hdmi->last_connector_result) {
2270 dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2271 handle_plugged_change(hdmi,
2272 result == connector_status_connected);
2273 hdmi->last_connector_result = result;
2274 }
2275 mutex_unlock(&hdmi->mutex);
2276
2277 return result;
2278 }
2279
2280 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2281 {
2282 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2283 connector);
2284 struct edid *edid;
2285 int ret = 0;
2286
2287 if (!hdmi->ddc)
2288 return 0;
2289
2290 edid = drm_get_edid(connector, hdmi->ddc);
2291 if (edid) {
2292 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2293 edid->width_cm, edid->height_cm);
2294
2295 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2296 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2297 drm_connector_update_edid_property(connector, edid);
2298 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2299 ret = drm_add_edid_modes(connector, edid);
2300 kfree(edid);
2301 } else {
2302 dev_dbg(hdmi->dev, "failed to get edid\n");
2303 }
2304
2305 return ret;
2306 }
2307
2308 static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2309 const struct drm_connector_state *new_state)
2310 {
2311 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2312 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2313
2314 if (!old_blob || !new_blob)
2315 return old_blob == new_blob;
2316
2317 if (old_blob->length != new_blob->length)
2318 return false;
2319
2320 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2321 }
2322
2323 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2324 struct drm_atomic_state *state)
2325 {
2326 struct drm_connector_state *old_state =
2327 drm_atomic_get_old_connector_state(state, connector);
2328 struct drm_connector_state *new_state =
2329 drm_atomic_get_new_connector_state(state, connector);
2330 struct drm_crtc *crtc = new_state->crtc;
2331 struct drm_crtc_state *crtc_state;
2332
2333 if (!crtc)
2334 return 0;
2335
2336 if (!hdr_metadata_equal(old_state, new_state)) {
2337 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2338 if (IS_ERR(crtc_state))
2339 return PTR_ERR(crtc_state);
2340
2341 crtc_state->mode_changed = true;
2342 }
2343
2344 return 0;
2345 }
2346
2347 static void dw_hdmi_connector_force(struct drm_connector *connector)
2348 {
2349 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2350 connector);
2351
2352 mutex_lock(&hdmi->mutex);
2353 hdmi->force = connector->force;
2354 dw_hdmi_update_power(hdmi);
2355 dw_hdmi_update_phy_mask(hdmi);
2356 mutex_unlock(&hdmi->mutex);
2357 }
2358
2359 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2360 .fill_modes = drm_helper_probe_single_connector_modes,
2361 .detect = dw_hdmi_connector_detect,
2362 .destroy = drm_connector_cleanup,
2363 .force = dw_hdmi_connector_force,
2364 .reset = drm_atomic_helper_connector_reset,
2365 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2366 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2367 };
2368
2369 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2370 .get_modes = dw_hdmi_connector_get_modes,
2371 .atomic_check = dw_hdmi_connector_atomic_check,
2372 };
2373
2374 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2375 {
2376 struct dw_hdmi *hdmi = bridge->driver_private;
2377 struct drm_encoder *encoder = bridge->encoder;
2378 struct drm_connector *connector = &hdmi->connector;
2379 struct cec_connector_info conn_info;
2380 struct cec_notifier *notifier;
2381
2382 connector->interlace_allowed = 1;
2383 connector->polled = DRM_CONNECTOR_POLL_HPD;
2384
2385 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2386
2387 drm_connector_init_with_ddc(bridge->dev, connector,
2388 &dw_hdmi_connector_funcs,
2389 DRM_MODE_CONNECTOR_HDMIA,
2390 hdmi->ddc);
2391
2392 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2393 drm_object_attach_property(&connector->base,
2394 connector->dev->mode_config.hdr_output_metadata_property, 0);
2395
2396 drm_connector_attach_encoder(connector, encoder);
2397
2398 cec_fill_conn_info_from_drm(&conn_info, connector);
2399
2400 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2401 if (!notifier)
2402 return -ENOMEM;
2403
2404 mutex_lock(&hdmi->cec_notifier_mutex);
2405 hdmi->cec_notifier = notifier;
2406 mutex_unlock(&hdmi->cec_notifier_mutex);
2407
2408 return 0;
2409 }
2410
2411 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2412 {
2413 struct dw_hdmi *hdmi = bridge->driver_private;
2414
2415 mutex_lock(&hdmi->cec_notifier_mutex);
2416 cec_notifier_conn_unregister(hdmi->cec_notifier);
2417 hdmi->cec_notifier = NULL;
2418 mutex_unlock(&hdmi->cec_notifier_mutex);
2419 }
2420
2421 static enum drm_mode_status
2422 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2423 const struct drm_display_mode *mode)
2424 {
2425 struct dw_hdmi *hdmi = bridge->driver_private;
2426 struct drm_connector *connector = &hdmi->connector;
2427 enum drm_mode_status mode_status = MODE_OK;
2428
2429 /* We don't support double-clocked modes */
2430 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2431 return MODE_BAD;
2432
2433 if (hdmi->plat_data->mode_valid)
2434 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2435
2436 return mode_status;
2437 }
2438
2439 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2440 const struct drm_display_mode *orig_mode,
2441 const struct drm_display_mode *mode)
2442 {
2443 struct dw_hdmi *hdmi = bridge->driver_private;
2444
2445 mutex_lock(&hdmi->mutex);
2446
2447 /* Store the display mode for plugin/DKMS poweron events */
2448 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2449
2450 mutex_unlock(&hdmi->mutex);
2451 }
2452
2453 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2454 {
2455 struct dw_hdmi *hdmi = bridge->driver_private;
2456
2457 mutex_lock(&hdmi->mutex);
2458 hdmi->disabled = true;
2459 dw_hdmi_update_power(hdmi);
2460 dw_hdmi_update_phy_mask(hdmi);
2461 mutex_unlock(&hdmi->mutex);
2462 }
2463
2464 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2465 {
2466 struct dw_hdmi *hdmi = bridge->driver_private;
2467
2468 mutex_lock(&hdmi->mutex);
2469 hdmi->disabled = false;
2470 dw_hdmi_update_power(hdmi);
2471 dw_hdmi_update_phy_mask(hdmi);
2472 mutex_unlock(&hdmi->mutex);
2473 }
2474
2475 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2476 .attach = dw_hdmi_bridge_attach,
2477 .detach = dw_hdmi_bridge_detach,
2478 .enable = dw_hdmi_bridge_enable,
2479 .disable = dw_hdmi_bridge_disable,
2480 .mode_set = dw_hdmi_bridge_mode_set,
2481 .mode_valid = dw_hdmi_bridge_mode_valid,
2482 };
2483
2484 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2485 {
2486 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2487 unsigned int stat;
2488
2489 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2490 if (!stat)
2491 return IRQ_NONE;
2492
2493 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2494
2495 i2c->stat = stat;
2496
2497 complete(&i2c->cmp);
2498
2499 return IRQ_HANDLED;
2500 }
2501
2502 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2503 {
2504 struct dw_hdmi *hdmi = dev_id;
2505 u8 intr_stat;
2506 irqreturn_t ret = IRQ_NONE;
2507
2508 if (hdmi->i2c)
2509 ret = dw_hdmi_i2c_irq(hdmi);
2510
2511 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2512 if (intr_stat) {
2513 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2514 return IRQ_WAKE_THREAD;
2515 }
2516
2517 return ret;
2518 }
2519
2520 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2521 {
2522 mutex_lock(&hdmi->mutex);
2523
2524 if (!hdmi->force) {
2525 /*
2526 * If the RX sense status indicates we're disconnected,
2527 * clear the software rxsense status.
2528 */
2529 if (!rx_sense)
2530 hdmi->rxsense = false;
2531
2532 /*
2533 * Only set the software rxsense status when both
2534 * rxsense and hpd indicates we're connected.
2535 * This avoids what seems to be bad behaviour in
2536 * at least iMX6S versions of the phy.
2537 */
2538 if (hpd)
2539 hdmi->rxsense = true;
2540
2541 dw_hdmi_update_power(hdmi);
2542 dw_hdmi_update_phy_mask(hdmi);
2543 }
2544 mutex_unlock(&hdmi->mutex);
2545 }
2546 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2547
2548 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2549 {
2550 struct dw_hdmi *hdmi = dev_id;
2551 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2552
2553 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2554 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2555 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2556
2557 phy_pol_mask = 0;
2558 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2559 phy_pol_mask |= HDMI_PHY_HPD;
2560 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2561 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2562 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2563 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2564 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2565 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2566 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2567 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2568
2569 if (phy_pol_mask)
2570 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2571
2572 /*
2573 * RX sense tells us whether the TDMS transmitters are detecting
2574 * load - in other words, there's something listening on the
2575 * other end of the link. Use this to decide whether we should
2576 * power on the phy as HPD may be toggled by the sink to merely
2577 * ask the source to re-read the EDID.
2578 */
2579 if (intr_stat &
2580 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2581 dw_hdmi_setup_rx_sense(hdmi,
2582 phy_stat & HDMI_PHY_HPD,
2583 phy_stat & HDMI_PHY_RX_SENSE);
2584
2585 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
2586 mutex_lock(&hdmi->cec_notifier_mutex);
2587 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
2588 mutex_unlock(&hdmi->cec_notifier_mutex);
2589 }
2590 }
2591
2592 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2593 dev_dbg(hdmi->dev, "EVENT=%s\n",
2594 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2595 if (hdmi->bridge.dev)
2596 drm_helper_hpd_irq_event(hdmi->bridge.dev);
2597 }
2598
2599 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2600 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2601 HDMI_IH_MUTE_PHY_STAT0);
2602
2603 return IRQ_HANDLED;
2604 }
2605
2606 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2607 {
2608 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2609 .name = "DWC HDMI TX PHY",
2610 .gen = 1,
2611 }, {
2612 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2613 .name = "DWC MHL PHY + HEAC PHY",
2614 .gen = 2,
2615 .has_svsret = true,
2616 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2617 }, {
2618 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2619 .name = "DWC MHL PHY",
2620 .gen = 2,
2621 .has_svsret = true,
2622 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2623 }, {
2624 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2625 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2626 .gen = 2,
2627 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2628 }, {
2629 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2630 .name = "DWC HDMI 3D TX PHY",
2631 .gen = 2,
2632 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2633 }, {
2634 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2635 .name = "DWC HDMI 2.0 TX PHY",
2636 .gen = 2,
2637 .has_svsret = true,
2638 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2639 }, {
2640 .type = DW_HDMI_PHY_VENDOR_PHY,
2641 .name = "Vendor PHY",
2642 }
2643 };
2644
2645 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2646 {
2647 unsigned int i;
2648 u8 phy_type;
2649
2650 phy_type = hdmi->plat_data->phy_force_vendor ?
2651 DW_HDMI_PHY_VENDOR_PHY :
2652 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2653
2654 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2655 /* Vendor PHYs require support from the glue layer. */
2656 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2657 dev_err(hdmi->dev,
2658 "Vendor HDMI PHY not supported by glue layer\n");
2659 return -ENODEV;
2660 }
2661
2662 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2663 hdmi->phy.data = hdmi->plat_data->phy_data;
2664 hdmi->phy.name = hdmi->plat_data->phy_name;
2665 return 0;
2666 }
2667
2668 /* Synopsys PHYs are handled internally. */
2669 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2670 if (dw_hdmi_phys[i].type == phy_type) {
2671 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2672 hdmi->phy.name = dw_hdmi_phys[i].name;
2673 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2674
2675 if (!dw_hdmi_phys[i].configure &&
2676 !hdmi->plat_data->configure_phy) {
2677 dev_err(hdmi->dev, "%s requires platform support\n",
2678 hdmi->phy.name);
2679 return -ENODEV;
2680 }
2681
2682 return 0;
2683 }
2684 }
2685
2686 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2687 return -ENODEV;
2688 }
2689
2690 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2691 {
2692 mutex_lock(&hdmi->mutex);
2693 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2694 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2695 mutex_unlock(&hdmi->mutex);
2696 }
2697
2698 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2699 {
2700 mutex_lock(&hdmi->mutex);
2701 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2702 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2703 mutex_unlock(&hdmi->mutex);
2704 }
2705
2706 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2707 .write = hdmi_writeb,
2708 .read = hdmi_readb,
2709 .enable = dw_hdmi_cec_enable,
2710 .disable = dw_hdmi_cec_disable,
2711 };
2712
2713 static const struct regmap_config hdmi_regmap_8bit_config = {
2714 .reg_bits = 32,
2715 .val_bits = 8,
2716 .reg_stride = 1,
2717 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2718 };
2719
2720 static const struct regmap_config hdmi_regmap_32bit_config = {
2721 .reg_bits = 32,
2722 .val_bits = 32,
2723 .reg_stride = 4,
2724 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2725 };
2726
2727 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
2728 {
2729 initialize_hdmi_ih_mutes(hdmi);
2730
2731 /*
2732 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
2733 * Even if we are using a separate i2c adapter doing this doesn't
2734 * hurt.
2735 */
2736 dw_hdmi_i2c_init(hdmi);
2737
2738 if (hdmi->phy.ops->setup_hpd)
2739 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2740 }
2741
2742 static struct dw_hdmi *
2743 __dw_hdmi_probe(struct platform_device *pdev,
2744 const struct dw_hdmi_plat_data *plat_data)
2745 {
2746 struct device *dev = &pdev->dev;
2747 struct device_node *np = dev->of_node;
2748 struct platform_device_info pdevinfo;
2749 struct device_node *ddc_node;
2750 struct dw_hdmi_cec_data cec;
2751 struct dw_hdmi *hdmi;
2752 struct resource *iores = NULL;
2753 int irq;
2754 int ret;
2755 u32 val = 1;
2756 u8 prod_id0;
2757 u8 prod_id1;
2758 u8 config0;
2759 u8 config3;
2760
2761 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2762 if (!hdmi)
2763 return ERR_PTR(-ENOMEM);
2764
2765 hdmi->plat_data = plat_data;
2766 hdmi->dev = dev;
2767 hdmi->sample_rate = 48000;
2768 hdmi->disabled = true;
2769 hdmi->rxsense = true;
2770 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2771 hdmi->mc_clkdis = 0x7f;
2772 hdmi->last_connector_result = connector_status_disconnected;
2773
2774 mutex_init(&hdmi->mutex);
2775 mutex_init(&hdmi->audio_mutex);
2776 mutex_init(&hdmi->cec_notifier_mutex);
2777 spin_lock_init(&hdmi->audio_lock);
2778
2779 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2780 if (ddc_node) {
2781 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2782 of_node_put(ddc_node);
2783 if (!hdmi->ddc) {
2784 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2785 return ERR_PTR(-EPROBE_DEFER);
2786 }
2787
2788 } else {
2789 dev_dbg(hdmi->dev, "no ddc property found\n");
2790 }
2791
2792 if (!plat_data->regm) {
2793 const struct regmap_config *reg_config;
2794
2795 of_property_read_u32(np, "reg-io-width", &val);
2796 switch (val) {
2797 case 4:
2798 reg_config = &hdmi_regmap_32bit_config;
2799 hdmi->reg_shift = 2;
2800 break;
2801 case 1:
2802 reg_config = &hdmi_regmap_8bit_config;
2803 break;
2804 default:
2805 dev_err(dev, "reg-io-width must be 1 or 4\n");
2806 return ERR_PTR(-EINVAL);
2807 }
2808
2809 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2810 hdmi->regs = devm_ioremap_resource(dev, iores);
2811 if (IS_ERR(hdmi->regs)) {
2812 ret = PTR_ERR(hdmi->regs);
2813 goto err_res;
2814 }
2815
2816 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2817 if (IS_ERR(hdmi->regm)) {
2818 dev_err(dev, "Failed to configure regmap\n");
2819 ret = PTR_ERR(hdmi->regm);
2820 goto err_res;
2821 }
2822 } else {
2823 hdmi->regm = plat_data->regm;
2824 }
2825
2826 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2827 if (IS_ERR(hdmi->isfr_clk)) {
2828 ret = PTR_ERR(hdmi->isfr_clk);
2829 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2830 goto err_res;
2831 }
2832
2833 ret = clk_prepare_enable(hdmi->isfr_clk);
2834 if (ret) {
2835 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2836 goto err_res;
2837 }
2838
2839 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2840 if (IS_ERR(hdmi->iahb_clk)) {
2841 ret = PTR_ERR(hdmi->iahb_clk);
2842 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2843 goto err_isfr;
2844 }
2845
2846 ret = clk_prepare_enable(hdmi->iahb_clk);
2847 if (ret) {
2848 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2849 goto err_isfr;
2850 }
2851
2852 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2853 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2854 hdmi->cec_clk = NULL;
2855 } else if (IS_ERR(hdmi->cec_clk)) {
2856 ret = PTR_ERR(hdmi->cec_clk);
2857 if (ret != -EPROBE_DEFER)
2858 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2859 ret);
2860
2861 hdmi->cec_clk = NULL;
2862 goto err_iahb;
2863 } else {
2864 ret = clk_prepare_enable(hdmi->cec_clk);
2865 if (ret) {
2866 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2867 ret);
2868 goto err_iahb;
2869 }
2870 }
2871
2872 /* Product and revision IDs */
2873 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2874 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2875 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2876 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2877
2878 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2879 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2880 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2881 hdmi->version, prod_id0, prod_id1);
2882 ret = -ENODEV;
2883 goto err_iahb;
2884 }
2885
2886 ret = dw_hdmi_detect_phy(hdmi);
2887 if (ret < 0)
2888 goto err_iahb;
2889
2890 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2891 hdmi->version >> 12, hdmi->version & 0xfff,
2892 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2893 hdmi->phy.name);
2894
2895 dw_hdmi_init_hw(hdmi);
2896
2897 irq = platform_get_irq(pdev, 0);
2898 if (irq < 0) {
2899 ret = irq;
2900 goto err_iahb;
2901 }
2902
2903 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2904 dw_hdmi_irq, IRQF_SHARED,
2905 dev_name(dev), hdmi);
2906 if (ret)
2907 goto err_iahb;
2908
2909 /*
2910 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2911 * N and cts values before enabling phy
2912 */
2913 hdmi_init_clk_regenerator(hdmi);
2914
2915 /* If DDC bus is not specified, try to register HDMI I2C bus */
2916 if (!hdmi->ddc) {
2917 /* Look for (optional) stuff related to unwedging */
2918 hdmi->pinctrl = devm_pinctrl_get(dev);
2919 if (!IS_ERR(hdmi->pinctrl)) {
2920 hdmi->unwedge_state =
2921 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2922 hdmi->default_state =
2923 pinctrl_lookup_state(hdmi->pinctrl, "default");
2924
2925 if (IS_ERR(hdmi->default_state) ||
2926 IS_ERR(hdmi->unwedge_state)) {
2927 if (!IS_ERR(hdmi->unwedge_state))
2928 dev_warn(dev,
2929 "Unwedge requires default pinctrl\n");
2930 hdmi->default_state = NULL;
2931 hdmi->unwedge_state = NULL;
2932 }
2933 }
2934
2935 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2936 if (IS_ERR(hdmi->ddc))
2937 hdmi->ddc = NULL;
2938 }
2939
2940 hdmi->bridge.driver_private = hdmi;
2941 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2942 #ifdef CONFIG_OF
2943 hdmi->bridge.of_node = pdev->dev.of_node;
2944 #endif
2945
2946 memset(&pdevinfo, 0, sizeof(pdevinfo));
2947 pdevinfo.parent = dev;
2948 pdevinfo.id = PLATFORM_DEVID_AUTO;
2949
2950 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2951 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2952
2953 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2954 struct dw_hdmi_audio_data audio;
2955
2956 audio.phys = iores->start;
2957 audio.base = hdmi->regs;
2958 audio.irq = irq;
2959 audio.hdmi = hdmi;
2960 audio.eld = hdmi->connector.eld;
2961 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2962 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2963
2964 pdevinfo.name = "dw-hdmi-ahb-audio";
2965 pdevinfo.data = &audio;
2966 pdevinfo.size_data = sizeof(audio);
2967 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2968 hdmi->audio = platform_device_register_full(&pdevinfo);
2969 } else if (config0 & HDMI_CONFIG0_I2S) {
2970 struct dw_hdmi_i2s_audio_data audio;
2971
2972 audio.hdmi = hdmi;
2973 audio.eld = hdmi->connector.eld;
2974 audio.write = hdmi_writeb;
2975 audio.read = hdmi_readb;
2976 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2977 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2978
2979 pdevinfo.name = "dw-hdmi-i2s-audio";
2980 pdevinfo.data = &audio;
2981 pdevinfo.size_data = sizeof(audio);
2982 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2983 hdmi->audio = platform_device_register_full(&pdevinfo);
2984 }
2985
2986 if (config0 & HDMI_CONFIG0_CEC) {
2987 cec.hdmi = hdmi;
2988 cec.ops = &dw_hdmi_cec_ops;
2989 cec.irq = irq;
2990
2991 pdevinfo.name = "dw-hdmi-cec";
2992 pdevinfo.data = &cec;
2993 pdevinfo.size_data = sizeof(cec);
2994 pdevinfo.dma_mask = 0;
2995
2996 hdmi->cec = platform_device_register_full(&pdevinfo);
2997 }
2998
2999 return hdmi;
3000
3001 err_iahb:
3002 if (hdmi->i2c) {
3003 i2c_del_adapter(&hdmi->i2c->adap);
3004 hdmi->ddc = NULL;
3005 }
3006
3007 clk_disable_unprepare(hdmi->iahb_clk);
3008 if (hdmi->cec_clk)
3009 clk_disable_unprepare(hdmi->cec_clk);
3010 err_isfr:
3011 clk_disable_unprepare(hdmi->isfr_clk);
3012 err_res:
3013 i2c_put_adapter(hdmi->ddc);
3014
3015 return ERR_PTR(ret);
3016 }
3017
3018 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
3019 {
3020 if (hdmi->audio && !IS_ERR(hdmi->audio))
3021 platform_device_unregister(hdmi->audio);
3022 if (!IS_ERR(hdmi->cec))
3023 platform_device_unregister(hdmi->cec);
3024
3025 /* Disable all interrupts */
3026 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3027
3028 clk_disable_unprepare(hdmi->iahb_clk);
3029 clk_disable_unprepare(hdmi->isfr_clk);
3030 if (hdmi->cec_clk)
3031 clk_disable_unprepare(hdmi->cec_clk);
3032
3033 if (hdmi->i2c)
3034 i2c_del_adapter(&hdmi->i2c->adap);
3035 else
3036 i2c_put_adapter(hdmi->ddc);
3037 }
3038
3039 /* -----------------------------------------------------------------------------
3040 * Probe/remove API, used from platforms based on the DRM bridge API.
3041 */
3042 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3043 const struct dw_hdmi_plat_data *plat_data)
3044 {
3045 struct dw_hdmi *hdmi;
3046
3047 hdmi = __dw_hdmi_probe(pdev, plat_data);
3048 if (IS_ERR(hdmi))
3049 return hdmi;
3050
3051 drm_bridge_add(&hdmi->bridge);
3052
3053 return hdmi;
3054 }
3055 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3056
3057 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3058 {
3059 drm_bridge_remove(&hdmi->bridge);
3060
3061 __dw_hdmi_remove(hdmi);
3062 }
3063 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3064
3065 /* -----------------------------------------------------------------------------
3066 * Bind/unbind API, used from platforms based on the component framework.
3067 */
3068 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3069 struct drm_encoder *encoder,
3070 const struct dw_hdmi_plat_data *plat_data)
3071 {
3072 struct dw_hdmi *hdmi;
3073 int ret;
3074
3075 hdmi = __dw_hdmi_probe(pdev, plat_data);
3076 if (IS_ERR(hdmi))
3077 return hdmi;
3078
3079 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
3080 if (ret) {
3081 dw_hdmi_remove(hdmi);
3082 DRM_ERROR("Failed to initialize bridge with drm\n");
3083 return ERR_PTR(ret);
3084 }
3085
3086 return hdmi;
3087 }
3088 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3089
3090 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3091 {
3092 __dw_hdmi_remove(hdmi);
3093 }
3094 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3095
3096 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3097 {
3098 dw_hdmi_init_hw(hdmi);
3099 }
3100 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3101
3102 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3103 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3104 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3105 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3106 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3107 MODULE_LICENSE("GPL");
3108 MODULE_ALIAS("platform:dw-hdmi");
Linux with added FPC-III support