drivers/gpu/drm/gma500/oaktrail_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Authors:
   6  *      Eric Anholt <eric@anholt.net>
   7  *      Dave Airlie <airlied@linux.ie>
   8  *      Jesse Barnes <jesse.barnes@intel.com>
   9  */
  10
  11 #include <linux/i2c.h>
  12 #include <linux/pm_runtime.h>
  13
  14 #include <asm/intel-mid.h>
  15
  16 #include "intel_bios.h"
  17 #include "power.h"
  18 #include "psb_drv.h"
  19 #include "psb_intel_drv.h"
  20 #include "psb_intel_reg.h"
  21
  22 /* The max/min PWM frequency in BPCR[31:17] - */
  23 /* The smallest number is 1 (not 0) that can fit in the
  24  * 15-bit field of the and then*/
  25 /* shifts to the left by one bit to get the actual 16-bit
  26  * value that the 15-bits correspond to.*/
  27 #define MRST_BLC_MAX_PWM_REG_FREQ           0xFFFF
  28 #define BRIGHTNESS_MAX_LEVEL 100
  29
  30 /**
  31  * Sets the power state for the panel.
  32  */
  33 static void oaktrail_lvds_set_power(struct drm_device *dev,
  34                                 struct gma_encoder *gma_encoder,
  35                                 bool on)
  36 {
  37         u32 pp_status;
  38         struct drm_psb_private *dev_priv = dev->dev_private;
  39
  40         if (!gma_power_begin(dev, true))
  41                 return;
  42
  43         if (on) {
  44                 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  45                           POWER_TARGET_ON);
  46                 do {
  47                         pp_status = REG_READ(PP_STATUS);
  48                 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
  49                 dev_priv->is_lvds_on = true;
  50                 if (dev_priv->ops->lvds_bl_power)
  51                         dev_priv->ops->lvds_bl_power(dev, true);
  52         } else {
  53                 if (dev_priv->ops->lvds_bl_power)
  54                         dev_priv->ops->lvds_bl_power(dev, false);
  55                 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  56                           ~POWER_TARGET_ON);
  57                 do {
  58                         pp_status = REG_READ(PP_STATUS);
  59                 } while (pp_status & PP_ON);
  60                 dev_priv->is_lvds_on = false;
  61                 pm_request_idle(&dev->pdev->dev);
  62         }
  63         gma_power_end(dev);
  64 }
  65
  66 static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
  67 {
  68         struct drm_device *dev = encoder->dev;
  69         struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  70
  71         if (mode == DRM_MODE_DPMS_ON)
  72                 oaktrail_lvds_set_power(dev, gma_encoder, true);
  73         else
  74                 oaktrail_lvds_set_power(dev, gma_encoder, false);
  75
  76         /* XXX: We never power down the LVDS pairs. */
  77 }
  78
  79 static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
  80                                struct drm_display_mode *mode,
  81                                struct drm_display_mode *adjusted_mode)
  82 {
  83         struct drm_device *dev = encoder->dev;
  84         struct drm_psb_private *dev_priv = dev->dev_private;
  85         struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  86         struct drm_mode_config *mode_config = &dev->mode_config;
  87         struct drm_connector *connector = NULL;
  88         struct drm_crtc *crtc = encoder->crtc;
  89         u32 lvds_port;
  90         uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
  91
  92         if (!gma_power_begin(dev, true))
  93                 return;
  94
  95         /*
  96          * The LVDS pin pair will already have been turned on in the
  97          * psb_intel_crtc_mode_set since it has a large impact on the DPLL
  98          * settings.
  99          */
 100         lvds_port = (REG_READ(LVDS) &
 101                     (~LVDS_PIPEB_SELECT)) |
 102                     LVDS_PORT_EN |
 103                     LVDS_BORDER_EN;
 104
 105         /* If the firmware says dither on Moorestown, or the BIOS does
 106            on Oaktrail then enable dithering */
 107         if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
 108                 lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
 109
 110         REG_WRITE(LVDS, lvds_port);
 111
 112         /* Find the connector we're trying to set up */
 113         list_for_each_entry(connector, &mode_config->connector_list, head) {
 114                 if (!connector->encoder || connector->encoder->crtc != crtc)
 115                         continue;
 116         }
 117
 118         if (!connector) {
 119                 DRM_ERROR("Couldn't find connector when setting mode");
 120                 gma_power_end(dev);
 121                 return;
 122         }
 123
 124         drm_object_property_get_value(
 125                 &connector->base,
 126                 dev->mode_config.scaling_mode_property,
 127                 &v);
 128
 129         if (v == DRM_MODE_SCALE_NO_SCALE)
 130                 REG_WRITE(PFIT_CONTROL, 0);
 131         else if (v == DRM_MODE_SCALE_ASPECT) {
 132                 if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
 133                     (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
 134                         if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
 135                             (mode->hdisplay * adjusted_mode->crtc_vdisplay))
 136                                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
 137                         else if ((adjusted_mode->crtc_hdisplay *
 138                                 mode->vdisplay) > (mode->hdisplay *
 139                                 adjusted_mode->crtc_vdisplay))
 140                                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
 141                                           PFIT_SCALING_MODE_PILLARBOX);
 142                         else
 143                                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
 144                                           PFIT_SCALING_MODE_LETTERBOX);
 145                 } else
 146                         REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
 147         } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
 148                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
 149
 150         gma_power_end(dev);
 151 }
 152
 153 static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
 154 {
 155         struct drm_device *dev = encoder->dev;
 156         struct drm_psb_private *dev_priv = dev->dev_private;
 157         struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
 158         struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
 159
 160         if (!gma_power_begin(dev, true))
 161                 return;
 162
 163         mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
 164         mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
 165                                           BACKLIGHT_DUTY_CYCLE_MASK);
 166         oaktrail_lvds_set_power(dev, gma_encoder, false);
 167         gma_power_end(dev);
 168 }
 169
 170 static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
 171 {
 172         struct drm_psb_private *dev_priv = dev->dev_private;
 173         u32 ret;
 174
 175         if (gma_power_begin(dev, false)) {
 176                 ret = ((REG_READ(BLC_PWM_CTL) &
 177                           BACKLIGHT_MODULATION_FREQ_MASK) >>
 178                           BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
 179
 180                 gma_power_end(dev);
 181         } else
 182                 ret = ((dev_priv->regs.saveBLC_PWM_CTL &
 183                           BACKLIGHT_MODULATION_FREQ_MASK) >>
 184                           BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
 185
 186         return ret;
 187 }
 188
 189 static void oaktrail_lvds_commit(struct drm_encoder *encoder)
 190 {
 191         struct drm_device *dev = encoder->dev;
 192         struct drm_psb_private *dev_priv = dev->dev_private;
 193         struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
 194         struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
 195
 196         if (mode_dev->backlight_duty_cycle == 0)
 197                 mode_dev->backlight_duty_cycle =
 198                                         oaktrail_lvds_get_max_backlight(dev);
 199         oaktrail_lvds_set_power(dev, gma_encoder, true);
 200 }
 201
 202 static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
 203         .dpms = oaktrail_lvds_dpms,
 204         .mode_fixup = psb_intel_lvds_mode_fixup,
 205         .prepare = oaktrail_lvds_prepare,
 206         .mode_set = oaktrail_lvds_mode_set,
 207         .commit = oaktrail_lvds_commit,
 208 };
 209
 210 /* Returns the panel fixed mode from configuration. */
 211
 212 static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
 213                                         struct psb_intel_mode_device *mode_dev)
 214 {
 215         struct drm_display_mode *mode = NULL;
 216         struct drm_psb_private *dev_priv = dev->dev_private;
 217         struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
 218
 219         mode_dev->panel_fixed_mode = NULL;
 220
 221         /* Use the firmware provided data on Moorestown */
 222         if (dev_priv->has_gct) {
 223                 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 224                 if (!mode)
 225                         return;
 226
 227                 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
 228                 mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
 229                 mode->hsync_start = mode->hdisplay + \
 230                                 ((ti->hsync_offset_hi << 8) | \
 231                                 ti->hsync_offset_lo);
 232                 mode->hsync_end = mode->hsync_start + \
 233                                 ((ti->hsync_pulse_width_hi << 8) | \
 234                                 ti->hsync_pulse_width_lo);
 235                 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
 236                                                         ti->hblank_lo);
 237                 mode->vsync_start = \
 238                         mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
 239                                                 ti->vsync_offset_lo);
 240                 mode->vsync_end = \
 241                         mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
 242                                                 ti->vsync_pulse_width_lo);
 243                 mode->vtotal = mode->vdisplay + \
 244                                 ((ti->vblank_hi << 8) | ti->vblank_lo);
 245                 mode->clock = ti->pixel_clock * 10;
 246 #if 0
 247                 pr_info("hdisplay is %d\n", mode->hdisplay);
 248                 pr_info("vdisplay is %d\n", mode->vdisplay);
 249                 pr_info("HSS is %d\n", mode->hsync_start);
 250                 pr_info("HSE is %d\n", mode->hsync_end);
 251                 pr_info("htotal is %d\n", mode->htotal);
 252                 pr_info("VSS is %d\n", mode->vsync_start);
 253                 pr_info("VSE is %d\n", mode->vsync_end);
 254                 pr_info("vtotal is %d\n", mode->vtotal);
 255                 pr_info("clock is %d\n", mode->clock);
 256 #endif
 257                 mode_dev->panel_fixed_mode = mode;
 258         }
 259
 260         /* Use the BIOS VBT mode if available */
 261         if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
 262                 mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
 263                                                 mode_dev->vbt_mode);
 264
 265         /* Then try the LVDS VBT mode */
 266         if (mode_dev->panel_fixed_mode == NULL)
 267                 if (dev_priv->lfp_lvds_vbt_mode)
 268                         mode_dev->panel_fixed_mode =
 269                                 drm_mode_duplicate(dev,
 270                                         dev_priv->lfp_lvds_vbt_mode);
 271
 272         /* If we still got no mode then bail */
 273         if (mode_dev->panel_fixed_mode == NULL)
 274                 return;
 275
 276         drm_mode_set_name(mode_dev->panel_fixed_mode);
 277         drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
 278 }
 279
 280 /**
 281  * oaktrail_lvds_init - setup LVDS connectors on this device
 282  * @dev: drm device
 283  *
 284  * Create the connector, register the LVDS DDC bus, and try to figure out what
 285  * modes we can display on the LVDS panel (if present).
 286  */
 287 void oaktrail_lvds_init(struct drm_device *dev,
 288                     struct psb_intel_mode_device *mode_dev)
 289 {
 290         struct gma_encoder *gma_encoder;
 291         struct gma_connector *gma_connector;
 292         struct drm_connector *connector;
 293         struct drm_encoder *encoder;
 294         struct drm_psb_private *dev_priv = dev->dev_private;
 295         struct edid *edid;
 296         struct i2c_adapter *i2c_adap;
 297         struct drm_display_mode *scan;  /* *modes, *bios_mode; */
 298
 299         gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
 300         if (!gma_encoder)
 301                 return;
 302
 303         gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
 304         if (!gma_connector)
 305                 goto failed_connector;
 306
 307         connector = &gma_connector->base;
 308         encoder = &gma_encoder->base;
 309         dev_priv->is_lvds_on = true;
 310         drm_connector_init(dev, connector,
 311                            &psb_intel_lvds_connector_funcs,
 312                            DRM_MODE_CONNECTOR_LVDS);
 313
 314         drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
 315                          DRM_MODE_ENCODER_LVDS, NULL);
 316
 317         gma_connector_attach_encoder(gma_connector, gma_encoder);
 318         gma_encoder->type = INTEL_OUTPUT_LVDS;
 319
 320         drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
 321         drm_connector_helper_add(connector,
 322                                  &psb_intel_lvds_connector_helper_funcs);
 323         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 324         connector->interlace_allowed = false;
 325         connector->doublescan_allowed = false;
 326
 327         drm_object_attach_property(&connector->base,
 328                                         dev->mode_config.scaling_mode_property,
 329                                         DRM_MODE_SCALE_FULLSCREEN);
 330         drm_object_attach_property(&connector->base,
 331                                         dev_priv->backlight_property,
 332                                         BRIGHTNESS_MAX_LEVEL);
 333
 334         mode_dev->panel_wants_dither = false;
 335         if (dev_priv->has_gct)
 336                 mode_dev->panel_wants_dither = (dev_priv->gct_data.
 337                         Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
 338         if (dev_priv->lvds_dither)
 339                 mode_dev->panel_wants_dither = 1;
 340
 341         /*
 342          * LVDS discovery:
 343          * 1) check for EDID on DDC
 344          * 2) check for VBT data
 345          * 3) check to see if LVDS is already on
 346          *    if none of the above, no panel
 347          * 4) make sure lid is open
 348          *    if closed, act like it's not there for now
 349          */
 350
 351         edid = NULL;
 352         mutex_lock(&dev->mode_config.mutex);
 353         i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
 354         if (i2c_adap)
 355                 edid = drm_get_edid(connector, i2c_adap);
 356         if (edid == NULL && dev_priv->lpc_gpio_base) {
 357                 oaktrail_lvds_i2c_init(encoder);
 358                 if (gma_encoder->ddc_bus != NULL) {
 359                         i2c_adap = &gma_encoder->ddc_bus->adapter;
 360                         edid = drm_get_edid(connector, i2c_adap);
 361                 }
 362         }
 363         /*
 364          * Attempt to get the fixed panel mode from DDC.  Assume that the
 365          * preferred mode is the right one.
 366          */
 367         if (edid) {
 368                 drm_connector_update_edid_property(connector, edid);
 369                 drm_add_edid_modes(connector, edid);
 370                 kfree(edid);
 371
 372                 list_for_each_entry(scan, &connector->probed_modes, head) {
 373                         if (scan->type & DRM_MODE_TYPE_PREFERRED) {
 374                                 mode_dev->panel_fixed_mode =
 375                                     drm_mode_duplicate(dev, scan);
 376                                 goto out;       /* FIXME: check for quirks */
 377                         }
 378                 }
 379         } else
 380                 dev_err(dev->dev, "No ddc adapter available!\n");
 381         /*
 382          * If we didn't get EDID, try geting panel timing
 383          * from configuration data
 384          */
 385         oaktrail_lvds_get_configuration_mode(dev, mode_dev);
 386
 387         if (mode_dev->panel_fixed_mode) {
 388                 mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 389                 goto out;       /* FIXME: check for quirks */
 390         }
 391
 392         /* If we still don't have a mode after all that, give up. */
 393         if (!mode_dev->panel_fixed_mode) {
 394                 dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
 395                 goto failed_find;
 396         }
 397
 398 out:
 399         mutex_unlock(&dev->mode_config.mutex);
 400
 401         drm_connector_register(connector);
 402         return;
 403
 404 failed_find:
 405         mutex_unlock(&dev->mode_config.mutex);
 406
 407         dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
 408         if (gma_encoder->ddc_bus) {
 409                 psb_intel_i2c_destroy(gma_encoder->ddc_bus);
 410                 gma_encoder->ddc_bus = NULL;
 411         }
 412
 413 /* failed_ddc: */
 414
 415         drm_encoder_cleanup(encoder);
 416         drm_connector_cleanup(connector);
 417         kfree(gma_connector);
 418 failed_connector:
 419         kfree(gma_encoder);
 420 }
 421