1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
9 #include <linux/types.h>
11 #include <drm/i915_drm.h>
17 struct drm_connector_state
;
19 struct drm_i915_private
;
20 struct drm_modeset_acquire_ctx
;
21 struct intel_connector
;
22 struct intel_crtc_state
;
23 struct intel_digital_port
;
27 struct link_config_limits
{
28 int min_clock
, max_clock
;
29 int min_lane_count
, max_lane_count
;
33 void intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
34 struct intel_crtc_state
*pipe_config
,
35 struct link_config_limits
*limits
);
36 bool intel_dp_limited_color_range(const struct intel_crtc_state
*crtc_state
,
37 const struct drm_connector_state
*conn_state
);
38 int intel_dp_min_bpp(const struct intel_crtc_state
*crtc_state
);
39 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
40 i915_reg_t dp_reg
, enum port port
,
42 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
44 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
45 struct intel_connector
*intel_connector
);
46 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
47 int link_rate
, u8 lane_count
,
49 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
50 int link_rate
, u8 lane_count
);
51 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
52 struct drm_modeset_acquire_ctx
*ctx
);
53 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
54 void intel_dp_sink_set_decompression_state(struct intel_dp
*intel_dp
,
55 const struct intel_crtc_state
*crtc_state
,
57 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
58 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
59 void intel_dp_encoder_flush_work(struct drm_encoder
*encoder
);
60 int intel_dp_compute_config(struct intel_encoder
*encoder
,
61 struct intel_crtc_state
*pipe_config
,
62 struct drm_connector_state
*conn_state
);
63 bool intel_dp_is_edp(struct intel_dp
*intel_dp
);
64 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
65 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
67 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
68 const struct drm_connector_state
*conn_state
);
69 void intel_edp_backlight_off(const struct drm_connector_state
*conn_state
);
70 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
71 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
72 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
73 void intel_dp_mst_suspend(struct drm_i915_private
*dev_priv
);
74 void intel_dp_mst_resume(struct drm_i915_private
*dev_priv
);
75 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
76 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
);
77 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
78 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
79 u32
intel_dp_pack_aux(const u8
*src
, int src_bytes
);
81 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
82 const struct intel_crtc_state
*crtc_state
);
83 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
84 const struct intel_crtc_state
*crtc_state
);
85 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
86 unsigned int frontbuffer_bits
);
87 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
88 unsigned int frontbuffer_bits
);
91 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
94 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
95 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
97 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
99 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, u8 voltage_swing
);
100 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
101 u8
*link_bw
, u8
*rate_select
);
102 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
103 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
);
105 intel_dp_get_link_status(struct intel_dp
*intel_dp
, u8
*link_status
);
107 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
108 bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
);
109 int intel_dp_link_required(int pixel_clock
, int bpp
);
110 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
111 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state
,
112 const struct drm_connector_state
*conn_state
);
113 void intel_dp_vsc_enable(struct intel_dp
*intel_dp
,
114 const struct intel_crtc_state
*crtc_state
,
115 const struct drm_connector_state
*conn_state
);
116 void intel_dp_hdr_metadata_enable(struct intel_dp
*intel_dp
,
117 const struct intel_crtc_state
*crtc_state
,
118 const struct drm_connector_state
*conn_state
);
119 bool intel_digital_port_connected(struct intel_encoder
*encoder
);
121 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
123 return ~((1 << lane_count
) - 1) & 0xf;
126 u32
intel_dp_mode_to_fec_clock(u32 mode_clock
);
128 #endif /* __INTEL_DP_H__ */