drivers/gpu/drm/i915/gt/debugfs_gt_pm.c

   1 // SPDX-License-Identifier: MIT
   2
   3 /*
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #include <linux/seq_file.h>
   8
   9 #include "debugfs_gt.h"
  10 #include "debugfs_gt_pm.h"
  11 #include "i915_drv.h"
  12 #include "intel_gt.h"
  13 #include "intel_llc.h"
  14 #include "intel_rc6.h"
  15 #include "intel_rps.h"
  16 #include "intel_runtime_pm.h"
  17 #include "intel_sideband.h"
  18 #include "intel_uncore.h"
  19
  20 static int fw_domains_show(struct seq_file *m, void *data)
  21 {
  22         struct intel_gt *gt = m->private;
  23         struct intel_uncore *uncore = gt->uncore;
  24         struct intel_uncore_forcewake_domain *fw_domain;
  25         unsigned int tmp;
  26
  27         seq_printf(m, "user.bypass_count = %u\n",
  28                    uncore->user_forcewake_count);
  29
  30         for_each_fw_domain(fw_domain, uncore, tmp)
  31                 seq_printf(m, "%s.wake_count = %u\n",
  32                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
  33                            READ_ONCE(fw_domain->wake_count));
  34
  35         return 0;
  36 }
  37 DEFINE_GT_DEBUGFS_ATTRIBUTE(fw_domains);
  38
  39 static void print_rc6_res(struct seq_file *m,
  40                           const char *title,
  41                           const i915_reg_t reg)
  42 {
  43         struct intel_gt *gt = m->private;
  44         intel_wakeref_t wakeref;
  45
  46         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
  47                 seq_printf(m, "%s %u (%llu us)\n", title,
  48                            intel_uncore_read(gt->uncore, reg),
  49                            intel_rc6_residency_us(&gt->rc6, reg));
  50 }
  51
  52 static int vlv_drpc(struct seq_file *m)
  53 {
  54         struct intel_gt *gt = m->private;
  55         struct intel_uncore *uncore = gt->uncore;
  56         u32 rcctl1, pw_status;
  57
  58         pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
  59         rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
  60
  61         seq_printf(m, "RC6 Enabled: %s\n",
  62                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
  63                                         GEN6_RC_CTL_EI_MODE(1))));
  64         seq_printf(m, "Render Power Well: %s\n",
  65                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
  66         seq_printf(m, "Media Power Well: %s\n",
  67                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
  68
  69         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
  70         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
  71
  72         return fw_domains_show(m, NULL);
  73 }
  74
  75 static int gen6_drpc(struct seq_file *m)
  76 {
  77         struct intel_gt *gt = m->private;
  78         struct drm_i915_private *i915 = gt->i915;
  79         struct intel_uncore *uncore = gt->uncore;
  80         u32 gt_core_status, rcctl1, rc6vids = 0;
  81         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
  82
  83         gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
  84
  85         rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
  86         if (INTEL_GEN(i915) >= 9) {
  87                 gen9_powergate_enable =
  88                         intel_uncore_read(uncore, GEN9_PG_ENABLE);
  89                 gen9_powergate_status =
  90                         intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
  91         }
  92
  93         if (INTEL_GEN(i915) <= 7)
  94                 sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
  95                                        &rc6vids, NULL);
  96
  97         seq_printf(m, "RC1e Enabled: %s\n",
  98                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  99         seq_printf(m, "RC6 Enabled: %s\n",
 100                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
 101         if (INTEL_GEN(i915) >= 9) {
 102                 seq_printf(m, "Render Well Gating Enabled: %s\n",
 103                            yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
 104                 seq_printf(m, "Media Well Gating Enabled: %s\n",
 105                            yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
 106         }
 107         seq_printf(m, "Deep RC6 Enabled: %s\n",
 108                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
 109         seq_printf(m, "Deepest RC6 Enabled: %s\n",
 110                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
 111         seq_puts(m, "Current RC state: ");
 112         switch (gt_core_status & GEN6_RCn_MASK) {
 113         case GEN6_RC0:
 114                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
 115                         seq_puts(m, "Core Power Down\n");
 116                 else
 117                         seq_puts(m, "on\n");
 118                 break;
 119         case GEN6_RC3:
 120                 seq_puts(m, "RC3\n");
 121                 break;
 122         case GEN6_RC6:
 123                 seq_puts(m, "RC6\n");
 124                 break;
 125         case GEN6_RC7:
 126                 seq_puts(m, "RC7\n");
 127                 break;
 128         default:
 129                 seq_puts(m, "Unknown\n");
 130                 break;
 131         }
 132
 133         seq_printf(m, "Core Power Down: %s\n",
 134                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
 135         if (INTEL_GEN(i915) >= 9) {
 136                 seq_printf(m, "Render Power Well: %s\n",
 137                            (gen9_powergate_status &
 138                             GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
 139                 seq_printf(m, "Media Power Well: %s\n",
 140                            (gen9_powergate_status &
 141                             GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
 142         }
 143
 144         /* Not exactly sure what this is */
 145         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
 146                       GEN6_GT_GFX_RC6_LOCKED);
 147         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
 148         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
 149         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
 150
 151         if (INTEL_GEN(i915) <= 7) {
 152                 seq_printf(m, "RC6   voltage: %dmV\n",
 153                            GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
 154                 seq_printf(m, "RC6+  voltage: %dmV\n",
 155                            GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
 156                 seq_printf(m, "RC6++ voltage: %dmV\n",
 157                            GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
 158         }
 159
 160         return fw_domains_show(m, NULL);
 161 }
 162
 163 static int ilk_drpc(struct seq_file *m)
 164 {
 165         struct intel_gt *gt = m->private;
 166         struct intel_uncore *uncore = gt->uncore;
 167         u32 rgvmodectl, rstdbyctl;
 168         u16 crstandvid;
 169
 170         rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
 171         rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
 172         crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
 173
 174         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
 175         seq_printf(m, "Boost freq: %d\n",
 176                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 177                    MEMMODE_BOOST_FREQ_SHIFT);
 178         seq_printf(m, "HW control enabled: %s\n",
 179                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
 180         seq_printf(m, "SW control enabled: %s\n",
 181                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
 182         seq_printf(m, "Gated voltage change: %s\n",
 183                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
 184         seq_printf(m, "Starting frequency: P%d\n",
 185                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 186         seq_printf(m, "Max P-state: P%d\n",
 187                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 188         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 189         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 190         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 191         seq_printf(m, "Render standby enabled: %s\n",
 192                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
 193         seq_puts(m, "Current RS state: ");
 194         switch (rstdbyctl & RSX_STATUS_MASK) {
 195         case RSX_STATUS_ON:
 196                 seq_puts(m, "on\n");
 197                 break;
 198         case RSX_STATUS_RC1:
 199                 seq_puts(m, "RC1\n");
 200                 break;
 201         case RSX_STATUS_RC1E:
 202                 seq_puts(m, "RC1E\n");
 203                 break;
 204         case RSX_STATUS_RS1:
 205                 seq_puts(m, "RS1\n");
 206                 break;
 207         case RSX_STATUS_RS2:
 208                 seq_puts(m, "RS2 (RC6)\n");
 209                 break;
 210         case RSX_STATUS_RS3:
 211                 seq_puts(m, "RC3 (RC6+)\n");
 212                 break;
 213         default:
 214                 seq_puts(m, "unknown\n");
 215                 break;
 216         }
 217
 218         return 0;
 219 }
 220
 221 static int drpc_show(struct seq_file *m, void *unused)
 222 {
 223         struct intel_gt *gt = m->private;
 224         struct drm_i915_private *i915 = gt->i915;
 225         intel_wakeref_t wakeref;
 226         int err = -ENODEV;
 227
 228         with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
 229                 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 230                         err = vlv_drpc(m);
 231                 else if (INTEL_GEN(i915) >= 6)
 232                         err = gen6_drpc(m);
 233                 else
 234                         err = ilk_drpc(m);
 235         }
 236
 237         return err;
 238 }
 239 DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
 240
 241 static int frequency_show(struct seq_file *m, void *unused)
 242 {
 243         struct intel_gt *gt = m->private;
 244         struct drm_i915_private *i915 = gt->i915;
 245         struct intel_uncore *uncore = gt->uncore;
 246         struct intel_rps *rps = &gt->rps;
 247         intel_wakeref_t wakeref;
 248
 249         wakeref = intel_runtime_pm_get(uncore->rpm);
 250
 251         if (IS_GEN(i915, 5)) {
 252                 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 253                 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
 254
 255                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 256                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 257                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 258                            MEMSTAT_VID_SHIFT);
 259                 seq_printf(m, "Current P-state: %d\n",
 260                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 261         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 262                 u32 rpmodectl, freq_sts;
 263
 264                 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
 265                 seq_printf(m, "Video Turbo Mode: %s\n",
 266                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 267                 seq_printf(m, "HW control enabled: %s\n",
 268                            yesno(rpmodectl & GEN6_RP_ENABLE));
 269                 seq_printf(m, "SW control enabled: %s\n",
 270                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 271                                   GEN6_RP_MEDIA_SW_MODE));
 272
 273                 vlv_punit_get(i915);
 274                 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
 275                 vlv_punit_put(i915);
 276
 277                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 278                 seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
 279
 280                 seq_printf(m, "actual GPU freq: %d MHz\n",
 281                            intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
 282
 283                 seq_printf(m, "current GPU freq: %d MHz\n",
 284                            intel_gpu_freq(rps, rps->cur_freq));
 285
 286                 seq_printf(m, "max GPU freq: %d MHz\n",
 287                            intel_gpu_freq(rps, rps->max_freq));
 288
 289                 seq_printf(m, "min GPU freq: %d MHz\n",
 290                            intel_gpu_freq(rps, rps->min_freq));
 291
 292                 seq_printf(m, "idle GPU freq: %d MHz\n",
 293                            intel_gpu_freq(rps, rps->idle_freq));
 294
 295                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
 296                            intel_gpu_freq(rps, rps->efficient_freq));
 297         } else if (INTEL_GEN(i915) >= 6) {
 298                 u32 rp_state_limits;
 299                 u32 gt_perf_status;
 300                 u32 rp_state_cap;
 301                 u32 rpmodectl, rpinclimit, rpdeclimit;
 302                 u32 rpstat, cagf, reqf;
 303                 u32 rpupei, rpcurup, rpprevup;
 304                 u32 rpdownei, rpcurdown, rpprevdown;
 305                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 306                 int max_freq;
 307
 308                 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
 309                 if (IS_GEN9_LP(i915)) {
 310                         rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
 311                         gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
 312                 } else {
 313                         rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
 314                         gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
 315                 }
 316
 317                 /* RPSTAT1 is in the GT power well */
 318                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 319
 320                 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
 321                 if (INTEL_GEN(i915) >= 9) {
 322                         reqf >>= 23;
 323                 } else {
 324                         reqf &= ~GEN6_TURBO_DISABLE;
 325                         if (IS_HASWELL(i915) || IS_BROADWELL(i915))
 326                                 reqf >>= 24;
 327                         else
 328                                 reqf >>= 25;
 329                 }
 330                 reqf = intel_gpu_freq(rps, reqf);
 331
 332                 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
 333                 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
 334                 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
 335
 336                 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
 337                 rpupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
 338                 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
 339                 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
 340                 rpdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 341                 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 342                 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
 343                 cagf = intel_rps_read_actual_frequency(rps);
 344
 345                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 346
 347                 if (INTEL_GEN(i915) >= 11) {
 348                         pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
 349                         pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
 350                         /*
 351                          * The equivalent to the PM ISR & IIR cannot be read
 352                          * without affecting the current state of the system
 353                          */
 354                         pm_isr = 0;
 355                         pm_iir = 0;
 356                 } else if (INTEL_GEN(i915) >= 8) {
 357                         pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
 358                         pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
 359                         pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
 360                         pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
 361                 } else {
 362                         pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
 363                         pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
 364                         pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
 365                         pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
 366                 }
 367                 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
 368
 369                 seq_printf(m, "Video Turbo Mode: %s\n",
 370                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 371                 seq_printf(m, "HW control enabled: %s\n",
 372                            yesno(rpmodectl & GEN6_RP_ENABLE));
 373                 seq_printf(m, "SW control enabled: %s\n",
 374                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 375                                   GEN6_RP_MEDIA_SW_MODE));
 376
 377                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
 378                            pm_ier, pm_imr, pm_mask);
 379                 if (INTEL_GEN(i915) <= 10)
 380                         seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
 381                                    pm_isr, pm_iir);
 382                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 383                            rps->pm_intrmsk_mbz);
 384                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 385                 seq_printf(m, "Render p-state ratio: %d\n",
 386                            (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
 387                 seq_printf(m, "Render p-state VID: %d\n",
 388                            gt_perf_status & 0xff);
 389                 seq_printf(m, "Render p-state limit: %d\n",
 390                            rp_state_limits & 0xff);
 391                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 392                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 393                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
 394                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
 395                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
 396                 seq_printf(m, "CAGF: %dMHz\n", cagf);
 397                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
 398                            rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
 399                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
 400                            rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
 401                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
 402                            rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
 403                 seq_printf(m, "Up threshold: %d%%\n",
 404                            rps->power.up_threshold);
 405
 406                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
 407                            rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
 408                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
 409                            rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
 410                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
 411                            rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
 412                 seq_printf(m, "Down threshold: %d%%\n",
 413                            rps->power.down_threshold);
 414
 415                 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
 416                             rp_state_cap >> 16) & 0xff;
 417                 max_freq *= (IS_GEN9_BC(i915) ||
 418                              INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
 419                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 420                            intel_gpu_freq(rps, max_freq));
 421
 422                 max_freq = (rp_state_cap & 0xff00) >> 8;
 423                 max_freq *= (IS_GEN9_BC(i915) ||
 424                              INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
 425                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 426                            intel_gpu_freq(rps, max_freq));
 427
 428                 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
 429                             rp_state_cap >> 0) & 0xff;
 430                 max_freq *= (IS_GEN9_BC(i915) ||
 431                              INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
 432                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 433                            intel_gpu_freq(rps, max_freq));
 434                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
 435                            intel_gpu_freq(rps, rps->max_freq));
 436
 437                 seq_printf(m, "Current freq: %d MHz\n",
 438                            intel_gpu_freq(rps, rps->cur_freq));
 439                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
 440                 seq_printf(m, "Idle freq: %d MHz\n",
 441                            intel_gpu_freq(rps, rps->idle_freq));
 442                 seq_printf(m, "Min freq: %d MHz\n",
 443                            intel_gpu_freq(rps, rps->min_freq));
 444                 seq_printf(m, "Boost freq: %d MHz\n",
 445                            intel_gpu_freq(rps, rps->boost_freq));
 446                 seq_printf(m, "Max freq: %d MHz\n",
 447                            intel_gpu_freq(rps, rps->max_freq));
 448                 seq_printf(m,
 449                            "efficient (RPe) frequency: %d MHz\n",
 450                            intel_gpu_freq(rps, rps->efficient_freq));
 451         } else {
 452                 seq_puts(m, "no P-state info available\n");
 453         }
 454
 455         seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
 456         seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
 457         seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
 458
 459         intel_runtime_pm_put(uncore->rpm, wakeref);
 460
 461         return 0;
 462 }
 463 DEFINE_GT_DEBUGFS_ATTRIBUTE(frequency);
 464
 465 static int llc_show(struct seq_file *m, void *data)
 466 {
 467         struct intel_gt *gt = m->private;
 468         struct drm_i915_private *i915 = gt->i915;
 469         const bool edram = INTEL_GEN(i915) > 8;
 470         struct intel_rps *rps = &gt->rps;
 471         unsigned int max_gpu_freq, min_gpu_freq;
 472         intel_wakeref_t wakeref;
 473         int gpu_freq, ia_freq;
 474
 475         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915)));
 476         seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
 477                    i915->edram_size_mb);
 478
 479         min_gpu_freq = rps->min_freq;
 480         max_gpu_freq = rps->max_freq;
 481         if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
 482                 /* Convert GT frequency to 50 HZ units */
 483                 min_gpu_freq /= GEN9_FREQ_SCALER;
 484                 max_gpu_freq /= GEN9_FREQ_SCALER;
 485         }
 486
 487         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
 488
 489         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 490         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
 491                 ia_freq = gpu_freq;
 492                 sandybridge_pcode_read(i915,
 493                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
 494                                        &ia_freq, NULL);
 495                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
 496                            intel_gpu_freq(rps,
 497                                           (gpu_freq *
 498                                            (IS_GEN9_BC(i915) ||
 499                                             INTEL_GEN(i915) >= 10 ?
 500                                             GEN9_FREQ_SCALER : 1))),
 501                            ((ia_freq >> 0) & 0xff) * 100,
 502                            ((ia_freq >> 8) & 0xff) * 100);
 503         }
 504         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 505
 506         return 0;
 507 }
 508
 509 static bool llc_eval(const struct intel_gt *gt)
 510 {
 511         return HAS_LLC(gt->i915);
 512 }
 513
 514 DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
 515
 516 static const char *rps_power_to_str(unsigned int power)
 517 {
 518         static const char * const strings[] = {
 519                 [LOW_POWER] = "low power",
 520                 [BETWEEN] = "mixed",
 521                 [HIGH_POWER] = "high power",
 522         };
 523
 524         if (power >= ARRAY_SIZE(strings) || !strings[power])
 525                 return "unknown";
 526
 527         return strings[power];
 528 }
 529
 530 static int rps_boost_show(struct seq_file *m, void *data)
 531 {
 532         struct intel_gt *gt = m->private;
 533         struct drm_i915_private *i915 = gt->i915;
 534         struct intel_rps *rps = &gt->rps;
 535
 536         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
 537         seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));
 538         seq_printf(m, "Boosts outstanding? %d\n",
 539                    atomic_read(&rps->num_waiters));
 540         seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
 541         seq_printf(m, "Frequency requested %d, actual %d\n",
 542                    intel_gpu_freq(rps, rps->cur_freq),
 543                    intel_rps_read_actual_frequency(rps));
 544         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
 545                    intel_gpu_freq(rps, rps->min_freq),
 546                    intel_gpu_freq(rps, rps->min_freq_softlimit),
 547                    intel_gpu_freq(rps, rps->max_freq_softlimit),
 548                    intel_gpu_freq(rps, rps->max_freq));
 549         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
 550                    intel_gpu_freq(rps, rps->idle_freq),
 551                    intel_gpu_freq(rps, rps->efficient_freq),
 552                    intel_gpu_freq(rps, rps->boost_freq));
 553
 554         seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
 555
 556         if (INTEL_GEN(i915) >= 6 && rps->enabled && gt->awake) {
 557                 struct intel_uncore *uncore = gt->uncore;
 558                 u32 rpup, rpupei;
 559                 u32 rpdown, rpdownei;
 560
 561                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 562                 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
 563                 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
 564                 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
 565                 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
 566                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 567
 568                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
 569                            rps_power_to_str(rps->power.mode));
 570                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
 571                            rpup && rpupei ? 100 * rpup / rpupei : 0,
 572                            rps->power.up_threshold);
 573                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
 574                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
 575                            rps->power.down_threshold);
 576         } else {
 577                 seq_puts(m, "\nRPS Autotuning inactive\n");
 578         }
 579
 580         return 0;
 581 }
 582
 583 static bool rps_eval(const struct intel_gt *gt)
 584 {
 585         return HAS_RPS(gt->i915);
 586 }
 587
 588 DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
 589
 590 void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
 591 {
 592         static const struct debugfs_gt_file files[] = {
 593                 { "drpc", &drpc_fops, NULL },
 594                 { "frequency", &frequency_fops, NULL },
 595                 { "forcewake", &fw_domains_fops, NULL },
 596                 { "llc", &llc_fops, llc_eval },
 597                 { "rps_boost", &rps_boost_fops, rps_eval },
 598         };
 599
 600         debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
 601 }