2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
28 #include <drm/drm_drv.h>
30 #include "display/intel_fbdev.h"
33 #include "i915_perf.h"
34 #include "i915_globals.h"
35 #include "i915_selftest.h"
37 #define PLATFORM(x) .platform = (x)
38 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
40 #define I845_PIPE_OFFSETS \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
48 #define I9XX_PIPE_OFFSETS \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 #define IVB_PIPE_OFFSETS \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
70 #define HSW_PIPE_OFFSETS \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
84 #define CHV_PIPE_OFFSETS \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
96 #define I845_CURSOR_OFFSETS \
98 [PIPE_A] = CURSOR_A_OFFSET, \
101 #define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
107 #define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
114 #define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
121 #define TGL_CURSOR_OFFSETS \
122 .cursor_offsets = { \
123 [PIPE_A] = CURSOR_A_OFFSET, \
124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
129 #define I9XX_COLORS \
130 .color = { .gamma_lut_size = 256 }
131 #define I965_COLORS \
132 .color = { .gamma_lut_size = 129, \
133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
136 .color = { .gamma_lut_size = 1024 }
138 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
140 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
141 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
145 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
147 DRM_COLOR_LUT_EQUAL_CHANNELS, \
150 /* Keep in gen based order, and chronological order within a gen */
152 #define GEN_DEFAULT_PAGE_SIZES \
153 .page_sizes = I915_GTT_PAGE_SIZE_4K
155 #define GEN_DEFAULT_REGIONS \
156 .memory_regions = REGION_SMEM | REGION_STOLEN
158 #define I830_FEATURES \
161 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
162 .display.has_overlay = 1, \
163 .display.cursor_needs_physical = 1, \
164 .display.overlay_needs_physical = 1, \
165 .display.has_gmch = 1, \
166 .gpu_reset_clobbers_display = true, \
167 .hws_needs_physical = 1, \
168 .unfenced_needs_alignment = 1, \
169 .engine_mask = BIT(RCS0), \
171 .has_coherent_ggtt = false, \
173 I9XX_CURSOR_OFFSETS, \
175 GEN_DEFAULT_PAGE_SIZES, \
178 #define I845_FEATURES \
180 .pipe_mask = BIT(PIPE_A), \
181 .display.has_overlay = 1, \
182 .display.overlay_needs_physical = 1, \
183 .display.has_gmch = 1, \
184 .gpu_reset_clobbers_display = true, \
185 .hws_needs_physical = 1, \
186 .unfenced_needs_alignment = 1, \
187 .engine_mask = BIT(RCS0), \
189 .has_coherent_ggtt = false, \
191 I845_CURSOR_OFFSETS, \
193 GEN_DEFAULT_PAGE_SIZES, \
196 static const struct intel_device_info i830_info
= {
198 PLATFORM(INTEL_I830
),
201 static const struct intel_device_info i845g_info
= {
203 PLATFORM(INTEL_I845G
),
206 static const struct intel_device_info i85x_info
= {
208 PLATFORM(INTEL_I85X
),
209 .display
.has_fbc
= 1,
212 static const struct intel_device_info i865g_info
= {
214 PLATFORM(INTEL_I865G
),
217 #define GEN3_FEATURES \
219 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
220 .display.has_gmch = 1, \
221 .gpu_reset_clobbers_display = true, \
222 .engine_mask = BIT(RCS0), \
224 .has_coherent_ggtt = true, \
226 I9XX_CURSOR_OFFSETS, \
228 GEN_DEFAULT_PAGE_SIZES, \
231 static const struct intel_device_info i915g_info
= {
233 PLATFORM(INTEL_I915G
),
234 .has_coherent_ggtt
= false,
235 .display
.cursor_needs_physical
= 1,
236 .display
.has_overlay
= 1,
237 .display
.overlay_needs_physical
= 1,
238 .hws_needs_physical
= 1,
239 .unfenced_needs_alignment
= 1,
242 static const struct intel_device_info i915gm_info
= {
244 PLATFORM(INTEL_I915GM
),
246 .display
.cursor_needs_physical
= 1,
247 .display
.has_overlay
= 1,
248 .display
.overlay_needs_physical
= 1,
249 .display
.supports_tv
= 1,
250 .display
.has_fbc
= 1,
251 .hws_needs_physical
= 1,
252 .unfenced_needs_alignment
= 1,
255 static const struct intel_device_info i945g_info
= {
257 PLATFORM(INTEL_I945G
),
258 .display
.has_hotplug
= 1,
259 .display
.cursor_needs_physical
= 1,
260 .display
.has_overlay
= 1,
261 .display
.overlay_needs_physical
= 1,
262 .hws_needs_physical
= 1,
263 .unfenced_needs_alignment
= 1,
266 static const struct intel_device_info i945gm_info
= {
268 PLATFORM(INTEL_I945GM
),
270 .display
.has_hotplug
= 1,
271 .display
.cursor_needs_physical
= 1,
272 .display
.has_overlay
= 1,
273 .display
.overlay_needs_physical
= 1,
274 .display
.supports_tv
= 1,
275 .display
.has_fbc
= 1,
276 .hws_needs_physical
= 1,
277 .unfenced_needs_alignment
= 1,
280 static const struct intel_device_info g33_info
= {
283 .display
.has_hotplug
= 1,
284 .display
.has_overlay
= 1,
287 static const struct intel_device_info pnv_g_info
= {
289 PLATFORM(INTEL_PINEVIEW
),
290 .display
.has_hotplug
= 1,
291 .display
.has_overlay
= 1,
294 static const struct intel_device_info pnv_m_info
= {
296 PLATFORM(INTEL_PINEVIEW
),
298 .display
.has_hotplug
= 1,
299 .display
.has_overlay
= 1,
302 #define GEN4_FEATURES \
304 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
305 .display.has_hotplug = 1, \
306 .display.has_gmch = 1, \
307 .gpu_reset_clobbers_display = true, \
308 .engine_mask = BIT(RCS0), \
310 .has_coherent_ggtt = true, \
312 I9XX_CURSOR_OFFSETS, \
314 GEN_DEFAULT_PAGE_SIZES, \
317 static const struct intel_device_info i965g_info
= {
319 PLATFORM(INTEL_I965G
),
320 .display
.has_overlay
= 1,
321 .hws_needs_physical
= 1,
325 static const struct intel_device_info i965gm_info
= {
327 PLATFORM(INTEL_I965GM
),
329 .display
.has_fbc
= 1,
330 .display
.has_overlay
= 1,
331 .display
.supports_tv
= 1,
332 .hws_needs_physical
= 1,
336 static const struct intel_device_info g45_info
= {
339 .engine_mask
= BIT(RCS0
) | BIT(VCS0
),
340 .gpu_reset_clobbers_display
= false,
343 static const struct intel_device_info gm45_info
= {
345 PLATFORM(INTEL_GM45
),
347 .display
.has_fbc
= 1,
348 .display
.supports_tv
= 1,
349 .engine_mask
= BIT(RCS0
) | BIT(VCS0
),
350 .gpu_reset_clobbers_display
= false,
353 #define GEN5_FEATURES \
355 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
356 .display.has_hotplug = 1, \
357 .engine_mask = BIT(RCS0) | BIT(VCS0), \
359 .has_coherent_ggtt = true, \
360 /* ilk does support rc6, but we do not implement [power] contexts */ \
363 I9XX_CURSOR_OFFSETS, \
365 GEN_DEFAULT_PAGE_SIZES, \
368 static const struct intel_device_info ilk_d_info
= {
370 PLATFORM(INTEL_IRONLAKE
),
373 static const struct intel_device_info ilk_m_info
= {
375 PLATFORM(INTEL_IRONLAKE
),
377 .display
.has_fbc
= 1,
380 #define GEN6_FEATURES \
382 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
383 .display.has_hotplug = 1, \
384 .display.has_fbc = 1, \
385 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
386 .has_coherent_ggtt = true, \
391 .ppgtt_type = INTEL_PPGTT_ALIASING, \
394 I9XX_CURSOR_OFFSETS, \
396 GEN_DEFAULT_PAGE_SIZES, \
399 #define SNB_D_PLATFORM \
401 PLATFORM(INTEL_SANDYBRIDGE)
403 static const struct intel_device_info snb_d_gt1_info
= {
408 static const struct intel_device_info snb_d_gt2_info
= {
413 #define SNB_M_PLATFORM \
415 PLATFORM(INTEL_SANDYBRIDGE), \
419 static const struct intel_device_info snb_m_gt1_info
= {
424 static const struct intel_device_info snb_m_gt2_info
= {
429 #define GEN7_FEATURES \
431 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
432 .display.has_hotplug = 1, \
433 .display.has_fbc = 1, \
434 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
435 .has_coherent_ggtt = true, \
440 .ppgtt_type = INTEL_PPGTT_FULL, \
443 IVB_CURSOR_OFFSETS, \
445 GEN_DEFAULT_PAGE_SIZES, \
448 #define IVB_D_PLATFORM \
450 PLATFORM(INTEL_IVYBRIDGE), \
453 static const struct intel_device_info ivb_d_gt1_info
= {
458 static const struct intel_device_info ivb_d_gt2_info
= {
463 #define IVB_M_PLATFORM \
465 PLATFORM(INTEL_IVYBRIDGE), \
469 static const struct intel_device_info ivb_m_gt1_info
= {
474 static const struct intel_device_info ivb_m_gt2_info
= {
479 static const struct intel_device_info ivb_q_info
= {
481 PLATFORM(INTEL_IVYBRIDGE
),
483 .pipe_mask
= 0, /* legal, last one wins */
487 static const struct intel_device_info vlv_info
= {
488 PLATFORM(INTEL_VALLEYVIEW
),
491 .pipe_mask
= BIT(PIPE_A
) | BIT(PIPE_B
),
495 .display
.has_gmch
= 1,
496 .display
.has_hotplug
= 1,
497 .ppgtt_type
= INTEL_PPGTT_FULL
,
500 .has_coherent_ggtt
= false,
501 .engine_mask
= BIT(RCS0
) | BIT(VCS0
) | BIT(BCS0
),
502 .display_mmio_offset
= VLV_DISPLAY_BASE
,
506 GEN_DEFAULT_PAGE_SIZES
,
510 #define G75_FEATURES \
512 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
513 .display.has_ddi = 1, \
515 .display.has_psr = 1, \
516 .display.has_dp_mst = 1, \
517 .has_rc6p = 0 /* RC6p removed-by HSW */, \
521 #define HSW_PLATFORM \
523 PLATFORM(INTEL_HASWELL), \
526 static const struct intel_device_info hsw_gt1_info
= {
531 static const struct intel_device_info hsw_gt2_info
= {
536 static const struct intel_device_info hsw_gt3_info
= {
541 #define GEN8_FEATURES \
544 .has_logical_ring_contexts = 1, \
545 .ppgtt_type = INTEL_PPGTT_FULL, \
547 .has_64bit_reloc = 1, \
548 .has_reset_engine = 1
550 #define BDW_PLATFORM \
552 PLATFORM(INTEL_BROADWELL)
554 static const struct intel_device_info bdw_gt1_info
= {
559 static const struct intel_device_info bdw_gt2_info
= {
564 static const struct intel_device_info bdw_rsvd_info
= {
567 /* According to the device ID those devices are GT3, they were
568 * previously treated as not GT3, keep it like that.
572 static const struct intel_device_info bdw_gt3_info
= {
576 BIT(RCS0
) | BIT(VCS0
) | BIT(BCS0
) | BIT(VECS0
) | BIT(VCS1
),
579 static const struct intel_device_info chv_info
= {
580 PLATFORM(INTEL_CHERRYVIEW
),
582 .pipe_mask
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
),
583 .display
.has_hotplug
= 1,
585 .engine_mask
= BIT(RCS0
) | BIT(VCS0
) | BIT(BCS0
) | BIT(VECS0
),
586 .has_64bit_reloc
= 1,
590 .has_logical_ring_contexts
= 1,
591 .display
.has_gmch
= 1,
592 .ppgtt_type
= INTEL_PPGTT_ALIASING
,
594 .has_reset_engine
= 1,
596 .has_coherent_ggtt
= false,
597 .display_mmio_offset
= VLV_DISPLAY_BASE
,
601 GEN_DEFAULT_PAGE_SIZES
,
605 #define GEN9_DEFAULT_PAGE_SIZES \
606 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
607 I915_GTT_PAGE_SIZE_64K
609 #define GEN9_FEATURES \
612 GEN9_DEFAULT_PAGE_SIZES, \
613 .has_logical_ring_preemption = 1, \
614 .display.has_csr = 1, \
616 .display.has_hdcp = 1, \
617 .display.has_ipc = 1, \
620 #define SKL_PLATFORM \
622 PLATFORM(INTEL_SKYLAKE)
624 static const struct intel_device_info skl_gt1_info
= {
629 static const struct intel_device_info skl_gt2_info
= {
634 #define SKL_GT3_PLUS_PLATFORM \
637 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
640 static const struct intel_device_info skl_gt3_info
= {
641 SKL_GT3_PLUS_PLATFORM
,
645 static const struct intel_device_info skl_gt4_info
= {
646 SKL_GT3_PLUS_PLATFORM
,
650 #define GEN9_LP_FEATURES \
653 .display.has_hotplug = 1, \
654 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
655 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
656 .has_64bit_reloc = 1, \
657 .display.has_ddi = 1, \
659 .display.has_fbc = 1, \
660 .display.has_hdcp = 1, \
661 .display.has_psr = 1, \
662 .has_runtime_pm = 1, \
663 .display.has_csr = 1, \
666 .display.has_dp_mst = 1, \
667 .has_logical_ring_contexts = 1, \
668 .has_logical_ring_preemption = 1, \
670 .ppgtt_type = INTEL_PPGTT_FULL, \
672 .has_reset_engine = 1, \
674 .has_coherent_ggtt = false, \
675 .display.has_ipc = 1, \
677 IVB_CURSOR_OFFSETS, \
679 GEN9_DEFAULT_PAGE_SIZES, \
682 static const struct intel_device_info bxt_info
= {
684 PLATFORM(INTEL_BROXTON
),
688 static const struct intel_device_info glk_info
= {
690 PLATFORM(INTEL_GEMINILAKE
),
695 #define KBL_PLATFORM \
697 PLATFORM(INTEL_KABYLAKE)
699 static const struct intel_device_info kbl_gt1_info
= {
704 static const struct intel_device_info kbl_gt2_info
= {
709 static const struct intel_device_info kbl_gt3_info
= {
713 BIT(RCS0
) | BIT(VCS0
) | BIT(BCS0
) | BIT(VECS0
) | BIT(VCS1
),
716 #define CFL_PLATFORM \
718 PLATFORM(INTEL_COFFEELAKE)
720 static const struct intel_device_info cfl_gt1_info
= {
725 static const struct intel_device_info cfl_gt2_info
= {
730 static const struct intel_device_info cfl_gt3_info
= {
734 BIT(RCS0
) | BIT(VCS0
) | BIT(BCS0
) | BIT(VECS0
) | BIT(VCS1
),
737 #define GEN10_FEATURES \
741 .display.has_dsc = 1, \
742 .has_coherent_ggtt = false, \
745 static const struct intel_device_info cnl_info
= {
747 PLATFORM(INTEL_CANNONLAKE
),
751 #define GEN11_DEFAULT_PAGE_SIZES \
752 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
753 I915_GTT_PAGE_SIZE_64K | \
754 I915_GTT_PAGE_SIZE_2M
756 #define GEN11_FEATURES \
758 GEN11_DEFAULT_PAGE_SIZES, \
760 [TRANSCODER_A] = PIPE_A_OFFSET, \
761 [TRANSCODER_B] = PIPE_B_OFFSET, \
762 [TRANSCODER_C] = PIPE_C_OFFSET, \
763 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
764 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
765 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
768 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
769 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
770 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
771 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
772 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
773 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
777 .has_logical_ring_elsq = 1, \
778 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
780 static const struct intel_device_info icl_info
= {
782 PLATFORM(INTEL_ICELAKE
),
784 BIT(RCS0
) | BIT(BCS0
) | BIT(VECS0
) | BIT(VCS0
) | BIT(VCS2
),
787 static const struct intel_device_info ehl_info
= {
789 PLATFORM(INTEL_ELKHARTLAKE
),
790 .require_force_probe
= 1,
791 .engine_mask
= BIT(RCS0
) | BIT(BCS0
) | BIT(VCS0
) | BIT(VECS0
),
795 #define GEN12_FEATURES \
799 [TRANSCODER_A] = PIPE_A_OFFSET, \
800 [TRANSCODER_B] = PIPE_B_OFFSET, \
801 [TRANSCODER_C] = PIPE_C_OFFSET, \
802 [TRANSCODER_D] = PIPE_D_OFFSET, \
803 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
804 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
807 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
808 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
809 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
810 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
811 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
812 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
814 TGL_CURSOR_OFFSETS, \
815 .has_global_mocs = 1, \
818 static const struct intel_device_info tgl_info
= {
820 PLATFORM(INTEL_TIGERLAKE
),
821 .pipe_mask
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
822 .require_force_probe
= 1,
823 .display
.has_modular_fia
= 1,
825 BIT(RCS0
) | BIT(BCS0
) | BIT(VECS0
) | BIT(VCS0
) | BIT(VCS2
),
826 .has_rps
= false, /* XXX disabled for debugging */
829 #define GEN12_DGFX_FEATURES \
837 * Make sure any device matches here are from most specific to most
838 * general. For example, since the Quanta match is based on the subsystem
839 * and subvendor IDs, we need it to come before the more general IVB
840 * PCI ID matches, otherwise we'll use the wrong info struct above.
842 static const struct pci_device_id pciidlist
[] = {
843 INTEL_I830_IDS(&i830_info
),
844 INTEL_I845G_IDS(&i845g_info
),
845 INTEL_I85X_IDS(&i85x_info
),
846 INTEL_I865G_IDS(&i865g_info
),
847 INTEL_I915G_IDS(&i915g_info
),
848 INTEL_I915GM_IDS(&i915gm_info
),
849 INTEL_I945G_IDS(&i945g_info
),
850 INTEL_I945GM_IDS(&i945gm_info
),
851 INTEL_I965G_IDS(&i965g_info
),
852 INTEL_G33_IDS(&g33_info
),
853 INTEL_I965GM_IDS(&i965gm_info
),
854 INTEL_GM45_IDS(&gm45_info
),
855 INTEL_G45_IDS(&g45_info
),
856 INTEL_PINEVIEW_G_IDS(&pnv_g_info
),
857 INTEL_PINEVIEW_M_IDS(&pnv_m_info
),
858 INTEL_IRONLAKE_D_IDS(&ilk_d_info
),
859 INTEL_IRONLAKE_M_IDS(&ilk_m_info
),
860 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info
),
861 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info
),
862 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info
),
863 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info
),
864 INTEL_IVB_Q_IDS(&ivb_q_info
), /* must be first IVB */
865 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info
),
866 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info
),
867 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info
),
868 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info
),
869 INTEL_HSW_GT1_IDS(&hsw_gt1_info
),
870 INTEL_HSW_GT2_IDS(&hsw_gt2_info
),
871 INTEL_HSW_GT3_IDS(&hsw_gt3_info
),
872 INTEL_VLV_IDS(&vlv_info
),
873 INTEL_BDW_GT1_IDS(&bdw_gt1_info
),
874 INTEL_BDW_GT2_IDS(&bdw_gt2_info
),
875 INTEL_BDW_GT3_IDS(&bdw_gt3_info
),
876 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info
),
877 INTEL_CHV_IDS(&chv_info
),
878 INTEL_SKL_GT1_IDS(&skl_gt1_info
),
879 INTEL_SKL_GT2_IDS(&skl_gt2_info
),
880 INTEL_SKL_GT3_IDS(&skl_gt3_info
),
881 INTEL_SKL_GT4_IDS(&skl_gt4_info
),
882 INTEL_BXT_IDS(&bxt_info
),
883 INTEL_GLK_IDS(&glk_info
),
884 INTEL_KBL_GT1_IDS(&kbl_gt1_info
),
885 INTEL_KBL_GT2_IDS(&kbl_gt2_info
),
886 INTEL_KBL_GT3_IDS(&kbl_gt3_info
),
887 INTEL_KBL_GT4_IDS(&kbl_gt3_info
),
888 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info
),
889 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info
),
890 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info
),
891 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info
),
892 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info
),
893 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info
),
894 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info
),
895 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info
),
896 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info
),
897 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info
),
898 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info
),
899 INTEL_CML_GT1_IDS(&cfl_gt1_info
),
900 INTEL_CML_GT2_IDS(&cfl_gt2_info
),
901 INTEL_CML_U_GT1_IDS(&cfl_gt1_info
),
902 INTEL_CML_U_GT2_IDS(&cfl_gt2_info
),
903 INTEL_CNL_IDS(&cnl_info
),
904 INTEL_ICL_11_IDS(&icl_info
),
905 INTEL_EHL_IDS(&ehl_info
),
906 INTEL_TGL_12_IDS(&tgl_info
),
909 MODULE_DEVICE_TABLE(pci
, pciidlist
);
911 static void i915_pci_remove(struct pci_dev
*pdev
)
913 struct drm_i915_private
*i915
;
915 i915
= pci_get_drvdata(pdev
);
916 if (!i915
) /* driver load aborted, nothing to cleanup */
919 i915_driver_remove(i915
);
920 pci_set_drvdata(pdev
, NULL
);
922 drm_dev_put(&i915
->drm
);
925 /* is device_id present in comma separated list of ids */
926 static bool force_probe(u16 device_id
, const char *devices
)
931 /* FIXME: transitional */
932 if (i915_modparams
.alpha_support
) {
933 DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
938 if (!devices
|| !*devices
)
941 /* match everything */
942 if (strcmp(devices
, "*") == 0)
945 s
= kstrdup(devices
, GFP_KERNEL
);
949 for (p
= s
, ret
= false; (tok
= strsep(&p
, ",")) != NULL
; ) {
952 if (kstrtou16(tok
, 16, &val
) == 0 && val
== device_id
) {
963 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
965 struct intel_device_info
*intel_info
=
966 (struct intel_device_info
*) ent
->driver_data
;
969 if (intel_info
->require_force_probe
&&
970 !force_probe(pdev
->device
, i915_modparams
.force_probe
)) {
971 DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
972 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
973 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
974 "or (recommended) check for kernel updates.\n",
975 pdev
->device
, pdev
->device
, pdev
->device
);
979 /* Only bind to function 0 of the device. Early generations
980 * used function 1 as a placeholder for multi-head. This causes
981 * us confusion instead, especially on the systems where both
982 * functions have the same PCI-ID!
984 if (PCI_FUNC(pdev
->devfn
))
988 * apple-gmux is needed on dual GPU MacBook Pro
989 * to probe the panel if we're the inactive GPU.
991 if (vga_switcheroo_client_probe_defer(pdev
))
992 return -EPROBE_DEFER
;
994 err
= i915_driver_probe(pdev
, ent
);
998 if (i915_inject_probe_failure(pci_get_drvdata(pdev
))) {
999 i915_pci_remove(pdev
);
1003 err
= i915_live_selftests(pdev
);
1005 i915_pci_remove(pdev
);
1006 return err
> 0 ? -ENOTTY
: err
;
1009 err
= i915_perf_selftests(pdev
);
1011 i915_pci_remove(pdev
);
1012 return err
> 0 ? -ENOTTY
: err
;
1018 static struct pci_driver i915_pci_driver
= {
1019 .name
= DRIVER_NAME
,
1020 .id_table
= pciidlist
,
1021 .probe
= i915_pci_probe
,
1022 .remove
= i915_pci_remove
,
1023 .driver
.pm
= &i915_pm_ops
,
1026 static int __init
i915_init(void)
1028 bool use_kms
= true;
1031 err
= i915_globals_init();
1035 err
= i915_mock_selftests();
1037 return err
> 0 ? 0 : err
;
1040 * Enable KMS by default, unless explicitly overriden by
1041 * either the i915.modeset prarameter or by the
1042 * vga_text_mode_force boot option.
1045 if (i915_modparams
.modeset
== 0)
1048 if (vgacon_text_force() && i915_modparams
.modeset
== -1)
1052 /* Silently fail loading to not upset userspace. */
1053 DRM_DEBUG_DRIVER("KMS disabled.\n");
1057 err
= pci_register_driver(&i915_pci_driver
);
1061 i915_perf_sysctl_register();
1065 static void __exit
i915_exit(void)
1067 if (!i915_pci_driver
.driver
.owner
)
1070 i915_perf_sysctl_unregister();
1071 pci_unregister_driver(&i915_pci_driver
);
1072 i915_globals_exit();
1075 module_init(i915_init
);
1076 module_exit(i915_exit
);
1078 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1079 MODULE_AUTHOR("Intel Corporation");
1081 MODULE_DESCRIPTION(DRIVER_DESC
);
1082 MODULE_LICENSE("GPL and additional rights");