treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_pci.c
blob83f01401b8b5c5758dea58f7c8ed5dcf6c22c21c
1 /*
2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
28 #include <drm/drm_drv.h>
30 #include "display/intel_fbdev.h"
32 #include "i915_drv.h"
33 #include "i915_perf.h"
34 #include "i915_globals.h"
35 #include "i915_selftest.h"
37 #define PLATFORM(x) .platform = (x)
38 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
40 #define I845_PIPE_OFFSETS \
41 .pipe_offsets = { \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
43 }, \
44 .trans_offsets = { \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
48 #define I9XX_PIPE_OFFSETS \
49 .pipe_offsets = { \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
52 }, \
53 .trans_offsets = { \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 #define IVB_PIPE_OFFSETS \
59 .pipe_offsets = { \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
63 }, \
64 .trans_offsets = { \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
70 #define HSW_PIPE_OFFSETS \
71 .pipe_offsets = { \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
76 }, \
77 .trans_offsets = { \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
84 #define CHV_PIPE_OFFSETS \
85 .pipe_offsets = { \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
89 }, \
90 .trans_offsets = { \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
96 #define I845_CURSOR_OFFSETS \
97 .cursor_offsets = { \
98 [PIPE_A] = CURSOR_A_OFFSET, \
101 #define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
107 #define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
114 #define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
121 #define TGL_CURSOR_OFFSETS \
122 .cursor_offsets = { \
123 [PIPE_A] = CURSOR_A_OFFSET, \
124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
129 #define I9XX_COLORS \
130 .color = { .gamma_lut_size = 256 }
131 #define I965_COLORS \
132 .color = { .gamma_lut_size = 129, \
133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135 #define ILK_COLORS \
136 .color = { .gamma_lut_size = 1024 }
137 #define IVB_COLORS \
138 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
139 #define CHV_COLORS \
140 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
141 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
144 #define GLK_COLORS \
145 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
147 DRM_COLOR_LUT_EQUAL_CHANNELS, \
150 /* Keep in gen based order, and chronological order within a gen */
152 #define GEN_DEFAULT_PAGE_SIZES \
153 .page_sizes = I915_GTT_PAGE_SIZE_4K
155 #define GEN_DEFAULT_REGIONS \
156 .memory_regions = REGION_SMEM | REGION_STOLEN
158 #define I830_FEATURES \
159 GEN(2), \
160 .is_mobile = 1, \
161 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
162 .display.has_overlay = 1, \
163 .display.cursor_needs_physical = 1, \
164 .display.overlay_needs_physical = 1, \
165 .display.has_gmch = 1, \
166 .gpu_reset_clobbers_display = true, \
167 .hws_needs_physical = 1, \
168 .unfenced_needs_alignment = 1, \
169 .engine_mask = BIT(RCS0), \
170 .has_snoop = true, \
171 .has_coherent_ggtt = false, \
172 I9XX_PIPE_OFFSETS, \
173 I9XX_CURSOR_OFFSETS, \
174 I9XX_COLORS, \
175 GEN_DEFAULT_PAGE_SIZES, \
176 GEN_DEFAULT_REGIONS
178 #define I845_FEATURES \
179 GEN(2), \
180 .pipe_mask = BIT(PIPE_A), \
181 .display.has_overlay = 1, \
182 .display.overlay_needs_physical = 1, \
183 .display.has_gmch = 1, \
184 .gpu_reset_clobbers_display = true, \
185 .hws_needs_physical = 1, \
186 .unfenced_needs_alignment = 1, \
187 .engine_mask = BIT(RCS0), \
188 .has_snoop = true, \
189 .has_coherent_ggtt = false, \
190 I845_PIPE_OFFSETS, \
191 I845_CURSOR_OFFSETS, \
192 I9XX_COLORS, \
193 GEN_DEFAULT_PAGE_SIZES, \
194 GEN_DEFAULT_REGIONS
196 static const struct intel_device_info i830_info = {
197 I830_FEATURES,
198 PLATFORM(INTEL_I830),
201 static const struct intel_device_info i845g_info = {
202 I845_FEATURES,
203 PLATFORM(INTEL_I845G),
206 static const struct intel_device_info i85x_info = {
207 I830_FEATURES,
208 PLATFORM(INTEL_I85X),
209 .display.has_fbc = 1,
212 static const struct intel_device_info i865g_info = {
213 I845_FEATURES,
214 PLATFORM(INTEL_I865G),
217 #define GEN3_FEATURES \
218 GEN(3), \
219 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
220 .display.has_gmch = 1, \
221 .gpu_reset_clobbers_display = true, \
222 .engine_mask = BIT(RCS0), \
223 .has_snoop = true, \
224 .has_coherent_ggtt = true, \
225 I9XX_PIPE_OFFSETS, \
226 I9XX_CURSOR_OFFSETS, \
227 I9XX_COLORS, \
228 GEN_DEFAULT_PAGE_SIZES, \
229 GEN_DEFAULT_REGIONS
231 static const struct intel_device_info i915g_info = {
232 GEN3_FEATURES,
233 PLATFORM(INTEL_I915G),
234 .has_coherent_ggtt = false,
235 .display.cursor_needs_physical = 1,
236 .display.has_overlay = 1,
237 .display.overlay_needs_physical = 1,
238 .hws_needs_physical = 1,
239 .unfenced_needs_alignment = 1,
242 static const struct intel_device_info i915gm_info = {
243 GEN3_FEATURES,
244 PLATFORM(INTEL_I915GM),
245 .is_mobile = 1,
246 .display.cursor_needs_physical = 1,
247 .display.has_overlay = 1,
248 .display.overlay_needs_physical = 1,
249 .display.supports_tv = 1,
250 .display.has_fbc = 1,
251 .hws_needs_physical = 1,
252 .unfenced_needs_alignment = 1,
255 static const struct intel_device_info i945g_info = {
256 GEN3_FEATURES,
257 PLATFORM(INTEL_I945G),
258 .display.has_hotplug = 1,
259 .display.cursor_needs_physical = 1,
260 .display.has_overlay = 1,
261 .display.overlay_needs_physical = 1,
262 .hws_needs_physical = 1,
263 .unfenced_needs_alignment = 1,
266 static const struct intel_device_info i945gm_info = {
267 GEN3_FEATURES,
268 PLATFORM(INTEL_I945GM),
269 .is_mobile = 1,
270 .display.has_hotplug = 1,
271 .display.cursor_needs_physical = 1,
272 .display.has_overlay = 1,
273 .display.overlay_needs_physical = 1,
274 .display.supports_tv = 1,
275 .display.has_fbc = 1,
276 .hws_needs_physical = 1,
277 .unfenced_needs_alignment = 1,
280 static const struct intel_device_info g33_info = {
281 GEN3_FEATURES,
282 PLATFORM(INTEL_G33),
283 .display.has_hotplug = 1,
284 .display.has_overlay = 1,
287 static const struct intel_device_info pnv_g_info = {
288 GEN3_FEATURES,
289 PLATFORM(INTEL_PINEVIEW),
290 .display.has_hotplug = 1,
291 .display.has_overlay = 1,
294 static const struct intel_device_info pnv_m_info = {
295 GEN3_FEATURES,
296 PLATFORM(INTEL_PINEVIEW),
297 .is_mobile = 1,
298 .display.has_hotplug = 1,
299 .display.has_overlay = 1,
302 #define GEN4_FEATURES \
303 GEN(4), \
304 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
305 .display.has_hotplug = 1, \
306 .display.has_gmch = 1, \
307 .gpu_reset_clobbers_display = true, \
308 .engine_mask = BIT(RCS0), \
309 .has_snoop = true, \
310 .has_coherent_ggtt = true, \
311 I9XX_PIPE_OFFSETS, \
312 I9XX_CURSOR_OFFSETS, \
313 I965_COLORS, \
314 GEN_DEFAULT_PAGE_SIZES, \
315 GEN_DEFAULT_REGIONS
317 static const struct intel_device_info i965g_info = {
318 GEN4_FEATURES,
319 PLATFORM(INTEL_I965G),
320 .display.has_overlay = 1,
321 .hws_needs_physical = 1,
322 .has_snoop = false,
325 static const struct intel_device_info i965gm_info = {
326 GEN4_FEATURES,
327 PLATFORM(INTEL_I965GM),
328 .is_mobile = 1,
329 .display.has_fbc = 1,
330 .display.has_overlay = 1,
331 .display.supports_tv = 1,
332 .hws_needs_physical = 1,
333 .has_snoop = false,
336 static const struct intel_device_info g45_info = {
337 GEN4_FEATURES,
338 PLATFORM(INTEL_G45),
339 .engine_mask = BIT(RCS0) | BIT(VCS0),
340 .gpu_reset_clobbers_display = false,
343 static const struct intel_device_info gm45_info = {
344 GEN4_FEATURES,
345 PLATFORM(INTEL_GM45),
346 .is_mobile = 1,
347 .display.has_fbc = 1,
348 .display.supports_tv = 1,
349 .engine_mask = BIT(RCS0) | BIT(VCS0),
350 .gpu_reset_clobbers_display = false,
353 #define GEN5_FEATURES \
354 GEN(5), \
355 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
356 .display.has_hotplug = 1, \
357 .engine_mask = BIT(RCS0) | BIT(VCS0), \
358 .has_snoop = true, \
359 .has_coherent_ggtt = true, \
360 /* ilk does support rc6, but we do not implement [power] contexts */ \
361 .has_rc6 = 0, \
362 I9XX_PIPE_OFFSETS, \
363 I9XX_CURSOR_OFFSETS, \
364 ILK_COLORS, \
365 GEN_DEFAULT_PAGE_SIZES, \
366 GEN_DEFAULT_REGIONS
368 static const struct intel_device_info ilk_d_info = {
369 GEN5_FEATURES,
370 PLATFORM(INTEL_IRONLAKE),
373 static const struct intel_device_info ilk_m_info = {
374 GEN5_FEATURES,
375 PLATFORM(INTEL_IRONLAKE),
376 .is_mobile = 1,
377 .display.has_fbc = 1,
380 #define GEN6_FEATURES \
381 GEN(6), \
382 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
383 .display.has_hotplug = 1, \
384 .display.has_fbc = 1, \
385 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
386 .has_coherent_ggtt = true, \
387 .has_llc = 1, \
388 .has_rc6 = 1, \
389 .has_rc6p = 1, \
390 .has_rps = true, \
391 .ppgtt_type = INTEL_PPGTT_ALIASING, \
392 .ppgtt_size = 31, \
393 I9XX_PIPE_OFFSETS, \
394 I9XX_CURSOR_OFFSETS, \
395 ILK_COLORS, \
396 GEN_DEFAULT_PAGE_SIZES, \
397 GEN_DEFAULT_REGIONS
399 #define SNB_D_PLATFORM \
400 GEN6_FEATURES, \
401 PLATFORM(INTEL_SANDYBRIDGE)
403 static const struct intel_device_info snb_d_gt1_info = {
404 SNB_D_PLATFORM,
405 .gt = 1,
408 static const struct intel_device_info snb_d_gt2_info = {
409 SNB_D_PLATFORM,
410 .gt = 2,
413 #define SNB_M_PLATFORM \
414 GEN6_FEATURES, \
415 PLATFORM(INTEL_SANDYBRIDGE), \
416 .is_mobile = 1
419 static const struct intel_device_info snb_m_gt1_info = {
420 SNB_M_PLATFORM,
421 .gt = 1,
424 static const struct intel_device_info snb_m_gt2_info = {
425 SNB_M_PLATFORM,
426 .gt = 2,
429 #define GEN7_FEATURES \
430 GEN(7), \
431 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
432 .display.has_hotplug = 1, \
433 .display.has_fbc = 1, \
434 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
435 .has_coherent_ggtt = true, \
436 .has_llc = 1, \
437 .has_rc6 = 1, \
438 .has_rc6p = 1, \
439 .has_rps = true, \
440 .ppgtt_type = INTEL_PPGTT_FULL, \
441 .ppgtt_size = 31, \
442 IVB_PIPE_OFFSETS, \
443 IVB_CURSOR_OFFSETS, \
444 IVB_COLORS, \
445 GEN_DEFAULT_PAGE_SIZES, \
446 GEN_DEFAULT_REGIONS
448 #define IVB_D_PLATFORM \
449 GEN7_FEATURES, \
450 PLATFORM(INTEL_IVYBRIDGE), \
451 .has_l3_dpf = 1
453 static const struct intel_device_info ivb_d_gt1_info = {
454 IVB_D_PLATFORM,
455 .gt = 1,
458 static const struct intel_device_info ivb_d_gt2_info = {
459 IVB_D_PLATFORM,
460 .gt = 2,
463 #define IVB_M_PLATFORM \
464 GEN7_FEATURES, \
465 PLATFORM(INTEL_IVYBRIDGE), \
466 .is_mobile = 1, \
467 .has_l3_dpf = 1
469 static const struct intel_device_info ivb_m_gt1_info = {
470 IVB_M_PLATFORM,
471 .gt = 1,
474 static const struct intel_device_info ivb_m_gt2_info = {
475 IVB_M_PLATFORM,
476 .gt = 2,
479 static const struct intel_device_info ivb_q_info = {
480 GEN7_FEATURES,
481 PLATFORM(INTEL_IVYBRIDGE),
482 .gt = 2,
483 .pipe_mask = 0, /* legal, last one wins */
484 .has_l3_dpf = 1,
487 static const struct intel_device_info vlv_info = {
488 PLATFORM(INTEL_VALLEYVIEW),
489 GEN(7),
490 .is_lp = 1,
491 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
492 .has_runtime_pm = 1,
493 .has_rc6 = 1,
494 .has_rps = true,
495 .display.has_gmch = 1,
496 .display.has_hotplug = 1,
497 .ppgtt_type = INTEL_PPGTT_FULL,
498 .ppgtt_size = 31,
499 .has_snoop = true,
500 .has_coherent_ggtt = false,
501 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
502 .display_mmio_offset = VLV_DISPLAY_BASE,
503 I9XX_PIPE_OFFSETS,
504 I9XX_CURSOR_OFFSETS,
505 I965_COLORS,
506 GEN_DEFAULT_PAGE_SIZES,
507 GEN_DEFAULT_REGIONS,
510 #define G75_FEATURES \
511 GEN7_FEATURES, \
512 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
513 .display.has_ddi = 1, \
514 .has_fpga_dbg = 1, \
515 .display.has_psr = 1, \
516 .display.has_dp_mst = 1, \
517 .has_rc6p = 0 /* RC6p removed-by HSW */, \
518 HSW_PIPE_OFFSETS, \
519 .has_runtime_pm = 1
521 #define HSW_PLATFORM \
522 G75_FEATURES, \
523 PLATFORM(INTEL_HASWELL), \
524 .has_l3_dpf = 1
526 static const struct intel_device_info hsw_gt1_info = {
527 HSW_PLATFORM,
528 .gt = 1,
531 static const struct intel_device_info hsw_gt2_info = {
532 HSW_PLATFORM,
533 .gt = 2,
536 static const struct intel_device_info hsw_gt3_info = {
537 HSW_PLATFORM,
538 .gt = 3,
541 #define GEN8_FEATURES \
542 G75_FEATURES, \
543 GEN(8), \
544 .has_logical_ring_contexts = 1, \
545 .ppgtt_type = INTEL_PPGTT_FULL, \
546 .ppgtt_size = 48, \
547 .has_64bit_reloc = 1, \
548 .has_reset_engine = 1
550 #define BDW_PLATFORM \
551 GEN8_FEATURES, \
552 PLATFORM(INTEL_BROADWELL)
554 static const struct intel_device_info bdw_gt1_info = {
555 BDW_PLATFORM,
556 .gt = 1,
559 static const struct intel_device_info bdw_gt2_info = {
560 BDW_PLATFORM,
561 .gt = 2,
564 static const struct intel_device_info bdw_rsvd_info = {
565 BDW_PLATFORM,
566 .gt = 3,
567 /* According to the device ID those devices are GT3, they were
568 * previously treated as not GT3, keep it like that.
572 static const struct intel_device_info bdw_gt3_info = {
573 BDW_PLATFORM,
574 .gt = 3,
575 .engine_mask =
576 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
579 static const struct intel_device_info chv_info = {
580 PLATFORM(INTEL_CHERRYVIEW),
581 GEN(8),
582 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
583 .display.has_hotplug = 1,
584 .is_lp = 1,
585 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
586 .has_64bit_reloc = 1,
587 .has_runtime_pm = 1,
588 .has_rc6 = 1,
589 .has_rps = true,
590 .has_logical_ring_contexts = 1,
591 .display.has_gmch = 1,
592 .ppgtt_type = INTEL_PPGTT_ALIASING,
593 .ppgtt_size = 32,
594 .has_reset_engine = 1,
595 .has_snoop = true,
596 .has_coherent_ggtt = false,
597 .display_mmio_offset = VLV_DISPLAY_BASE,
598 CHV_PIPE_OFFSETS,
599 CHV_CURSOR_OFFSETS,
600 CHV_COLORS,
601 GEN_DEFAULT_PAGE_SIZES,
602 GEN_DEFAULT_REGIONS,
605 #define GEN9_DEFAULT_PAGE_SIZES \
606 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
607 I915_GTT_PAGE_SIZE_64K
609 #define GEN9_FEATURES \
610 GEN8_FEATURES, \
611 GEN(9), \
612 GEN9_DEFAULT_PAGE_SIZES, \
613 .has_logical_ring_preemption = 1, \
614 .display.has_csr = 1, \
615 .has_gt_uc = 1, \
616 .display.has_hdcp = 1, \
617 .display.has_ipc = 1, \
618 .ddb_size = 896
620 #define SKL_PLATFORM \
621 GEN9_FEATURES, \
622 PLATFORM(INTEL_SKYLAKE)
624 static const struct intel_device_info skl_gt1_info = {
625 SKL_PLATFORM,
626 .gt = 1,
629 static const struct intel_device_info skl_gt2_info = {
630 SKL_PLATFORM,
631 .gt = 2,
634 #define SKL_GT3_PLUS_PLATFORM \
635 SKL_PLATFORM, \
636 .engine_mask = \
637 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
640 static const struct intel_device_info skl_gt3_info = {
641 SKL_GT3_PLUS_PLATFORM,
642 .gt = 3,
645 static const struct intel_device_info skl_gt4_info = {
646 SKL_GT3_PLUS_PLATFORM,
647 .gt = 4,
650 #define GEN9_LP_FEATURES \
651 GEN(9), \
652 .is_lp = 1, \
653 .display.has_hotplug = 1, \
654 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
655 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
656 .has_64bit_reloc = 1, \
657 .display.has_ddi = 1, \
658 .has_fpga_dbg = 1, \
659 .display.has_fbc = 1, \
660 .display.has_hdcp = 1, \
661 .display.has_psr = 1, \
662 .has_runtime_pm = 1, \
663 .display.has_csr = 1, \
664 .has_rc6 = 1, \
665 .has_rps = true, \
666 .display.has_dp_mst = 1, \
667 .has_logical_ring_contexts = 1, \
668 .has_logical_ring_preemption = 1, \
669 .has_gt_uc = 1, \
670 .ppgtt_type = INTEL_PPGTT_FULL, \
671 .ppgtt_size = 48, \
672 .has_reset_engine = 1, \
673 .has_snoop = true, \
674 .has_coherent_ggtt = false, \
675 .display.has_ipc = 1, \
676 HSW_PIPE_OFFSETS, \
677 IVB_CURSOR_OFFSETS, \
678 IVB_COLORS, \
679 GEN9_DEFAULT_PAGE_SIZES, \
680 GEN_DEFAULT_REGIONS
682 static const struct intel_device_info bxt_info = {
683 GEN9_LP_FEATURES,
684 PLATFORM(INTEL_BROXTON),
685 .ddb_size = 512,
688 static const struct intel_device_info glk_info = {
689 GEN9_LP_FEATURES,
690 PLATFORM(INTEL_GEMINILAKE),
691 .ddb_size = 1024,
692 GLK_COLORS,
695 #define KBL_PLATFORM \
696 GEN9_FEATURES, \
697 PLATFORM(INTEL_KABYLAKE)
699 static const struct intel_device_info kbl_gt1_info = {
700 KBL_PLATFORM,
701 .gt = 1,
704 static const struct intel_device_info kbl_gt2_info = {
705 KBL_PLATFORM,
706 .gt = 2,
709 static const struct intel_device_info kbl_gt3_info = {
710 KBL_PLATFORM,
711 .gt = 3,
712 .engine_mask =
713 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
716 #define CFL_PLATFORM \
717 GEN9_FEATURES, \
718 PLATFORM(INTEL_COFFEELAKE)
720 static const struct intel_device_info cfl_gt1_info = {
721 CFL_PLATFORM,
722 .gt = 1,
725 static const struct intel_device_info cfl_gt2_info = {
726 CFL_PLATFORM,
727 .gt = 2,
730 static const struct intel_device_info cfl_gt3_info = {
731 CFL_PLATFORM,
732 .gt = 3,
733 .engine_mask =
734 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
737 #define GEN10_FEATURES \
738 GEN9_FEATURES, \
739 GEN(10), \
740 .ddb_size = 1024, \
741 .display.has_dsc = 1, \
742 .has_coherent_ggtt = false, \
743 GLK_COLORS
745 static const struct intel_device_info cnl_info = {
746 GEN10_FEATURES,
747 PLATFORM(INTEL_CANNONLAKE),
748 .gt = 2,
751 #define GEN11_DEFAULT_PAGE_SIZES \
752 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
753 I915_GTT_PAGE_SIZE_64K | \
754 I915_GTT_PAGE_SIZE_2M
756 #define GEN11_FEATURES \
757 GEN10_FEATURES, \
758 GEN11_DEFAULT_PAGE_SIZES, \
759 .pipe_offsets = { \
760 [TRANSCODER_A] = PIPE_A_OFFSET, \
761 [TRANSCODER_B] = PIPE_B_OFFSET, \
762 [TRANSCODER_C] = PIPE_C_OFFSET, \
763 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
764 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
765 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
766 }, \
767 .trans_offsets = { \
768 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
769 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
770 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
771 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
772 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
773 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
774 }, \
775 GEN(11), \
776 .ddb_size = 2048, \
777 .has_logical_ring_elsq = 1, \
778 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
780 static const struct intel_device_info icl_info = {
781 GEN11_FEATURES,
782 PLATFORM(INTEL_ICELAKE),
783 .engine_mask =
784 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
787 static const struct intel_device_info ehl_info = {
788 GEN11_FEATURES,
789 PLATFORM(INTEL_ELKHARTLAKE),
790 .require_force_probe = 1,
791 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
792 .ppgtt_size = 36,
795 #define GEN12_FEATURES \
796 GEN11_FEATURES, \
797 GEN(12), \
798 .pipe_offsets = { \
799 [TRANSCODER_A] = PIPE_A_OFFSET, \
800 [TRANSCODER_B] = PIPE_B_OFFSET, \
801 [TRANSCODER_C] = PIPE_C_OFFSET, \
802 [TRANSCODER_D] = PIPE_D_OFFSET, \
803 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
804 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
805 }, \
806 .trans_offsets = { \
807 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
808 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
809 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
810 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
811 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
812 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
813 }, \
814 TGL_CURSOR_OFFSETS, \
815 .has_global_mocs = 1, \
816 .display.has_dsb = 1
818 static const struct intel_device_info tgl_info = {
819 GEN12_FEATURES,
820 PLATFORM(INTEL_TIGERLAKE),
821 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
822 .require_force_probe = 1,
823 .display.has_modular_fia = 1,
824 .engine_mask =
825 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
826 .has_rps = false, /* XXX disabled for debugging */
829 #define GEN12_DGFX_FEATURES \
830 GEN12_FEATURES, \
831 .is_dgfx = 1
833 #undef GEN
834 #undef PLATFORM
837 * Make sure any device matches here are from most specific to most
838 * general. For example, since the Quanta match is based on the subsystem
839 * and subvendor IDs, we need it to come before the more general IVB
840 * PCI ID matches, otherwise we'll use the wrong info struct above.
842 static const struct pci_device_id pciidlist[] = {
843 INTEL_I830_IDS(&i830_info),
844 INTEL_I845G_IDS(&i845g_info),
845 INTEL_I85X_IDS(&i85x_info),
846 INTEL_I865G_IDS(&i865g_info),
847 INTEL_I915G_IDS(&i915g_info),
848 INTEL_I915GM_IDS(&i915gm_info),
849 INTEL_I945G_IDS(&i945g_info),
850 INTEL_I945GM_IDS(&i945gm_info),
851 INTEL_I965G_IDS(&i965g_info),
852 INTEL_G33_IDS(&g33_info),
853 INTEL_I965GM_IDS(&i965gm_info),
854 INTEL_GM45_IDS(&gm45_info),
855 INTEL_G45_IDS(&g45_info),
856 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
857 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
858 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
859 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
860 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
861 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
862 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
863 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
864 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
865 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
866 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
867 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
868 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
869 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
870 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
871 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
872 INTEL_VLV_IDS(&vlv_info),
873 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
874 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
875 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
876 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
877 INTEL_CHV_IDS(&chv_info),
878 INTEL_SKL_GT1_IDS(&skl_gt1_info),
879 INTEL_SKL_GT2_IDS(&skl_gt2_info),
880 INTEL_SKL_GT3_IDS(&skl_gt3_info),
881 INTEL_SKL_GT4_IDS(&skl_gt4_info),
882 INTEL_BXT_IDS(&bxt_info),
883 INTEL_GLK_IDS(&glk_info),
884 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
885 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
886 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
887 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
888 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
889 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
890 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
891 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
892 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
893 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
894 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
895 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
896 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
897 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
898 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
899 INTEL_CML_GT1_IDS(&cfl_gt1_info),
900 INTEL_CML_GT2_IDS(&cfl_gt2_info),
901 INTEL_CML_U_GT1_IDS(&cfl_gt1_info),
902 INTEL_CML_U_GT2_IDS(&cfl_gt2_info),
903 INTEL_CNL_IDS(&cnl_info),
904 INTEL_ICL_11_IDS(&icl_info),
905 INTEL_EHL_IDS(&ehl_info),
906 INTEL_TGL_12_IDS(&tgl_info),
907 {0, 0, 0}
909 MODULE_DEVICE_TABLE(pci, pciidlist);
911 static void i915_pci_remove(struct pci_dev *pdev)
913 struct drm_i915_private *i915;
915 i915 = pci_get_drvdata(pdev);
916 if (!i915) /* driver load aborted, nothing to cleanup */
917 return;
919 i915_driver_remove(i915);
920 pci_set_drvdata(pdev, NULL);
922 drm_dev_put(&i915->drm);
925 /* is device_id present in comma separated list of ids */
926 static bool force_probe(u16 device_id, const char *devices)
928 char *s, *p, *tok;
929 bool ret;
931 /* FIXME: transitional */
932 if (i915_modparams.alpha_support) {
933 DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
934 device_id);
935 return true;
938 if (!devices || !*devices)
939 return false;
941 /* match everything */
942 if (strcmp(devices, "*") == 0)
943 return true;
945 s = kstrdup(devices, GFP_KERNEL);
946 if (!s)
947 return false;
949 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
950 u16 val;
952 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
953 ret = true;
954 break;
958 kfree(s);
960 return ret;
963 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
965 struct intel_device_info *intel_info =
966 (struct intel_device_info *) ent->driver_data;
967 int err;
969 if (intel_info->require_force_probe &&
970 !force_probe(pdev->device, i915_modparams.force_probe)) {
971 DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
972 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
973 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
974 "or (recommended) check for kernel updates.\n",
975 pdev->device, pdev->device, pdev->device);
976 return -ENODEV;
979 /* Only bind to function 0 of the device. Early generations
980 * used function 1 as a placeholder for multi-head. This causes
981 * us confusion instead, especially on the systems where both
982 * functions have the same PCI-ID!
984 if (PCI_FUNC(pdev->devfn))
985 return -ENODEV;
988 * apple-gmux is needed on dual GPU MacBook Pro
989 * to probe the panel if we're the inactive GPU.
991 if (vga_switcheroo_client_probe_defer(pdev))
992 return -EPROBE_DEFER;
994 err = i915_driver_probe(pdev, ent);
995 if (err)
996 return err;
998 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
999 i915_pci_remove(pdev);
1000 return -ENODEV;
1003 err = i915_live_selftests(pdev);
1004 if (err) {
1005 i915_pci_remove(pdev);
1006 return err > 0 ? -ENOTTY : err;
1009 err = i915_perf_selftests(pdev);
1010 if (err) {
1011 i915_pci_remove(pdev);
1012 return err > 0 ? -ENOTTY : err;
1015 return 0;
1018 static struct pci_driver i915_pci_driver = {
1019 .name = DRIVER_NAME,
1020 .id_table = pciidlist,
1021 .probe = i915_pci_probe,
1022 .remove = i915_pci_remove,
1023 .driver.pm = &i915_pm_ops,
1026 static int __init i915_init(void)
1028 bool use_kms = true;
1029 int err;
1031 err = i915_globals_init();
1032 if (err)
1033 return err;
1035 err = i915_mock_selftests();
1036 if (err)
1037 return err > 0 ? 0 : err;
1040 * Enable KMS by default, unless explicitly overriden by
1041 * either the i915.modeset prarameter or by the
1042 * vga_text_mode_force boot option.
1045 if (i915_modparams.modeset == 0)
1046 use_kms = false;
1048 if (vgacon_text_force() && i915_modparams.modeset == -1)
1049 use_kms = false;
1051 if (!use_kms) {
1052 /* Silently fail loading to not upset userspace. */
1053 DRM_DEBUG_DRIVER("KMS disabled.\n");
1054 return 0;
1057 err = pci_register_driver(&i915_pci_driver);
1058 if (err)
1059 return err;
1061 i915_perf_sysctl_register();
1062 return 0;
1065 static void __exit i915_exit(void)
1067 if (!i915_pci_driver.driver.owner)
1068 return;
1070 i915_perf_sysctl_unregister();
1071 pci_unregister_driver(&i915_pci_driver);
1072 i915_globals_exit();
1075 module_init(i915_init);
1076 module_exit(i915_exit);
1078 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1079 MODULE_AUTHOR("Intel Corporation");
1081 MODULE_DESCRIPTION(DRIVER_DESC);
1082 MODULE_LICENSE("GPL and additional rights");