drivers/gpu/drm/mediatek/mtk_mipi_tx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Jitao Shi <jitao.shi@mediatek.com>
   5  */
   6
   7 #ifndef _MTK_MIPI_TX_H
   8 #define _MTK_MIPI_TX_H
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/phy/phy.h>
  18
  19 struct mtk_mipitx_data {
  20         const u32 mppll_preserve;
  21         const struct clk_ops *mipi_tx_clk_ops;
  22         void (*mipi_tx_enable_signal)(struct phy *phy);
  23         void (*mipi_tx_disable_signal)(struct phy *phy);
  24 };
  25
  26 struct mtk_mipi_tx {
  27         struct device *dev;
  28         void __iomem *regs;
  29         u32 data_rate;
  30         const struct mtk_mipitx_data *driver_data;
  31         struct clk_hw pll_hw;
  32         struct clk *pll;
  33 };
  34
  35 struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
  36 void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
  37 void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
  38 void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask,
  39                              u32 data);
  40 int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  41                              unsigned long parent_rate);
  42 unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
  43                                           unsigned long parent_rate);
  44
  45 extern const struct mtk_mipitx_data mt2701_mipitx_data;
  46 extern const struct mtk_mipitx_data mt8173_mipitx_data;
  47 extern const struct mtk_mipitx_data mt8183_mipitx_data;
  48
  49 #endif