drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: jitao.shi <jitao.shi@mediatek.com>
   5  */
   6
   7 #include "mtk_mipi_tx.h"
   8
   9 #define MIPITX_LANE_CON         0x000c
  10 #define RG_DSI_CPHY_T1DRV_EN            BIT(0)
  11 #define RG_DSI_ANA_CK_SEL               BIT(1)
  12 #define RG_DSI_PHY_CK_SEL               BIT(2)
  13 #define RG_DSI_CPHY_EN                  BIT(3)
  14 #define RG_DSI_PHYCK_INV_EN             BIT(4)
  15 #define RG_DSI_PWR04_EN                 BIT(5)
  16 #define RG_DSI_BG_LPF_EN                BIT(6)
  17 #define RG_DSI_BG_CORE_EN               BIT(7)
  18 #define RG_DSI_PAD_TIEL_SEL             BIT(8)
  19
  20 #define MIPITX_PLL_PWR          0x0028
  21 #define MIPITX_PLL_CON0         0x002c
  22 #define MIPITX_PLL_CON1         0x0030
  23 #define MIPITX_PLL_CON2         0x0034
  24 #define MIPITX_PLL_CON3         0x0038
  25 #define MIPITX_PLL_CON4         0x003c
  26 #define RG_DSI_PLL_IBIAS                (3 << 10)
  27
  28 #define MIPITX_D2_SW_CTL_EN     0x0144
  29 #define MIPITX_D0_SW_CTL_EN     0x0244
  30 #define MIPITX_CK_CKMODE_EN     0x0328
  31 #define DSI_CK_CKMODE_EN                BIT(0)
  32 #define MIPITX_CK_SW_CTL_EN     0x0344
  33 #define MIPITX_D1_SW_CTL_EN     0x0444
  34 #define MIPITX_D3_SW_CTL_EN     0x0544
  35 #define DSI_SW_CTL_EN                   BIT(0)
  36 #define AD_DSI_PLL_SDM_PWR_ON           BIT(0)
  37 #define AD_DSI_PLL_SDM_ISO_EN           BIT(1)
  38
  39 #define RG_DSI_PLL_EN                   BIT(4)
  40 #define RG_DSI_PLL_POSDIV               (0x7 << 8)
  41
  42 static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
  43 {
  44         struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  45         unsigned int txdiv, txdiv0;
  46         u64 pcw;
  47
  48         dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
  49
  50         if (mipi_tx->data_rate >= 2000000000) {
  51                 txdiv = 1;
  52                 txdiv0 = 0;
  53         } else if (mipi_tx->data_rate >= 1000000000) {
  54                 txdiv = 2;
  55                 txdiv0 = 1;
  56         } else if (mipi_tx->data_rate >= 500000000) {
  57                 txdiv = 4;
  58                 txdiv0 = 2;
  59         } else if (mipi_tx->data_rate > 250000000) {
  60                 txdiv = 8;
  61                 txdiv0 = 3;
  62         } else if (mipi_tx->data_rate >= 125000000) {
  63                 txdiv = 16;
  64                 txdiv0 = 4;
  65         } else {
  66                 return -EINVAL;
  67         }
  68
  69         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
  70
  71         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
  72         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  73         udelay(1);
  74         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
  75         pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
  76         writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
  77         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
  78                                 txdiv0 << 8);
  79         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  80
  81         return 0;
  82 }
  83
  84 static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
  85 {
  86         struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  87
  88         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  89
  90         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
  91         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
  92 }
  93
  94 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  95                                        unsigned long *prate)
  96 {
  97         return clamp_val(rate, 50000000, 1600000000);
  98 }
  99
 100 static const struct clk_ops mtk_mipi_tx_pll_ops = {
 101         .enable = mtk_mipi_tx_pll_enable,
 102         .disable = mtk_mipi_tx_pll_disable,
 103         .round_rate = mtk_mipi_tx_pll_round_rate,
 104         .set_rate = mtk_mipi_tx_pll_set_rate,
 105         .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 106 };
 107
 108 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 109 {
 110         struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
 111
 112         /* BG_LPF_EN / BG_CORE_EN */
 113         writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
 114                mipi_tx->regs + MIPITX_LANE_CON);
 115         usleep_range(30, 100);
 116         writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,
 117                mipi_tx->regs + MIPITX_LANE_CON);
 118
 119         /* Switch OFF each Lane */
 120         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
 121         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
 122         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
 123         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
 124         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 125
 126         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 127 }
 128
 129 static void mtk_mipi_tx_power_off_signal(struct phy *phy)
 130 {
 131         struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
 132
 133         /* Switch ON each Lane */
 134         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
 135         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
 136         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
 137         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
 138         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 139
 140         writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
 141                mipi_tx->regs + MIPITX_LANE_CON);
 142         writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);
 143 }
 144
 145 const struct mtk_mipitx_data mt8183_mipitx_data = {
 146         .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
 147         .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
 148         .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
 149 };