drivers/gpu/drm/mgag200/mgag200_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2010 Matt Turner.
   4  * Copyright 2012 Red Hat
   5  *
   6  * Authors: Matthew Garrett
   7  *          Matt Turner
   8  *          Dave Airlie
   9  */
  10 #ifndef __MGAG200_DRV_H__
  11 #define __MGAG200_DRV_H__
  12
  13 #include <linux/i2c-algo-bit.h>
  14 #include <linux/i2c.h>
  15
  16 #include <video/vga.h>
  17
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_fb_helper.h>
  20 #include <drm/drm_gem.h>
  21 #include <drm/drm_gem_vram_helper.h>
  22
  23 #include "mgag200_reg.h"
  24
  25 #define DRIVER_AUTHOR           "Matthew Garrett"
  26
  27 #define DRIVER_NAME             "mgag200"
  28 #define DRIVER_DESC             "MGA G200 SE"
  29 #define DRIVER_DATE             "20110418"
  30
  31 #define DRIVER_MAJOR            1
  32 #define DRIVER_MINOR            0
  33 #define DRIVER_PATCHLEVEL       0
  34
  35 #define MGAG200FB_CONN_LIMIT 1
  36
  37 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
  38 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
  39 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
  40 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
  41
  42 #define ATTR_INDEX 0x1fc0
  43 #define ATTR_DATA 0x1fc1
  44
  45 #define WREG_ATTR(reg, v)                                       \
  46         do {                                                    \
  47                 RREG8(0x1fda);                                  \
  48                 WREG8(ATTR_INDEX, reg);                         \
  49                 WREG8(ATTR_DATA, v);                            \
  50         } while (0)                                             \
  51
  52 #define WREG_SEQ(reg, v)                                        \
  53         do {                                                    \
  54                 WREG8(MGAREG_SEQ_INDEX, reg);                   \
  55                 WREG8(MGAREG_SEQ_DATA, v);                      \
  56         } while (0)                                             \
  57
  58 #define WREG_CRT(reg, v)                                        \
  59         do {                                                    \
  60                 WREG8(MGAREG_CRTC_INDEX, reg);                  \
  61                 WREG8(MGAREG_CRTC_DATA, v);                     \
  62         } while (0)                                             \
  63
  64
  65 #define WREG_ECRT(reg, v)                                       \
  66         do {                                                    \
  67                 WREG8(MGAREG_CRTCEXT_INDEX, reg);                               \
  68                 WREG8(MGAREG_CRTCEXT_DATA, v);                          \
  69         } while (0)                                             \
  70
  71 #define GFX_INDEX 0x1fce
  72 #define GFX_DATA 0x1fcf
  73
  74 #define WREG_GFX(reg, v)                                        \
  75         do {                                                    \
  76                 WREG8(GFX_INDEX, reg);                          \
  77                 WREG8(GFX_DATA, v);                             \
  78         } while (0)                                             \
  79
  80 #define DAC_INDEX 0x3c00
  81 #define DAC_DATA 0x3c0a
  82
  83 #define WREG_DAC(reg, v)                                        \
  84         do {                                                    \
  85                 WREG8(DAC_INDEX, reg);                          \
  86                 WREG8(DAC_DATA, v);                             \
  87         } while (0)                                             \
  88
  89 #define MGA_MISC_OUT 0x1fc2
  90 #define MGA_MISC_IN 0x1fcc
  91
  92 #define MGAG200_MAX_FB_HEIGHT 4096
  93 #define MGAG200_MAX_FB_WIDTH 4096
  94
  95 #define MATROX_DPMS_CLEARED (-1)
  96
  97 #define to_mga_crtc(x) container_of(x, struct mga_crtc, base)
  98 #define to_mga_encoder(x) container_of(x, struct mga_encoder, base)
  99 #define to_mga_connector(x) container_of(x, struct mga_connector, base)
 100
 101 struct mga_crtc {
 102         struct drm_crtc base;
 103         u8 lut_r[256], lut_g[256], lut_b[256];
 104         int last_dpms;
 105         bool enabled;
 106 };
 107
 108 struct mga_mode_info {
 109         bool mode_config_initialized;
 110         struct mga_crtc *crtc;
 111 };
 112
 113 struct mga_encoder {
 114         struct drm_encoder base;
 115         int last_dpms;
 116 };
 117
 118
 119 struct mga_i2c_chan {
 120         struct i2c_adapter adapter;
 121         struct drm_device *dev;
 122         struct i2c_algo_bit_data bit;
 123         int data, clock;
 124 };
 125
 126 struct mga_connector {
 127         struct drm_connector base;
 128         struct mga_i2c_chan *i2c;
 129 };
 130
 131 struct mga_cursor {
 132         struct drm_gem_vram_object *gbo[2];
 133         unsigned int next_index;
 134 };
 135
 136 struct mga_mc {
 137         resource_size_t                 vram_size;
 138         resource_size_t                 vram_base;
 139         resource_size_t                 vram_window;
 140 };
 141
 142 enum mga_type {
 143         G200_SE_A,
 144         G200_SE_B,
 145         G200_WB,
 146         G200_EV,
 147         G200_EH,
 148         G200_EH3,
 149         G200_ER,
 150         G200_EW3,
 151 };
 152
 153 /* HW does not handle 'startadd' field correct. */
 154 #define MGAG200_FLAG_HW_BUG_NO_STARTADD (1ul << 8)
 155
 156 #define MGAG200_TYPE_MASK       (0x000000ff)
 157 #define MGAG200_FLAG_MASK       (0x00ffff00)
 158
 159 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B)
 160
 161 struct mga_device {
 162         struct drm_device               *dev;
 163         unsigned long                   flags;
 164
 165         resource_size_t                 rmmio_base;
 166         resource_size_t                 rmmio_size;
 167         void __iomem                    *rmmio;
 168
 169         struct mga_mc                   mc;
 170         struct mga_mode_info            mode_info;
 171
 172         struct mga_cursor cursor;
 173
 174         size_t vram_fb_available;
 175
 176         bool                            suspended;
 177         int                             num_crtc;
 178         enum mga_type                   type;
 179         int                             has_sdram;
 180         struct drm_display_mode         mode;
 181
 182         int bpp_shifts[4];
 183
 184         int fb_mtrr;
 185
 186         /* SE model number stored in reg 0x1e24 */
 187         u32 unique_rev_id;
 188 };
 189
 190 static inline enum mga_type
 191 mgag200_type_from_driver_data(kernel_ulong_t driver_data)
 192 {
 193         return (enum mga_type)(driver_data & MGAG200_TYPE_MASK);
 194 }
 195
 196 static inline unsigned long
 197 mgag200_flags_from_driver_data(kernel_ulong_t driver_data)
 198 {
 199         return driver_data & MGAG200_FLAG_MASK;
 200 }
 201
 202                                 /* mgag200_mode.c */
 203 int mgag200_modeset_init(struct mga_device *mdev);
 204 void mgag200_modeset_fini(struct mga_device *mdev);
 205
 206                                 /* mgag200_main.c */
 207 int mgag200_driver_load(struct drm_device *dev, unsigned long flags);
 208 void mgag200_driver_unload(struct drm_device *dev);
 209
 210                                 /* mgag200_i2c.c */
 211 struct mga_i2c_chan *mgag200_i2c_create(struct drm_device *dev);
 212 void mgag200_i2c_destroy(struct mga_i2c_chan *i2c);
 213
 214 int mgag200_mm_init(struct mga_device *mdev);
 215 void mgag200_mm_fini(struct mga_device *mdev);
 216 int mgag200_mmap(struct file *filp, struct vm_area_struct *vma);
 217
 218 int mgag200_cursor_init(struct mga_device *mdev);
 219 void mgag200_cursor_fini(struct mga_device *mdev);
 220 int mgag200_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 221                             uint32_t handle, uint32_t width, uint32_t height);
 222 int mgag200_crtc_cursor_move(struct drm_crtc *crtc, int x, int y);
 223
 224 #endif                          /* __MGAG200_DRV_H__ */