drivers/gpu/drm/msm/adreno/a6xx_hfi.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3
   4 #ifndef _A6XX_HFI_H_
   5 #define _A6XX_HFI_H_
   6
   7 struct a6xx_hfi_queue_table_header {
   8         u32 version;
   9         u32 size;               /* Size of the queue table in dwords */
  10         u32 qhdr0_offset;       /* Offset of the first queue header */
  11         u32 qhdr_size;          /* Size of the queue headers */
  12         u32 num_queues;         /* Number of total queues */
  13         u32 active_queues;      /* Number of active queues */
  14 };
  15
  16 struct a6xx_hfi_queue_header {
  17         u32 status;
  18         u32 iova;
  19         u32 type;
  20         u32 size;
  21         u32 msg_size;
  22         u32 dropped;
  23         u32 rx_watermark;
  24         u32 tx_watermark;
  25         u32 rx_request;
  26         u32 tx_request;
  27         u32 read_index;
  28         u32 write_index;
  29 };
  30
  31 struct a6xx_hfi_queue {
  32         struct a6xx_hfi_queue_header *header;
  33         spinlock_t lock;
  34         u32 *data;
  35         atomic_t seqnum;
  36 };
  37
  38 /* This is the outgoing queue to the GMU */
  39 #define HFI_COMMAND_QUEUE 0
  40
  41 /* THis is the incoming response queue from the GMU */
  42 #define HFI_RESPONSE_QUEUE 1
  43
  44 #define HFI_HEADER_ID(msg) ((msg) & 0xff)
  45 #define HFI_HEADER_SIZE(msg) (((msg) >> 8) & 0xff)
  46 #define HFI_HEADER_SEQNUM(msg) (((msg) >> 20) & 0xfff)
  47
  48 /* FIXME: Do we need this or can we use ARRAY_SIZE? */
  49 #define HFI_RESPONSE_PAYLOAD_SIZE 16
  50
  51 /* HFI message types */
  52
  53 #define HFI_MSG_CMD 0
  54 #define HFI_MSG_ACK 2
  55
  56 #define HFI_F2H_MSG_ACK 126
  57
  58 struct a6xx_hfi_msg_response {
  59         u32 header;
  60         u32 ret_header;
  61         u32 error;
  62         u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
  63 };
  64
  65 #define HFI_F2H_MSG_ERROR 100
  66
  67 struct a6xx_hfi_msg_error {
  68         u32 header;
  69         u32 code;
  70         u32 payload[2];
  71 };
  72
  73 #define HFI_H2F_MSG_INIT 0
  74
  75 struct a6xx_hfi_msg_gmu_init_cmd {
  76         u32 header;
  77         u32 seg_id;
  78         u32 dbg_buffer_addr;
  79         u32 dbg_buffer_size;
  80         u32 boot_state;
  81 };
  82
  83 #define HFI_H2F_MSG_FW_VERSION 1
  84
  85 struct a6xx_hfi_msg_fw_version {
  86         u32 header;
  87         u32 supported_version;
  88 };
  89
  90 #define HFI_H2F_MSG_PERF_TABLE 4
  91
  92 struct perf_level {
  93         u32 vote;
  94         u32 freq;
  95 };
  96
  97 struct a6xx_hfi_msg_perf_table {
  98         u32 header;
  99         u32 num_gpu_levels;
 100         u32 num_gmu_levels;
 101
 102         struct perf_level gx_votes[16];
 103         struct perf_level cx_votes[4];
 104 };
 105
 106 #define HFI_H2F_MSG_BW_TABLE 3
 107
 108 struct a6xx_hfi_msg_bw_table {
 109         u32 header;
 110         u32 bw_level_num;
 111         u32 cnoc_cmds_num;
 112         u32 ddr_cmds_num;
 113         u32 cnoc_wait_bitmask;
 114         u32 ddr_wait_bitmask;
 115         u32 cnoc_cmds_addrs[6];
 116         u32 cnoc_cmds_data[2][6];
 117         u32 ddr_cmds_addrs[8];
 118         u32 ddr_cmds_data[16][8];
 119 };
 120
 121 #define HFI_H2F_MSG_TEST 5
 122
 123 struct a6xx_hfi_msg_test {
 124         u32 header;
 125 };
 126
 127 #endif