drivers/gpu/drm/msm/adreno/adreno_gpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #ifndef __ADRENO_GPU_H__
  10 #define __ADRENO_GPU_H__
  11
  12 #include <linux/firmware.h>
  13 #include <linux/iopoll.h>
  14
  15 #include "msm_gpu.h"
  16
  17 #include "adreno_common.xml.h"
  18 #include "adreno_pm4.xml.h"
  19
  20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
  21 #define REG_SKIP ~0
  22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
  23
  24 /**
  25  * adreno_regs: List of registers that are used in across all
  26  * 3D devices. Each device type has different offset value for the same
  27  * register, so an array of register offsets are declared for every device
  28  * and are indexed by the enumeration values defined in this enum
  29  */
  30 enum adreno_regs {
  31         REG_ADRENO_CP_RB_BASE,
  32         REG_ADRENO_CP_RB_BASE_HI,
  33         REG_ADRENO_CP_RB_RPTR_ADDR,
  34         REG_ADRENO_CP_RB_RPTR_ADDR_HI,
  35         REG_ADRENO_CP_RB_RPTR,
  36         REG_ADRENO_CP_RB_WPTR,
  37         REG_ADRENO_CP_RB_CNTL,
  38         REG_ADRENO_REGISTER_MAX,
  39 };
  40
  41 enum {
  42         ADRENO_FW_PM4 = 0,
  43         ADRENO_FW_SQE = 0, /* a6xx */
  44         ADRENO_FW_PFP = 1,
  45         ADRENO_FW_GMU = 1, /* a6xx */
  46         ADRENO_FW_GPMU = 2,
  47         ADRENO_FW_MAX,
  48 };
  49
  50 enum adreno_quirks {
  51         ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
  52         ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
  53         ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
  54 };
  55
  56 struct adreno_rev {
  57         uint8_t  core;
  58         uint8_t  major;
  59         uint8_t  minor;
  60         uint8_t  patchid;
  61 };
  62
  63 #define ADRENO_REV(core, major, minor, patchid) \
  64         ((struct adreno_rev){ core, major, minor, patchid })
  65
  66 struct adreno_gpu_funcs {
  67         struct msm_gpu_funcs base;
  68         int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
  69 };
  70
  71 struct adreno_info {
  72         struct adreno_rev rev;
  73         uint32_t revn;
  74         const char *name;
  75         const char *fw[ADRENO_FW_MAX];
  76         uint32_t gmem;
  77         enum adreno_quirks quirks;
  78         struct msm_gpu *(*init)(struct drm_device *dev);
  79         const char *zapfw;
  80         u32 inactive_period;
  81 };
  82
  83 const struct adreno_info *adreno_info(struct adreno_rev rev);
  84
  85 struct adreno_gpu {
  86         struct msm_gpu base;
  87         struct adreno_rev rev;
  88         const struct adreno_info *info;
  89         uint32_t gmem;  /* actual gmem size */
  90         uint32_t revn;  /* numeric revision name */
  91         const struct adreno_gpu_funcs *funcs;
  92
  93         /* interesting register offsets to dump: */
  94         const unsigned int *registers;
  95
  96         /*
  97          * Are we loading fw from legacy path?  Prior to addition
  98          * of gpu firmware to linux-firmware, the fw files were
  99          * placed in toplevel firmware directory, following qcom's
 100          * android kernel.  But linux-firmware preferred they be
 101          * placed in a 'qcom' subdirectory.
 102          *
 103          * For backwards compatibility, we try first to load from
 104          * the new path, using request_firmware_direct() to avoid
 105          * any potential timeout waiting for usermode helper, then
 106          * fall back to the old path (with direct load).  And
 107          * finally fall back to request_firmware() with the new
 108          * path to allow the usermode helper.
 109          */
 110         enum {
 111                 FW_LOCATION_UNKNOWN = 0,
 112                 FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
 113                 FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
 114                 FW_LOCATION_HELPER,
 115         } fwloc;
 116
 117         /* firmware: */
 118         const struct firmware *fw[ADRENO_FW_MAX];
 119
 120         /*
 121          * Register offsets are different between some GPUs.
 122          * GPU specific offsets will be exported by GPU specific
 123          * code (a3xx_gpu.c) and stored in this common location.
 124          */
 125         const unsigned int *reg_offsets;
 126 };
 127 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
 128
 129 struct adreno_ocmem {
 130         struct ocmem *ocmem;
 131         unsigned long base;
 132         void *hdl;
 133 };
 134
 135 /* platform config data (ie. from DT, or pdata) */
 136 struct adreno_platform_config {
 137         struct adreno_rev rev;
 138 };
 139
 140 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
 141
 142 #define spin_until(X) ({                                   \
 143         int __ret = -ETIMEDOUT;                            \
 144         unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
 145         do {                                               \
 146                 if (X) {                                   \
 147                         __ret = 0;                         \
 148                         break;                             \
 149                 }                                          \
 150         } while (time_before(jiffies, __t));               \
 151         __ret;                                             \
 152 })
 153
 154 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
 155 {
 156         return (gpu->revn < 300);
 157 }
 158
 159 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
 160 {
 161         return (gpu->revn < 210);
 162 }
 163
 164 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
 165 {
 166         return gpu->revn == 225;
 167 }
 168
 169 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
 170 {
 171         return (gpu->revn >= 300) && (gpu->revn < 400);
 172 }
 173
 174 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
 175 {
 176         return gpu->revn == 305;
 177 }
 178
 179 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
 180 {
 181         /* yes, 307, because a305c is 306 */
 182         return gpu->revn == 307;
 183 }
 184
 185 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
 186 {
 187         return gpu->revn == 320;
 188 }
 189
 190 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
 191 {
 192         return gpu->revn == 330;
 193 }
 194
 195 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
 196 {
 197         return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
 198 }
 199
 200 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
 201 {
 202         return (gpu->revn >= 400) && (gpu->revn < 500);
 203 }
 204
 205 static inline int adreno_is_a420(struct adreno_gpu *gpu)
 206 {
 207         return gpu->revn == 420;
 208 }
 209
 210 static inline int adreno_is_a430(struct adreno_gpu *gpu)
 211 {
 212        return gpu->revn == 430;
 213 }
 214
 215 static inline int adreno_is_a510(struct adreno_gpu *gpu)
 216 {
 217         return gpu->revn == 510;
 218 }
 219
 220 static inline int adreno_is_a530(struct adreno_gpu *gpu)
 221 {
 222         return gpu->revn == 530;
 223 }
 224
 225 static inline int adreno_is_a540(struct adreno_gpu *gpu)
 226 {
 227         return gpu->revn == 540;
 228 }
 229
 230 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 231 {
 232        return gpu->revn == 618;
 233 }
 234
 235 static inline int adreno_is_a630(struct adreno_gpu *gpu)
 236 {
 237        return gpu->revn == 630;
 238 }
 239
 240 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
 241 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
 242                 const char *fwname);
 243 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 244                 const struct firmware *fw, u64 *iova);
 245 int adreno_hw_init(struct msm_gpu *gpu);
 246 void adreno_recover(struct msm_gpu *gpu);
 247 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 248                 struct msm_file_private *ctx);
 249 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
 250 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
 251 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 252 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 253                 struct drm_printer *p);
 254 #endif
 255 void adreno_dump_info(struct msm_gpu *gpu);
 256 void adreno_dump(struct msm_gpu *gpu);
 257 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
 258 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
 259
 260 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
 261                           struct adreno_ocmem *ocmem);
 262 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
 263
 264 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 265                 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
 266                 int nr_rings);
 267 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
 268 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
 269
 270 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
 271
 272 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
 273 int adreno_gpu_state_put(struct msm_gpu_state *state);
 274
 275 /*
 276  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
 277  * out of secure mode
 278  */
 279 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
 280
 281 /* ringbuffer helpers (the parts that are adreno specific) */
 282
 283 static inline void
 284 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 285 {
 286         adreno_wait_ring(ring, cnt+1);
 287         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 288 }
 289
 290 /* no-op packet: */
 291 static inline void
 292 OUT_PKT2(struct msm_ringbuffer *ring)
 293 {
 294         adreno_wait_ring(ring, 1);
 295         OUT_RING(ring, CP_TYPE2_PKT);
 296 }
 297
 298 static inline void
 299 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 300 {
 301         adreno_wait_ring(ring, cnt+1);
 302         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 303 }
 304
 305 static inline u32 PM4_PARITY(u32 val)
 306 {
 307         return (0x9669 >> (0xF & (val ^
 308                 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
 309                 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
 310                 (val >> 28)))) & 1;
 311 }
 312
 313 /* Maximum number of values that can be executed for one opcode */
 314 #define TYPE4_MAX_PAYLOAD 127
 315
 316 #define PKT4(_reg, _cnt) \
 317         (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
 318          (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
 319
 320 static inline void
 321 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 322 {
 323         adreno_wait_ring(ring, cnt + 1);
 324         OUT_RING(ring, PKT4(regindx, cnt));
 325 }
 326
 327 static inline void
 328 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 329 {
 330         adreno_wait_ring(ring, cnt + 1);
 331         OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
 332                 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
 333 }
 334
 335 /*
 336  * adreno_reg_check() - Checks the validity of a register enum
 337  * @gpu:                Pointer to struct adreno_gpu
 338  * @offset_name:        The register enum that is checked
 339  */
 340 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
 341                 enum adreno_regs offset_name)
 342 {
 343         BUG_ON(offset_name >= REG_ADRENO_REGISTER_MAX || !gpu->reg_offsets[offset_name]);
 344
 345         /*
 346          * REG_SKIP is a special value that tell us that the register in
 347          * question isn't implemented on target but don't trigger a BUG(). This
 348          * is used to cleanly implement adreno_gpu_write64() and
 349          * adreno_gpu_read64() in a generic fashion
 350          */
 351         if (gpu->reg_offsets[offset_name] == REG_SKIP)
 352                 return false;
 353
 354         return true;
 355 }
 356
 357 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
 358                 enum adreno_regs offset_name)
 359 {
 360         u32 reg = gpu->reg_offsets[offset_name];
 361         u32 val = 0;
 362         if(adreno_reg_check(gpu,offset_name))
 363                 val = gpu_read(&gpu->base, reg - 1);
 364         return val;
 365 }
 366
 367 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
 368                 enum adreno_regs offset_name, u32 data)
 369 {
 370         u32 reg = gpu->reg_offsets[offset_name];
 371         if(adreno_reg_check(gpu, offset_name))
 372                 gpu_write(&gpu->base, reg - 1, data);
 373 }
 374
 375 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
 376 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
 377 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
 378 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
 379 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
 380
 381 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
 382                 enum adreno_regs lo, enum adreno_regs hi, u64 data)
 383 {
 384         adreno_gpu_write(gpu, lo, lower_32_bits(data));
 385         adreno_gpu_write(gpu, hi, upper_32_bits(data));
 386 }
 387
 388 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
 389 {
 390         return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
 391 }
 392
 393 /*
 394  * Given a register and a count, return a value to program into
 395  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
 396  * registers starting at _reg.
 397  *
 398  * The register base needs to be a multiple of the length. If it is not, the
 399  * hardware will quietly mask off the bits for you and shift the size. For
 400  * example, if you intend the protection to start at 0x07 for a length of 4
 401  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
 402  * expose registers you intended to protect!
 403  */
 404 #define ADRENO_PROTECT_RW(_reg, _len) \
 405         ((1 << 30) | (1 << 29) | \
 406         ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
 407
 408 /*
 409  * Same as above, but allow reads over the range. For areas of mixed use (such
 410  * as performance counters) this allows us to protect a much larger range with a
 411  * single register
 412  */
 413 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
 414         ((1 << 29) \
 415         ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
 416
 417
 418 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
 419         readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
 420                 interval, timeout)
 421
 422 #endif /* __ADRENO_GPU_H__ */