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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_encoder.c
blobf8ac3bf60fd6055ce7fb3a719cc44e73aff0dedb
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
9 #include <linux/debugfs.h>
10 #include <linux/kthread.h>
11 #include <linux/seq_file.h>
12
13 #include <drm/drm_crtc.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_probe_helper.h>
16
17 #include "msm_drv.h"
18 #include "dpu_kms.h"
19 #include "dpu_hwio.h"
20 #include "dpu_hw_catalog.h"
21 #include "dpu_hw_intf.h"
22 #include "dpu_hw_ctl.h"
23 #include "dpu_formats.h"
24 #include "dpu_encoder_phys.h"
25 #include "dpu_crtc.h"
26 #include "dpu_trace.h"
27 #include "dpu_core_irq.h"
28
29 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
30 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
31
32 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
33 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
34
35 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
36 (p) ? (p)->parent->base.id : -1, \
37 (p) ? (p)->intf_idx - INTF_0 : -1, \
38 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
39 ##__VA_ARGS__)
40
41 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
42 (p) ? (p)->parent->base.id : -1, \
43 (p) ? (p)->intf_idx - INTF_0 : -1, \
44 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
45 ##__VA_ARGS__)
46
47 /*
48 * Two to anticipate panels that can do cmd/vid dynamic switching
49 * plan is to create all possible physical encoder types, and switch between
50 * them at runtime
51 */
52 #define NUM_PHYS_ENCODER_TYPES 2
53
54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
56
57 #define MAX_CHANNELS_PER_ENC 2
58
59 #define IDLE_SHORT_TIMEOUT 1
60
61 #define MAX_HDISPLAY_SPLIT 1080
62
63 /* timeout in frames waiting for frame done */
64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
65
66 /**
67 * enum dpu_enc_rc_events - events for resource control state machine
68 * @DPU_ENC_RC_EVENT_KICKOFF:
69 * This event happens at NORMAL priority.
70 * Event that signals the start of the transfer. When this event is
71 * received, enable MDP/DSI core clocks. Regardless of the previous
72 * state, the resource should be in ON state at the end of this event.
73 * @DPU_ENC_RC_EVENT_FRAME_DONE:
74 * This event happens at INTERRUPT level.
75 * Event signals the end of the data transfer after the PP FRAME_DONE
76 * event. At the end of this event, a delayed work is scheduled to go to
77 * IDLE_PC state after IDLE_TIMEOUT time.
78 * @DPU_ENC_RC_EVENT_PRE_STOP:
79 * This event happens at NORMAL priority.
80 * This event, when received during the ON state, leave the RC STATE
81 * in the PRE_OFF state. It should be followed by the STOP event as
82 * part of encoder disable.
83 * If received during IDLE or OFF states, it will do nothing.
84 * @DPU_ENC_RC_EVENT_STOP:
85 * This event happens at NORMAL priority.
86 * When this event is received, disable all the MDP/DSI core clocks, and
87 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
89 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
90 * Resource state should be in OFF at the end of the event.
91 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
92 * This event happens at NORMAL priority from a work item.
93 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
94 * This would disable MDP/DSI core clocks and change the resource state
95 * to IDLE.
96 */
97 enum dpu_enc_rc_events {
98 DPU_ENC_RC_EVENT_KICKOFF = 1,
99 DPU_ENC_RC_EVENT_FRAME_DONE,
100 DPU_ENC_RC_EVENT_PRE_STOP,
101 DPU_ENC_RC_EVENT_STOP,
102 DPU_ENC_RC_EVENT_ENTER_IDLE
103 };
104
105 /*
106 * enum dpu_enc_rc_states - states that the resource control maintains
107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
112 */
113 enum dpu_enc_rc_states {
114 DPU_ENC_RC_STATE_OFF,
115 DPU_ENC_RC_STATE_PRE_OFF,
116 DPU_ENC_RC_STATE_ON,
117 DPU_ENC_RC_STATE_IDLE
118 };
119
120 /**
121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
122 * encoders. Virtual encoder manages one "logical" display. Physical
123 * encoders manage one intf block, tied to a specific panel/sub-panel.
124 * Virtual encoder defers as much as possible to the physical encoders.
125 * Virtual encoder registers itself with the DRM Framework as the encoder.
126 * @base: drm_encoder base class for registration with DRM
127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
128 * @bus_scaling_client: Client handle to the bus scaling interface
129 * @enabled: True if the encoder is active, protected by enc_lock
130 * @num_phys_encs: Actual number of physical encoders contained.
131 * @phys_encs: Container of physical encoders managed.
132 * @cur_master: Pointer to the current master in this mode. Optimization
133 * Only valid after enable. Cleared as disable.
134 * @hw_pp Handle to the pingpong blocks used for the display. No.
135 * pingpong blocks can be different than num_phys_encs.
136 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped
137 * for partial update right-only cases, such as pingpong
138 * split where virtual pingpong does not generate IRQs
139 * @crtc: Pointer to the currently assigned crtc. Normally you
140 * would use crtc->state->encoder_mask to determine the
141 * link between encoder/crtc. However in this case we need
142 * to track crtc in the disable() hook which is called
143 * _after_ encoder_mask is cleared.
144 * @crtc_kickoff_cb: Callback into CRTC that will flush & start
145 * all CTL paths
146 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
147 * @debugfs_root: Debug file system root file node
148 * @enc_lock: Lock around physical encoder
149 * create/destroy/enable/disable
150 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
151 * busy processing current command.
152 * Bit0 = phys_encs[0] etc.
153 * @crtc_frame_event_cb: callback handler for frame event
154 * @crtc_frame_event_cb_data: callback handler private data
155 * @frame_done_timeout_ms: frame done timeout in ms
156 * @frame_done_timer: watchdog timer for frame done event
157 * @vsync_event_timer: vsync timer
158 * @disp_info: local copy of msm_display_info struct
159 * @idle_pc_supported: indicate if idle power collaps is supported
160 * @rc_lock: resource control mutex lock to protect
161 * virt encoder over various state changes
162 * @rc_state: resource controller state
163 * @delayed_off_work: delayed worker to schedule disabling of
164 * clks and resources after IDLE_TIMEOUT time.
165 * @vsync_event_work: worker to handle vsync event for autorefresh
166 * @topology: topology of the display
167 * @mode_set_complete: flag to indicate modeset completion
168 * @idle_timeout: idle timeout duration in milliseconds
169 */
170 struct dpu_encoder_virt {
171 struct drm_encoder base;
172 spinlock_t enc_spinlock;
173 uint32_t bus_scaling_client;
174
175 bool enabled;
176
177 unsigned int num_phys_encs;
178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
179 struct dpu_encoder_phys *cur_master;
180 struct dpu_encoder_phys *cur_slave;
181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
182
183 bool intfs_swapped;
184
185 struct drm_crtc *crtc;
186
187 struct dentry *debugfs_root;
188 struct mutex enc_lock;
189 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
190 void (*crtc_frame_event_cb)(void *, u32 event);
191 void *crtc_frame_event_cb_data;
192
193 atomic_t frame_done_timeout_ms;
194 struct timer_list frame_done_timer;
195 struct timer_list vsync_event_timer;
196
197 struct msm_display_info disp_info;
198
199 bool idle_pc_supported;
200 struct mutex rc_lock;
201 enum dpu_enc_rc_states rc_state;
202 struct delayed_work delayed_off_work;
203 struct kthread_work vsync_event_work;
204 struct msm_display_topology topology;
205 bool mode_set_complete;
206
207 u32 idle_timeout;
208 };
209
210 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
211
212 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
213 enum dpu_intr_idx intr_idx)
214 {
215 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
216 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
217 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
218
219 if (phys_enc->parent_ops->handle_frame_done)
220 phys_enc->parent_ops->handle_frame_done(
221 phys_enc->parent, phys_enc,
222 DPU_ENCODER_FRAME_EVENT_ERROR);
223 }
224
225 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
226 int32_t hw_id, struct dpu_encoder_wait_info *info);
227
228 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
229 enum dpu_intr_idx intr_idx,
230 struct dpu_encoder_wait_info *wait_info)
231 {
232 struct dpu_encoder_irq *irq;
233 u32 irq_status;
234 int ret;
235
236 if (!wait_info || intr_idx >= INTR_IDX_MAX) {
237 DPU_ERROR("invalid params\n");
238 return -EINVAL;
239 }
240 irq = &phys_enc->irq[intr_idx];
241
242 /* note: do master / slave checking outside */
243
244 /* return EWOULDBLOCK since we know the wait isn't necessary */
245 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
246 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
247 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
248 irq->irq_idx);
249 return -EWOULDBLOCK;
250 }
251
252 if (irq->irq_idx < 0) {
253 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
254 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
255 irq->name);
256 return 0;
257 }
258
259 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
260 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
261 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
262 atomic_read(wait_info->atomic_cnt));
263
264 ret = dpu_encoder_helper_wait_event_timeout(
265 DRMID(phys_enc->parent),
266 irq->hw_idx,
267 wait_info);
268
269 if (ret <= 0) {
270 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
271 irq->irq_idx, true);
272 if (irq_status) {
273 unsigned long flags;
274
275 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
276 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
277 DRMID(phys_enc->parent), intr_idx,
278 irq->hw_idx, irq->irq_idx,
279 phys_enc->hw_pp->idx - PINGPONG_0,
280 atomic_read(wait_info->atomic_cnt));
281 local_irq_save(flags);
282 irq->cb.func(phys_enc, irq->irq_idx);
283 local_irq_restore(flags);
284 ret = 0;
285 } else {
286 ret = -ETIMEDOUT;
287 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
288 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
289 DRMID(phys_enc->parent), intr_idx,
290 irq->hw_idx, irq->irq_idx,
291 phys_enc->hw_pp->idx - PINGPONG_0,
292 atomic_read(wait_info->atomic_cnt));
293 }
294 } else {
295 ret = 0;
296 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
297 intr_idx, irq->hw_idx, irq->irq_idx,
298 phys_enc->hw_pp->idx - PINGPONG_0,
299 atomic_read(wait_info->atomic_cnt));
300 }
301
302 return ret;
303 }
304
305 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
306 enum dpu_intr_idx intr_idx)
307 {
308 struct dpu_encoder_irq *irq;
309 int ret = 0;
310
311 if (intr_idx >= INTR_IDX_MAX) {
312 DPU_ERROR("invalid params\n");
313 return -EINVAL;
314 }
315 irq = &phys_enc->irq[intr_idx];
316
317 if (irq->irq_idx >= 0) {
318 DPU_DEBUG_PHYS(phys_enc,
319 "skipping already registered irq %s type %d\n",
320 irq->name, irq->intr_type);
321 return 0;
322 }
323
324 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
325 irq->intr_type, irq->hw_idx);
326 if (irq->irq_idx < 0) {
327 DPU_ERROR_PHYS(phys_enc,
328 "failed to lookup IRQ index for %s type:%d\n",
329 irq->name, irq->intr_type);
330 return -EINVAL;
331 }
332
333 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
334 &irq->cb);
335 if (ret) {
336 DPU_ERROR_PHYS(phys_enc,
337 "failed to register IRQ callback for %s\n",
338 irq->name);
339 irq->irq_idx = -EINVAL;
340 return ret;
341 }
342
343 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
344 if (ret) {
345 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
346 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
347 irq->irq_idx);
348 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
349 irq->irq_idx, &irq->cb);
350 irq->irq_idx = -EINVAL;
351 return ret;
352 }
353
354 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
355 irq->hw_idx, irq->irq_idx);
356
357 return ret;
358 }
359
360 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
361 enum dpu_intr_idx intr_idx)
362 {
363 struct dpu_encoder_irq *irq;
364 int ret;
365
366 irq = &phys_enc->irq[intr_idx];
367
368 /* silently skip irqs that weren't registered */
369 if (irq->irq_idx < 0) {
370 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
371 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
372 irq->irq_idx);
373 return 0;
374 }
375
376 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
377 if (ret) {
378 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
379 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
380 irq->irq_idx, ret);
381 }
382
383 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
384 &irq->cb);
385 if (ret) {
386 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
387 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
388 irq->irq_idx, ret);
389 }
390
391 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
392 irq->hw_idx, irq->irq_idx);
393
394 irq->irq_idx = -EINVAL;
395
396 return 0;
397 }
398
399 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
400 struct dpu_encoder_hw_resources *hw_res)
401 {
402 struct dpu_encoder_virt *dpu_enc = NULL;
403 int i = 0;
404
405 dpu_enc = to_dpu_encoder_virt(drm_enc);
406 DPU_DEBUG_ENC(dpu_enc, "\n");
407
408 /* Query resources used by phys encs, expected to be without overlap */
409 memset(hw_res, 0, sizeof(*hw_res));
410
411 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
412 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
413
414 if (phys->ops.get_hw_resources)
415 phys->ops.get_hw_resources(phys, hw_res);
416 }
417 }
418
419 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
420 {
421 struct dpu_encoder_virt *dpu_enc = NULL;
422 int i = 0;
423
424 if (!drm_enc) {
425 DPU_ERROR("invalid encoder\n");
426 return;
427 }
428
429 dpu_enc = to_dpu_encoder_virt(drm_enc);
430 DPU_DEBUG_ENC(dpu_enc, "\n");
431
432 mutex_lock(&dpu_enc->enc_lock);
433
434 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
435 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
436
437 if (phys->ops.destroy) {
438 phys->ops.destroy(phys);
439 --dpu_enc->num_phys_encs;
440 dpu_enc->phys_encs[i] = NULL;
441 }
442 }
443
444 if (dpu_enc->num_phys_encs)
445 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
446 dpu_enc->num_phys_encs);
447 dpu_enc->num_phys_encs = 0;
448 mutex_unlock(&dpu_enc->enc_lock);
449
450 drm_encoder_cleanup(drm_enc);
451 mutex_destroy(&dpu_enc->enc_lock);
452 }
453
454 void dpu_encoder_helper_split_config(
455 struct dpu_encoder_phys *phys_enc,
456 enum dpu_intf interface)
457 {
458 struct dpu_encoder_virt *dpu_enc;
459 struct split_pipe_cfg cfg = { 0 };
460 struct dpu_hw_mdp *hw_mdptop;
461 struct msm_display_info *disp_info;
462
463 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
464 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
465 return;
466 }
467
468 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
469 hw_mdptop = phys_enc->hw_mdptop;
470 disp_info = &dpu_enc->disp_info;
471
472 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
473 return;
474
475 /**
476 * disable split modes since encoder will be operating in as the only
477 * encoder, either for the entire use case in the case of, for example,
478 * single DSI, or for this frame in the case of left/right only partial
479 * update.
480 */
481 if (phys_enc->split_role == ENC_ROLE_SOLO) {
482 if (hw_mdptop->ops.setup_split_pipe)
483 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
484 return;
485 }
486
487 cfg.en = true;
488 cfg.mode = phys_enc->intf_mode;
489 cfg.intf = interface;
490
491 if (cfg.en && phys_enc->ops.needs_single_flush &&
492 phys_enc->ops.needs_single_flush(phys_enc))
493 cfg.split_flush_en = true;
494
495 if (phys_enc->split_role == ENC_ROLE_MASTER) {
496 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
497
498 if (hw_mdptop->ops.setup_split_pipe)
499 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
500 }
501 }
502
503 static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
504 struct drm_display_mode *adj_mode)
505 {
506 struct drm_display_mode *cur_mode;
507
508 if (!connector || !adj_mode)
509 return;
510
511 list_for_each_entry(cur_mode, &connector->modes, head) {
512 if (cur_mode->vdisplay == adj_mode->vdisplay &&
513 cur_mode->hdisplay == adj_mode->hdisplay &&
514 drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
515 adj_mode->private = cur_mode->private;
516 adj_mode->private_flags |= cur_mode->private_flags;
517 }
518 }
519 }
520
521 static struct msm_display_topology dpu_encoder_get_topology(
522 struct dpu_encoder_virt *dpu_enc,
523 struct dpu_kms *dpu_kms,
524 struct drm_display_mode *mode)
525 {
526 struct msm_display_topology topology;
527 int i, intf_count = 0;
528
529 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
530 if (dpu_enc->phys_encs[i])
531 intf_count++;
532
533 /* Datapath topology selection
534 *
535 * Dual display
536 * 2 LM, 2 INTF ( Split display using 2 interfaces)
537 *
538 * Single display
539 * 1 LM, 1 INTF
540 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
541 *
542 */
543 if (intf_count == 2)
544 topology.num_lm = 2;
545 else if (!dpu_kms->catalog->caps->has_3d_merge)
546 topology.num_lm = 1;
547 else
548 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
549
550 topology.num_enc = 0;
551 topology.num_intf = intf_count;
552
553 return topology;
554 }
555 static int dpu_encoder_virt_atomic_check(
556 struct drm_encoder *drm_enc,
557 struct drm_crtc_state *crtc_state,
558 struct drm_connector_state *conn_state)
559 {
560 struct dpu_encoder_virt *dpu_enc;
561 struct msm_drm_private *priv;
562 struct dpu_kms *dpu_kms;
563 const struct drm_display_mode *mode;
564 struct drm_display_mode *adj_mode;
565 struct msm_display_topology topology;
566 int i = 0;
567 int ret = 0;
568
569 if (!drm_enc || !crtc_state || !conn_state) {
570 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
571 drm_enc != 0, crtc_state != 0, conn_state != 0);
572 return -EINVAL;
573 }
574
575 dpu_enc = to_dpu_encoder_virt(drm_enc);
576 DPU_DEBUG_ENC(dpu_enc, "\n");
577
578 priv = drm_enc->dev->dev_private;
579 dpu_kms = to_dpu_kms(priv->kms);
580 mode = &crtc_state->mode;
581 adj_mode = &crtc_state->adjusted_mode;
582 trace_dpu_enc_atomic_check(DRMID(drm_enc));
583
584 /*
585 * display drivers may populate private fields of the drm display mode
586 * structure while registering possible modes of a connector with DRM.
587 * These private fields are not populated back while DRM invokes
588 * the mode_set callbacks. This module retrieves and populates the
589 * private fields of the given mode.
590 */
591 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
592
593 /* perform atomic check on the first physical encoder (master) */
594 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
595 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
596
597 if (phys->ops.atomic_check)
598 ret = phys->ops.atomic_check(phys, crtc_state,
599 conn_state);
600 else if (phys->ops.mode_fixup)
601 if (!phys->ops.mode_fixup(phys, mode, adj_mode))
602 ret = -EINVAL;
603
604 if (ret) {
605 DPU_ERROR_ENC(dpu_enc,
606 "mode unsupported, phys idx %d\n", i);
607 break;
608 }
609 }
610
611 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
612
613 /* Reserve dynamic resources now. Indicating AtomicTest phase */
614 if (!ret) {
615 /*
616 * Avoid reserving resources when mode set is pending. Topology
617 * info may not be available to complete reservation.
618 */
619 if (drm_atomic_crtc_needs_modeset(crtc_state)
620 && dpu_enc->mode_set_complete) {
621 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
622 topology, true);
623 dpu_enc->mode_set_complete = false;
624 }
625 }
626
627 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
628 adj_mode->private_flags);
629
630 return ret;
631 }
632
633 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
634 struct msm_display_info *disp_info)
635 {
636 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
637 struct msm_drm_private *priv;
638 struct dpu_kms *dpu_kms;
639 struct dpu_hw_mdp *hw_mdptop;
640 struct drm_encoder *drm_enc;
641 int i;
642
643 if (!dpu_enc || !disp_info) {
644 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
645 dpu_enc != NULL, disp_info != NULL);
646 return;
647 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
648 DPU_ERROR("invalid num phys enc %d/%d\n",
649 dpu_enc->num_phys_encs,
650 (int) ARRAY_SIZE(dpu_enc->hw_pp));
651 return;
652 }
653
654 drm_enc = &dpu_enc->base;
655 /* this pointers are checked in virt_enable_helper */
656 priv = drm_enc->dev->dev_private;
657
658 dpu_kms = to_dpu_kms(priv->kms);
659 hw_mdptop = dpu_kms->hw_mdp;
660 if (!hw_mdptop) {
661 DPU_ERROR("invalid mdptop\n");
662 return;
663 }
664
665 if (hw_mdptop->ops.setup_vsync_source &&
666 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
667 for (i = 0; i < dpu_enc->num_phys_encs; i++)
668 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
669
670 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
671 if (disp_info->is_te_using_watchdog_timer)
672 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
673 else
674 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
675
676 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
677 }
678 }
679
680 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
681 {
682 struct dpu_encoder_virt *dpu_enc;
683 int i;
684
685 if (!drm_enc) {
686 DPU_ERROR("invalid encoder\n");
687 return;
688 }
689
690 dpu_enc = to_dpu_encoder_virt(drm_enc);
691
692 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
693 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
694 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
695
696 if (phys->ops.irq_control)
697 phys->ops.irq_control(phys, enable);
698 }
699
700 }
701
702 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
703 bool enable)
704 {
705 struct msm_drm_private *priv;
706 struct dpu_kms *dpu_kms;
707 struct dpu_encoder_virt *dpu_enc;
708
709 dpu_enc = to_dpu_encoder_virt(drm_enc);
710 priv = drm_enc->dev->dev_private;
711 dpu_kms = to_dpu_kms(priv->kms);
712
713 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
714
715 if (!dpu_enc->cur_master) {
716 DPU_ERROR("encoder master not set\n");
717 return;
718 }
719
720 if (enable) {
721 /* enable DPU core clks */
722 pm_runtime_get_sync(&dpu_kms->pdev->dev);
723
724 /* enable all the irq */
725 _dpu_encoder_irq_control(drm_enc, true);
726
727 } else {
728 /* disable all the irq */
729 _dpu_encoder_irq_control(drm_enc, false);
730
731 /* disable DPU core clks */
732 pm_runtime_put_sync(&dpu_kms->pdev->dev);
733 }
734
735 }
736
737 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
738 u32 sw_event)
739 {
740 struct dpu_encoder_virt *dpu_enc;
741 struct msm_drm_private *priv;
742 bool is_vid_mode = false;
743
744 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
745 DPU_ERROR("invalid parameters\n");
746 return -EINVAL;
747 }
748 dpu_enc = to_dpu_encoder_virt(drm_enc);
749 priv = drm_enc->dev->dev_private;
750 is_vid_mode = dpu_enc->disp_info.capabilities &
751 MSM_DISPLAY_CAP_VID_MODE;
752
753 /*
754 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
755 * events and return early for other events (ie wb display).
756 */
757 if (!dpu_enc->idle_pc_supported &&
758 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
759 sw_event != DPU_ENC_RC_EVENT_STOP &&
760 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
761 return 0;
762
763 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
764 dpu_enc->rc_state, "begin");
765
766 switch (sw_event) {
767 case DPU_ENC_RC_EVENT_KICKOFF:
768 /* cancel delayed off work, if any */
769 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
770 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
771 sw_event);
772
773 mutex_lock(&dpu_enc->rc_lock);
774
775 /* return if the resource control is already in ON state */
776 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
777 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
778 DRMID(drm_enc), sw_event);
779 mutex_unlock(&dpu_enc->rc_lock);
780 return 0;
781 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
782 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
783 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
784 DRMID(drm_enc), sw_event,
785 dpu_enc->rc_state);
786 mutex_unlock(&dpu_enc->rc_lock);
787 return -EINVAL;
788 }
789
790 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
791 _dpu_encoder_irq_control(drm_enc, true);
792 else
793 _dpu_encoder_resource_control_helper(drm_enc, true);
794
795 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
796
797 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
798 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
799 "kickoff");
800
801 mutex_unlock(&dpu_enc->rc_lock);
802 break;
803
804 case DPU_ENC_RC_EVENT_FRAME_DONE:
805 /*
806 * mutex lock is not used as this event happens at interrupt
807 * context. And locking is not required as, the other events
808 * like KICKOFF and STOP does a wait-for-idle before executing
809 * the resource_control
810 */
811 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
812 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
813 DRMID(drm_enc), sw_event,
814 dpu_enc->rc_state);
815 return -EINVAL;
816 }
817
818 /*
819 * schedule off work item only when there are no
820 * frames pending
821 */
822 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
823 DRM_DEBUG_KMS("id:%d skip schedule work\n",
824 DRMID(drm_enc));
825 return 0;
826 }
827
828 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
829 msecs_to_jiffies(dpu_enc->idle_timeout));
830
831 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
832 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
833 "frame done");
834 break;
835
836 case DPU_ENC_RC_EVENT_PRE_STOP:
837 /* cancel delayed off work, if any */
838 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
839 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
840 sw_event);
841
842 mutex_lock(&dpu_enc->rc_lock);
843
844 if (is_vid_mode &&
845 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
846 _dpu_encoder_irq_control(drm_enc, true);
847 }
848 /* skip if is already OFF or IDLE, resources are off already */
849 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
850 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
851 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
852 DRMID(drm_enc), sw_event,
853 dpu_enc->rc_state);
854 mutex_unlock(&dpu_enc->rc_lock);
855 return 0;
856 }
857
858 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
859
860 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
861 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
862 "pre stop");
863
864 mutex_unlock(&dpu_enc->rc_lock);
865 break;
866
867 case DPU_ENC_RC_EVENT_STOP:
868 mutex_lock(&dpu_enc->rc_lock);
869
870 /* return if the resource control is already in OFF state */
871 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
872 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
873 DRMID(drm_enc), sw_event);
874 mutex_unlock(&dpu_enc->rc_lock);
875 return 0;
876 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
877 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
878 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
879 mutex_unlock(&dpu_enc->rc_lock);
880 return -EINVAL;
881 }
882
883 /**
884 * expect to arrive here only if in either idle state or pre-off
885 * and in IDLE state the resources are already disabled
886 */
887 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
888 _dpu_encoder_resource_control_helper(drm_enc, false);
889
890 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
891
892 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
893 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
894 "stop");
895
896 mutex_unlock(&dpu_enc->rc_lock);
897 break;
898
899 case DPU_ENC_RC_EVENT_ENTER_IDLE:
900 mutex_lock(&dpu_enc->rc_lock);
901
902 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
903 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
904 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
905 mutex_unlock(&dpu_enc->rc_lock);
906 return 0;
907 }
908
909 /*
910 * if we are in ON but a frame was just kicked off,
911 * ignore the IDLE event, it's probably a stale timer event
912 */
913 if (dpu_enc->frame_busy_mask[0]) {
914 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
915 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
916 mutex_unlock(&dpu_enc->rc_lock);
917 return 0;
918 }
919
920 if (is_vid_mode)
921 _dpu_encoder_irq_control(drm_enc, false);
922 else
923 _dpu_encoder_resource_control_helper(drm_enc, false);
924
925 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
926
927 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
928 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
929 "idle");
930
931 mutex_unlock(&dpu_enc->rc_lock);
932 break;
933
934 default:
935 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
936 sw_event);
937 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
938 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
939 "error");
940 break;
941 }
942
943 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
944 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
945 "end");
946 return 0;
947 }
948
949 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
950 struct drm_display_mode *mode,
951 struct drm_display_mode *adj_mode)
952 {
953 struct dpu_encoder_virt *dpu_enc;
954 struct msm_drm_private *priv;
955 struct dpu_kms *dpu_kms;
956 struct list_head *connector_list;
957 struct drm_connector *conn = NULL, *conn_iter;
958 struct drm_crtc *drm_crtc;
959 struct dpu_crtc_state *cstate;
960 struct dpu_rm_hw_iter hw_iter;
961 struct msm_display_topology topology;
962 struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
963 struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
964 int num_lm = 0, num_ctl = 0;
965 int i, j, ret;
966
967 if (!drm_enc) {
968 DPU_ERROR("invalid encoder\n");
969 return;
970 }
971
972 dpu_enc = to_dpu_encoder_virt(drm_enc);
973 DPU_DEBUG_ENC(dpu_enc, "\n");
974
975 priv = drm_enc->dev->dev_private;
976 dpu_kms = to_dpu_kms(priv->kms);
977 connector_list = &dpu_kms->dev->mode_config.connector_list;
978
979 trace_dpu_enc_mode_set(DRMID(drm_enc));
980
981 list_for_each_entry(conn_iter, connector_list, head)
982 if (conn_iter->encoder == drm_enc)
983 conn = conn_iter;
984
985 if (!conn) {
986 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
987 return;
988 } else if (!conn->state) {
989 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
990 return;
991 }
992
993 drm_for_each_crtc(drm_crtc, drm_enc->dev)
994 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
995 break;
996
997 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
998
999 /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
1000 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_crtc->state,
1001 topology, false);
1002 if (ret) {
1003 DPU_ERROR_ENC(dpu_enc,
1004 "failed to reserve hw resources, %d\n", ret);
1005 return;
1006 }
1007
1008 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
1009 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1010 dpu_enc->hw_pp[i] = NULL;
1011 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1012 break;
1013 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw;
1014 }
1015
1016 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
1017 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1018 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1019 break;
1020 hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw;
1021 num_ctl++;
1022 }
1023
1024 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_LM);
1025 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1026 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1027 break;
1028 hw_lm[i] = (struct dpu_hw_mixer *)hw_iter.hw;
1029 num_lm++;
1030 }
1031
1032 cstate = to_dpu_crtc_state(drm_crtc->state);
1033
1034 for (i = 0; i < num_lm; i++) {
1035 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1036
1037 cstate->mixers[i].hw_lm = hw_lm[i];
1038 cstate->mixers[i].lm_ctl = hw_ctl[ctl_idx];
1039 }
1040
1041 cstate->num_mixers = num_lm;
1042
1043 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1044 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1045
1046 if (!dpu_enc->hw_pp[i]) {
1047 DPU_ERROR_ENC(dpu_enc,
1048 "no pp block assigned at idx: %d\n", i);
1049 goto error;
1050 }
1051
1052 if (!hw_ctl[i]) {
1053 DPU_ERROR_ENC(dpu_enc,
1054 "no ctl block assigned at idx: %d\n", i);
1055 goto error;
1056 }
1057
1058 phys->hw_pp = dpu_enc->hw_pp[i];
1059 phys->hw_ctl = hw_ctl[i];
1060
1061 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id,
1062 DPU_HW_BLK_INTF);
1063 for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {
1064 struct dpu_hw_intf *hw_intf;
1065
1066 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1067 break;
1068
1069 hw_intf = (struct dpu_hw_intf *)hw_iter.hw;
1070 if (hw_intf->idx == phys->intf_idx)
1071 phys->hw_intf = hw_intf;
1072 }
1073
1074 if (!phys->hw_intf) {
1075 DPU_ERROR_ENC(dpu_enc,
1076 "no intf block assigned at idx: %d\n", i);
1077 goto error;
1078 }
1079
1080 phys->connector = conn->state->connector;
1081 if (phys->ops.mode_set)
1082 phys->ops.mode_set(phys, mode, adj_mode);
1083 }
1084
1085 dpu_enc->mode_set_complete = true;
1086
1087 error:
1088 dpu_rm_release(&dpu_kms->rm, drm_enc);
1089 }
1090
1091 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1092 {
1093 struct dpu_encoder_virt *dpu_enc = NULL;
1094 struct msm_drm_private *priv;
1095 struct dpu_kms *dpu_kms;
1096
1097 if (!drm_enc || !drm_enc->dev) {
1098 DPU_ERROR("invalid parameters\n");
1099 return;
1100 }
1101
1102 priv = drm_enc->dev->dev_private;
1103 dpu_kms = to_dpu_kms(priv->kms);
1104
1105 dpu_enc = to_dpu_encoder_virt(drm_enc);
1106 if (!dpu_enc || !dpu_enc->cur_master) {
1107 DPU_ERROR("invalid dpu encoder/master\n");
1108 return;
1109 }
1110
1111 if (dpu_enc->cur_master->hw_mdptop &&
1112 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1113 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1114 dpu_enc->cur_master->hw_mdptop,
1115 dpu_kms->catalog);
1116
1117 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1118 }
1119
1120 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1121 {
1122 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1123
1124 mutex_lock(&dpu_enc->enc_lock);
1125
1126 if (!dpu_enc->enabled)
1127 goto out;
1128
1129 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1130 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1131 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1132 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1133
1134 _dpu_encoder_virt_enable_helper(drm_enc);
1135
1136 out:
1137 mutex_unlock(&dpu_enc->enc_lock);
1138 }
1139
1140 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1141 {
1142 struct dpu_encoder_virt *dpu_enc = NULL;
1143 int ret = 0;
1144 struct drm_display_mode *cur_mode = NULL;
1145
1146 if (!drm_enc) {
1147 DPU_ERROR("invalid encoder\n");
1148 return;
1149 }
1150 dpu_enc = to_dpu_encoder_virt(drm_enc);
1151
1152 mutex_lock(&dpu_enc->enc_lock);
1153 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1154
1155 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1156 cur_mode->vdisplay);
1157
1158 /* always enable slave encoder before master */
1159 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1160 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1161
1162 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1163 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1164
1165 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1166 if (ret) {
1167 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1168 ret);
1169 goto out;
1170 }
1171
1172 _dpu_encoder_virt_enable_helper(drm_enc);
1173
1174 dpu_enc->enabled = true;
1175
1176 out:
1177 mutex_unlock(&dpu_enc->enc_lock);
1178 }
1179
1180 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1181 {
1182 struct dpu_encoder_virt *dpu_enc = NULL;
1183 struct msm_drm_private *priv;
1184 struct dpu_kms *dpu_kms;
1185 int i = 0;
1186
1187 if (!drm_enc) {
1188 DPU_ERROR("invalid encoder\n");
1189 return;
1190 } else if (!drm_enc->dev) {
1191 DPU_ERROR("invalid dev\n");
1192 return;
1193 }
1194
1195 dpu_enc = to_dpu_encoder_virt(drm_enc);
1196 DPU_DEBUG_ENC(dpu_enc, "\n");
1197
1198 mutex_lock(&dpu_enc->enc_lock);
1199 dpu_enc->enabled = false;
1200
1201 priv = drm_enc->dev->dev_private;
1202 dpu_kms = to_dpu_kms(priv->kms);
1203
1204 trace_dpu_enc_disable(DRMID(drm_enc));
1205
1206 /* wait for idle */
1207 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1208
1209 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1210
1211 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1212 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1213
1214 if (phys->ops.disable)
1215 phys->ops.disable(phys);
1216 }
1217
1218 /* after phys waits for frame-done, should be no more frames pending */
1219 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1220 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1221 del_timer_sync(&dpu_enc->frame_done_timer);
1222 }
1223
1224 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1225
1226 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1227 dpu_enc->phys_encs[i]->connector = NULL;
1228 }
1229
1230 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1231
1232 dpu_rm_release(&dpu_kms->rm, drm_enc);
1233
1234 mutex_unlock(&dpu_enc->enc_lock);
1235 }
1236
1237 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1238 enum dpu_intf_type type, u32 controller_id)
1239 {
1240 int i = 0;
1241
1242 for (i = 0; i < catalog->intf_count; i++) {
1243 if (catalog->intf[i].type == type
1244 && catalog->intf[i].controller_id == controller_id) {
1245 return catalog->intf[i].id;
1246 }
1247 }
1248
1249 return INTF_MAX;
1250 }
1251
1252 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1253 struct dpu_encoder_phys *phy_enc)
1254 {
1255 struct dpu_encoder_virt *dpu_enc = NULL;
1256 unsigned long lock_flags;
1257
1258 if (!drm_enc || !phy_enc)
1259 return;
1260
1261 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1262 dpu_enc = to_dpu_encoder_virt(drm_enc);
1263
1264 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1265 if (dpu_enc->crtc)
1266 dpu_crtc_vblank_callback(dpu_enc->crtc);
1267 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1268
1269 atomic_inc(&phy_enc->vsync_cnt);
1270 DPU_ATRACE_END("encoder_vblank_callback");
1271 }
1272
1273 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1274 struct dpu_encoder_phys *phy_enc)
1275 {
1276 if (!phy_enc)
1277 return;
1278
1279 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1280 atomic_inc(&phy_enc->underrun_cnt);
1281 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1282 atomic_read(&phy_enc->underrun_cnt));
1283 DPU_ATRACE_END("encoder_underrun_callback");
1284 }
1285
1286 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1287 {
1288 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1289 unsigned long lock_flags;
1290
1291 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1292 /* crtc should always be cleared before re-assigning */
1293 WARN_ON(crtc && dpu_enc->crtc);
1294 dpu_enc->crtc = crtc;
1295 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1296 }
1297
1298 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1299 struct drm_crtc *crtc, bool enable)
1300 {
1301 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1302 unsigned long lock_flags;
1303 int i;
1304
1305 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1306
1307 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1308 if (dpu_enc->crtc != crtc) {
1309 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1310 return;
1311 }
1312 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1313
1314 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1315 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1316
1317 if (phys->ops.control_vblank_irq)
1318 phys->ops.control_vblank_irq(phys, enable);
1319 }
1320 }
1321
1322 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1323 void (*frame_event_cb)(void *, u32 event),
1324 void *frame_event_cb_data)
1325 {
1326 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1327 unsigned long lock_flags;
1328 bool enable;
1329
1330 enable = frame_event_cb ? true : false;
1331
1332 if (!drm_enc) {
1333 DPU_ERROR("invalid encoder\n");
1334 return;
1335 }
1336 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1337
1338 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1339 dpu_enc->crtc_frame_event_cb = frame_event_cb;
1340 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1341 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1342 }
1343
1344 static void dpu_encoder_frame_done_callback(
1345 struct drm_encoder *drm_enc,
1346 struct dpu_encoder_phys *ready_phys, u32 event)
1347 {
1348 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1349 unsigned int i;
1350
1351 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1352 | DPU_ENCODER_FRAME_EVENT_ERROR
1353 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1354
1355 if (!dpu_enc->frame_busy_mask[0]) {
1356 /**
1357 * suppress frame_done without waiter,
1358 * likely autorefresh
1359 */
1360 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1361 event, ready_phys->intf_idx);
1362 return;
1363 }
1364
1365 /* One of the physical encoders has become idle */
1366 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1367 if (dpu_enc->phys_encs[i] == ready_phys) {
1368 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1369 dpu_enc->frame_busy_mask[0]);
1370 clear_bit(i, dpu_enc->frame_busy_mask);
1371 }
1372 }
1373
1374 if (!dpu_enc->frame_busy_mask[0]) {
1375 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1376 del_timer(&dpu_enc->frame_done_timer);
1377
1378 dpu_encoder_resource_control(drm_enc,
1379 DPU_ENC_RC_EVENT_FRAME_DONE);
1380
1381 if (dpu_enc->crtc_frame_event_cb)
1382 dpu_enc->crtc_frame_event_cb(
1383 dpu_enc->crtc_frame_event_cb_data,
1384 event);
1385 }
1386 } else {
1387 if (dpu_enc->crtc_frame_event_cb)
1388 dpu_enc->crtc_frame_event_cb(
1389 dpu_enc->crtc_frame_event_cb_data, event);
1390 }
1391 }
1392
1393 static void dpu_encoder_off_work(struct work_struct *work)
1394 {
1395 struct dpu_encoder_virt *dpu_enc = container_of(work,
1396 struct dpu_encoder_virt, delayed_off_work.work);
1397
1398 if (!dpu_enc) {
1399 DPU_ERROR("invalid dpu encoder\n");
1400 return;
1401 }
1402
1403 dpu_encoder_resource_control(&dpu_enc->base,
1404 DPU_ENC_RC_EVENT_ENTER_IDLE);
1405
1406 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1407 DPU_ENCODER_FRAME_EVENT_IDLE);
1408 }
1409
1410 /**
1411 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1412 * drm_enc: Pointer to drm encoder structure
1413 * phys: Pointer to physical encoder structure
1414 * extra_flush_bits: Additional bit mask to include in flush trigger
1415 */
1416 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1417 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1418 {
1419 struct dpu_hw_ctl *ctl;
1420 int pending_kickoff_cnt;
1421 u32 ret = UINT_MAX;
1422
1423 if (!phys->hw_pp) {
1424 DPU_ERROR("invalid pingpong hw\n");
1425 return;
1426 }
1427
1428 ctl = phys->hw_ctl;
1429 if (!ctl->ops.trigger_flush) {
1430 DPU_ERROR("missing trigger cb\n");
1431 return;
1432 }
1433
1434 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1435
1436 if (extra_flush_bits && ctl->ops.update_pending_flush)
1437 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1438
1439 ctl->ops.trigger_flush(ctl);
1440
1441 if (ctl->ops.get_pending_flush)
1442 ret = ctl->ops.get_pending_flush(ctl);
1443
1444 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1445 pending_kickoff_cnt, ctl->idx,
1446 extra_flush_bits, ret);
1447 }
1448
1449 /**
1450 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1451 * phys: Pointer to physical encoder structure
1452 */
1453 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1454 {
1455 if (!phys) {
1456 DPU_ERROR("invalid argument(s)\n");
1457 return;
1458 }
1459
1460 if (!phys->hw_pp) {
1461 DPU_ERROR("invalid pingpong hw\n");
1462 return;
1463 }
1464
1465 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1466 phys->ops.trigger_start(phys);
1467 }
1468
1469 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1470 {
1471 struct dpu_hw_ctl *ctl;
1472
1473 ctl = phys_enc->hw_ctl;
1474 if (ctl->ops.trigger_start) {
1475 ctl->ops.trigger_start(ctl);
1476 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1477 }
1478 }
1479
1480 static int dpu_encoder_helper_wait_event_timeout(
1481 int32_t drm_id,
1482 int32_t hw_id,
1483 struct dpu_encoder_wait_info *info)
1484 {
1485 int rc = 0;
1486 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1487 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1488 s64 time;
1489
1490 do {
1491 rc = wait_event_timeout(*(info->wq),
1492 atomic_read(info->atomic_cnt) == 0, jiffies);
1493 time = ktime_to_ms(ktime_get());
1494
1495 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1496 expected_time,
1497 atomic_read(info->atomic_cnt));
1498 /* If we timed out, counter is valid and time is less, wait again */
1499 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1500 (time < expected_time));
1501
1502 return rc;
1503 }
1504
1505 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1506 {
1507 struct dpu_encoder_virt *dpu_enc;
1508 struct dpu_hw_ctl *ctl;
1509 int rc;
1510
1511 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1512 ctl = phys_enc->hw_ctl;
1513
1514 if (!ctl->ops.reset)
1515 return;
1516
1517 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1518 ctl->idx);
1519
1520 rc = ctl->ops.reset(ctl);
1521 if (rc)
1522 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1523
1524 phys_enc->enable_state = DPU_ENC_ENABLED;
1525 }
1526
1527 /**
1528 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1529 * Iterate through the physical encoders and perform consolidated flush
1530 * and/or control start triggering as needed. This is done in the virtual
1531 * encoder rather than the individual physical ones in order to handle
1532 * use cases that require visibility into multiple physical encoders at
1533 * a time.
1534 * dpu_enc: Pointer to virtual encoder structure
1535 */
1536 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1537 {
1538 struct dpu_hw_ctl *ctl;
1539 uint32_t i, pending_flush;
1540 unsigned long lock_flags;
1541
1542 pending_flush = 0x0;
1543
1544 /* update pending counts and trigger kickoff ctl flush atomically */
1545 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1546
1547 /* don't perform flush/start operations for slave encoders */
1548 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1549 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1550
1551 if (phys->enable_state == DPU_ENC_DISABLED)
1552 continue;
1553
1554 ctl = phys->hw_ctl;
1555
1556 /*
1557 * This is cleared in frame_done worker, which isn't invoked
1558 * for async commits. So don't set this for async, since it'll
1559 * roll over to the next commit.
1560 */
1561 if (phys->split_role != ENC_ROLE_SLAVE)
1562 set_bit(i, dpu_enc->frame_busy_mask);
1563
1564 if (!phys->ops.needs_single_flush ||
1565 !phys->ops.needs_single_flush(phys))
1566 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1567 else if (ctl->ops.get_pending_flush)
1568 pending_flush |= ctl->ops.get_pending_flush(ctl);
1569 }
1570
1571 /* for split flush, combine pending flush masks and send to master */
1572 if (pending_flush && dpu_enc->cur_master) {
1573 _dpu_encoder_trigger_flush(
1574 &dpu_enc->base,
1575 dpu_enc->cur_master,
1576 pending_flush);
1577 }
1578
1579 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1580
1581 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1582 }
1583
1584 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1585 {
1586 struct dpu_encoder_virt *dpu_enc;
1587 struct dpu_encoder_phys *phys;
1588 unsigned int i;
1589 struct dpu_hw_ctl *ctl;
1590 struct msm_display_info *disp_info;
1591
1592 if (!drm_enc) {
1593 DPU_ERROR("invalid encoder\n");
1594 return;
1595 }
1596 dpu_enc = to_dpu_encoder_virt(drm_enc);
1597 disp_info = &dpu_enc->disp_info;
1598
1599 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1600 phys = dpu_enc->phys_encs[i];
1601
1602 ctl = phys->hw_ctl;
1603 if (ctl->ops.clear_pending_flush)
1604 ctl->ops.clear_pending_flush(ctl);
1605
1606 /* update only for command mode primary ctl */
1607 if ((phys == dpu_enc->cur_master) &&
1608 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1609 && ctl->ops.trigger_pending)
1610 ctl->ops.trigger_pending(ctl);
1611 }
1612 }
1613
1614 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1615 struct drm_display_mode *mode)
1616 {
1617 u64 pclk_rate;
1618 u32 pclk_period;
1619 u32 line_time;
1620
1621 /*
1622 * For linetime calculation, only operate on master encoder.
1623 */
1624 if (!dpu_enc->cur_master)
1625 return 0;
1626
1627 if (!dpu_enc->cur_master->ops.get_line_count) {
1628 DPU_ERROR("get_line_count function not defined\n");
1629 return 0;
1630 }
1631
1632 pclk_rate = mode->clock; /* pixel clock in kHz */
1633 if (pclk_rate == 0) {
1634 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1635 return 0;
1636 }
1637
1638 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1639 if (pclk_period == 0) {
1640 DPU_ERROR("pclk period is 0\n");
1641 return 0;
1642 }
1643
1644 /*
1645 * Line time calculation based on Pixel clock and HTOTAL.
1646 * Final unit is in ns.
1647 */
1648 line_time = (pclk_period * mode->htotal) / 1000;
1649 if (line_time == 0) {
1650 DPU_ERROR("line time calculation is 0\n");
1651 return 0;
1652 }
1653
1654 DPU_DEBUG_ENC(dpu_enc,
1655 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1656 pclk_rate, pclk_period, line_time);
1657
1658 return line_time;
1659 }
1660
1661 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1662 {
1663 struct drm_display_mode *mode;
1664 struct dpu_encoder_virt *dpu_enc;
1665 u32 cur_line;
1666 u32 line_time;
1667 u32 vtotal, time_to_vsync;
1668 ktime_t cur_time;
1669
1670 dpu_enc = to_dpu_encoder_virt(drm_enc);
1671
1672 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1673 DPU_ERROR("crtc/crtc state object is NULL\n");
1674 return -EINVAL;
1675 }
1676 mode = &drm_enc->crtc->state->adjusted_mode;
1677
1678 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1679 if (!line_time)
1680 return -EINVAL;
1681
1682 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1683
1684 vtotal = mode->vtotal;
1685 if (cur_line >= vtotal)
1686 time_to_vsync = line_time * vtotal;
1687 else
1688 time_to_vsync = line_time * (vtotal - cur_line);
1689
1690 if (time_to_vsync == 0) {
1691 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1692 vtotal);
1693 return -EINVAL;
1694 }
1695
1696 cur_time = ktime_get();
1697 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1698
1699 DPU_DEBUG_ENC(dpu_enc,
1700 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1701 cur_line, vtotal, time_to_vsync,
1702 ktime_to_ms(cur_time),
1703 ktime_to_ms(*wakeup_time));
1704 return 0;
1705 }
1706
1707 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1708 {
1709 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1710 vsync_event_timer);
1711 struct drm_encoder *drm_enc = &dpu_enc->base;
1712 struct msm_drm_private *priv;
1713 struct msm_drm_thread *event_thread;
1714
1715 if (!drm_enc->dev || !drm_enc->crtc) {
1716 DPU_ERROR("invalid parameters\n");
1717 return;
1718 }
1719
1720 priv = drm_enc->dev->dev_private;
1721
1722 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1723 DPU_ERROR("invalid crtc index\n");
1724 return;
1725 }
1726 event_thread = &priv->event_thread[drm_enc->crtc->index];
1727 if (!event_thread) {
1728 DPU_ERROR("event_thread not found for crtc:%d\n",
1729 drm_enc->crtc->index);
1730 return;
1731 }
1732
1733 del_timer(&dpu_enc->vsync_event_timer);
1734 }
1735
1736 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1737 {
1738 struct dpu_encoder_virt *dpu_enc = container_of(work,
1739 struct dpu_encoder_virt, vsync_event_work);
1740 ktime_t wakeup_time;
1741
1742 if (!dpu_enc) {
1743 DPU_ERROR("invalid dpu encoder\n");
1744 return;
1745 }
1746
1747 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1748 return;
1749
1750 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1751 mod_timer(&dpu_enc->vsync_event_timer,
1752 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1753 }
1754
1755 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1756 {
1757 struct dpu_encoder_virt *dpu_enc;
1758 struct dpu_encoder_phys *phys;
1759 bool needs_hw_reset = false;
1760 unsigned int i;
1761
1762 dpu_enc = to_dpu_encoder_virt(drm_enc);
1763
1764 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1765
1766 /* prepare for next kickoff, may include waiting on previous kickoff */
1767 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1768 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1769 phys = dpu_enc->phys_encs[i];
1770 if (phys->ops.prepare_for_kickoff)
1771 phys->ops.prepare_for_kickoff(phys);
1772 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1773 needs_hw_reset = true;
1774 }
1775 DPU_ATRACE_END("enc_prepare_for_kickoff");
1776
1777 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1778
1779 /* if any phys needs reset, reset all phys, in-order */
1780 if (needs_hw_reset) {
1781 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1782 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1783 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1784 }
1785 }
1786 }
1787
1788 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1789 {
1790 struct dpu_encoder_virt *dpu_enc;
1791 struct dpu_encoder_phys *phys;
1792 ktime_t wakeup_time;
1793 unsigned long timeout_ms;
1794 unsigned int i;
1795
1796 DPU_ATRACE_BEGIN("encoder_kickoff");
1797 dpu_enc = to_dpu_encoder_virt(drm_enc);
1798
1799 trace_dpu_enc_kickoff(DRMID(drm_enc));
1800
1801 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1802 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1803
1804 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1805 mod_timer(&dpu_enc->frame_done_timer,
1806 jiffies + msecs_to_jiffies(timeout_ms));
1807
1808 /* All phys encs are ready to go, trigger the kickoff */
1809 _dpu_encoder_kickoff_phys(dpu_enc);
1810
1811 /* allow phys encs to handle any post-kickoff business */
1812 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1813 phys = dpu_enc->phys_encs[i];
1814 if (phys->ops.handle_post_kickoff)
1815 phys->ops.handle_post_kickoff(phys);
1816 }
1817
1818 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1819 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1820 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1821 ktime_to_ms(wakeup_time));
1822 mod_timer(&dpu_enc->vsync_event_timer,
1823 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1824 }
1825
1826 DPU_ATRACE_END("encoder_kickoff");
1827 }
1828
1829 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1830 {
1831 struct dpu_encoder_virt *dpu_enc;
1832 struct dpu_encoder_phys *phys;
1833 int i;
1834
1835 if (!drm_enc) {
1836 DPU_ERROR("invalid encoder\n");
1837 return;
1838 }
1839 dpu_enc = to_dpu_encoder_virt(drm_enc);
1840
1841 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1842 phys = dpu_enc->phys_encs[i];
1843 if (phys->ops.prepare_commit)
1844 phys->ops.prepare_commit(phys);
1845 }
1846 }
1847
1848 #ifdef CONFIG_DEBUG_FS
1849 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1850 {
1851 struct dpu_encoder_virt *dpu_enc = s->private;
1852 int i;
1853
1854 mutex_lock(&dpu_enc->enc_lock);
1855 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1856 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1857
1858 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
1859 phys->intf_idx - INTF_0,
1860 atomic_read(&phys->vsync_cnt),
1861 atomic_read(&phys->underrun_cnt));
1862
1863 switch (phys->intf_mode) {
1864 case INTF_MODE_VIDEO:
1865 seq_puts(s, "mode: video\n");
1866 break;
1867 case INTF_MODE_CMD:
1868 seq_puts(s, "mode: command\n");
1869 break;
1870 default:
1871 seq_puts(s, "mode: ???\n");
1872 break;
1873 }
1874 }
1875 mutex_unlock(&dpu_enc->enc_lock);
1876
1877 return 0;
1878 }
1879
1880 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1881 struct file *file)
1882 {
1883 return single_open(file, _dpu_encoder_status_show, inode->i_private);
1884 }
1885
1886 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1887 {
1888 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1889 int i;
1890
1891 static const struct file_operations debugfs_status_fops = {
1892 .open = _dpu_encoder_debugfs_status_open,
1893 .read = seq_read,
1894 .llseek = seq_lseek,
1895 .release = single_release,
1896 };
1897
1898 char name[DPU_NAME_SIZE];
1899
1900 if (!drm_enc->dev) {
1901 DPU_ERROR("invalid encoder or kms\n");
1902 return -EINVAL;
1903 }
1904
1905 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1906
1907 /* create overall sub-directory for the encoder */
1908 dpu_enc->debugfs_root = debugfs_create_dir(name,
1909 drm_enc->dev->primary->debugfs_root);
1910
1911 /* don't error check these */
1912 debugfs_create_file("status", 0600,
1913 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1914
1915 for (i = 0; i < dpu_enc->num_phys_encs; i++)
1916 if (dpu_enc->phys_encs[i]->ops.late_register)
1917 dpu_enc->phys_encs[i]->ops.late_register(
1918 dpu_enc->phys_encs[i],
1919 dpu_enc->debugfs_root);
1920
1921 return 0;
1922 }
1923 #else
1924 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1925 {
1926 return 0;
1927 }
1928 #endif
1929
1930 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1931 {
1932 return _dpu_encoder_init_debugfs(encoder);
1933 }
1934
1935 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1936 {
1937 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1938
1939 debugfs_remove_recursive(dpu_enc->debugfs_root);
1940 }
1941
1942 static int dpu_encoder_virt_add_phys_encs(
1943 u32 display_caps,
1944 struct dpu_encoder_virt *dpu_enc,
1945 struct dpu_enc_phys_init_params *params)
1946 {
1947 struct dpu_encoder_phys *enc = NULL;
1948
1949 DPU_DEBUG_ENC(dpu_enc, "\n");
1950
1951 /*
1952 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1953 * in this function, check up-front.
1954 */
1955 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1956 ARRAY_SIZE(dpu_enc->phys_encs)) {
1957 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1958 dpu_enc->num_phys_encs);
1959 return -EINVAL;
1960 }
1961
1962 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1963 enc = dpu_encoder_phys_vid_init(params);
1964
1965 if (IS_ERR_OR_NULL(enc)) {
1966 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1967 PTR_ERR(enc));
1968 return enc == 0 ? -EINVAL : PTR_ERR(enc);
1969 }
1970
1971 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1972 ++dpu_enc->num_phys_encs;
1973 }
1974
1975 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1976 enc = dpu_encoder_phys_cmd_init(params);
1977
1978 if (IS_ERR_OR_NULL(enc)) {
1979 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1980 PTR_ERR(enc));
1981 return enc == 0 ? -EINVAL : PTR_ERR(enc);
1982 }
1983
1984 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1985 ++dpu_enc->num_phys_encs;
1986 }
1987
1988 if (params->split_role == ENC_ROLE_SLAVE)
1989 dpu_enc->cur_slave = enc;
1990 else
1991 dpu_enc->cur_master = enc;
1992
1993 return 0;
1994 }
1995
1996 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
1997 .handle_vblank_virt = dpu_encoder_vblank_callback,
1998 .handle_underrun_virt = dpu_encoder_underrun_callback,
1999 .handle_frame_done = dpu_encoder_frame_done_callback,
2000 };
2001
2002 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2003 struct dpu_kms *dpu_kms,
2004 struct msm_display_info *disp_info)
2005 {
2006 int ret = 0;
2007 int i = 0;
2008 enum dpu_intf_type intf_type;
2009 struct dpu_enc_phys_init_params phys_params;
2010
2011 if (!dpu_enc) {
2012 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != 0);
2013 return -EINVAL;
2014 }
2015
2016 dpu_enc->cur_master = NULL;
2017
2018 memset(&phys_params, 0, sizeof(phys_params));
2019 phys_params.dpu_kms = dpu_kms;
2020 phys_params.parent = &dpu_enc->base;
2021 phys_params.parent_ops = &dpu_encoder_parent_ops;
2022 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2023
2024 DPU_DEBUG("\n");
2025
2026 switch (disp_info->intf_type) {
2027 case DRM_MODE_ENCODER_DSI:
2028 intf_type = INTF_DSI;
2029 break;
2030 default:
2031 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2032 return -EINVAL;
2033 }
2034
2035 WARN_ON(disp_info->num_of_h_tiles < 1);
2036
2037 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2038
2039 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2040 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2041 dpu_enc->idle_pc_supported =
2042 dpu_kms->catalog->caps->has_idle_pc;
2043
2044 mutex_lock(&dpu_enc->enc_lock);
2045 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2046 /*
2047 * Left-most tile is at index 0, content is controller id
2048 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2049 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2050 */
2051 u32 controller_id = disp_info->h_tile_instance[i];
2052
2053 if (disp_info->num_of_h_tiles > 1) {
2054 if (i == 0)
2055 phys_params.split_role = ENC_ROLE_MASTER;
2056 else
2057 phys_params.split_role = ENC_ROLE_SLAVE;
2058 } else {
2059 phys_params.split_role = ENC_ROLE_SOLO;
2060 }
2061
2062 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2063 i, controller_id, phys_params.split_role);
2064
2065 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2066 intf_type,
2067 controller_id);
2068 if (phys_params.intf_idx == INTF_MAX) {
2069 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2070 intf_type, controller_id);
2071 ret = -EINVAL;
2072 }
2073
2074 if (!ret) {
2075 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2076 dpu_enc,
2077 &phys_params);
2078 if (ret)
2079 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2080 }
2081 }
2082
2083 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2084 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2085 atomic_set(&phys->vsync_cnt, 0);
2086 atomic_set(&phys->underrun_cnt, 0);
2087 }
2088 mutex_unlock(&dpu_enc->enc_lock);
2089
2090 return ret;
2091 }
2092
2093 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2094 {
2095 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2096 frame_done_timer);
2097 struct drm_encoder *drm_enc = &dpu_enc->base;
2098 u32 event;
2099
2100 if (!drm_enc->dev) {
2101 DPU_ERROR("invalid parameters\n");
2102 return;
2103 }
2104
2105 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2106 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2107 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2108 return;
2109 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2110 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2111 return;
2112 }
2113
2114 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2115
2116 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2117 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2118 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2119 }
2120
2121 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2122 .mode_set = dpu_encoder_virt_mode_set,
2123 .disable = dpu_encoder_virt_disable,
2124 .enable = dpu_kms_encoder_enable,
2125 .atomic_check = dpu_encoder_virt_atomic_check,
2126
2127 /* This is called by dpu_kms_encoder_enable */
2128 .commit = dpu_encoder_virt_enable,
2129 };
2130
2131 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2132 .destroy = dpu_encoder_destroy,
2133 .late_register = dpu_encoder_late_register,
2134 .early_unregister = dpu_encoder_early_unregister,
2135 };
2136
2137 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2138 struct msm_display_info *disp_info)
2139 {
2140 struct msm_drm_private *priv = dev->dev_private;
2141 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2142 struct drm_encoder *drm_enc = NULL;
2143 struct dpu_encoder_virt *dpu_enc = NULL;
2144 int ret = 0;
2145
2146 dpu_enc = to_dpu_encoder_virt(enc);
2147
2148 mutex_init(&dpu_enc->enc_lock);
2149 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2150 if (ret)
2151 goto fail;
2152
2153 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2154 timer_setup(&dpu_enc->frame_done_timer,
2155 dpu_encoder_frame_done_timeout, 0);
2156
2157 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2158 timer_setup(&dpu_enc->vsync_event_timer,
2159 dpu_encoder_vsync_event_handler,
2160 0);
2161
2162
2163 mutex_init(&dpu_enc->rc_lock);
2164 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2165 dpu_encoder_off_work);
2166 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2167
2168 kthread_init_work(&dpu_enc->vsync_event_work,
2169 dpu_encoder_vsync_event_work_handler);
2170
2171 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2172
2173 DPU_DEBUG_ENC(dpu_enc, "created\n");
2174
2175 return ret;
2176
2177 fail:
2178 DPU_ERROR("failed to create encoder\n");
2179 if (drm_enc)
2180 dpu_encoder_destroy(drm_enc);
2181
2182 return ret;
2183
2184
2185 }
2186
2187 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2188 int drm_enc_mode)
2189 {
2190 struct dpu_encoder_virt *dpu_enc = NULL;
2191 int rc = 0;
2192
2193 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2194 if (!dpu_enc)
2195 return ERR_PTR(ENOMEM);
2196
2197 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2198 drm_enc_mode, NULL);
2199 if (rc) {
2200 devm_kfree(dev->dev, dpu_enc);
2201 return ERR_PTR(rc);
2202 }
2203
2204 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2205
2206 spin_lock_init(&dpu_enc->enc_spinlock);
2207 dpu_enc->enabled = false;
2208
2209 return &dpu_enc->base;
2210 }
2211
2212 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2213 enum msm_event_wait event)
2214 {
2215 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2216 struct dpu_encoder_virt *dpu_enc = NULL;
2217 int i, ret = 0;
2218
2219 if (!drm_enc) {
2220 DPU_ERROR("invalid encoder\n");
2221 return -EINVAL;
2222 }
2223 dpu_enc = to_dpu_encoder_virt(drm_enc);
2224 DPU_DEBUG_ENC(dpu_enc, "\n");
2225
2226 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2227 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2228
2229 switch (event) {
2230 case MSM_ENC_COMMIT_DONE:
2231 fn_wait = phys->ops.wait_for_commit_done;
2232 break;
2233 case MSM_ENC_TX_COMPLETE:
2234 fn_wait = phys->ops.wait_for_tx_complete;
2235 break;
2236 case MSM_ENC_VBLANK:
2237 fn_wait = phys->ops.wait_for_vblank;
2238 break;
2239 default:
2240 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2241 event);
2242 return -EINVAL;
2243 }
2244
2245 if (fn_wait) {
2246 DPU_ATRACE_BEGIN("wait_for_completion_event");
2247 ret = fn_wait(phys);
2248 DPU_ATRACE_END("wait_for_completion_event");
2249 if (ret)
2250 return ret;
2251 }
2252 }
2253
2254 return ret;
2255 }
2256
2257 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2258 {
2259 struct dpu_encoder_virt *dpu_enc = NULL;
2260
2261 if (!encoder) {
2262 DPU_ERROR("invalid encoder\n");
2263 return INTF_MODE_NONE;
2264 }
2265 dpu_enc = to_dpu_encoder_virt(encoder);
2266
2267 if (dpu_enc->cur_master)
2268 return dpu_enc->cur_master->intf_mode;
2269
2270 if (dpu_enc->num_phys_encs)
2271 return dpu_enc->phys_encs[0]->intf_mode;
2272
2273 return INTF_MODE_NONE;
2274 }
Linux with added FPC-III support