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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_hw_intf.c
blobefe9a5719c6b76c55b8a573ebddc8b5e4e0ff5ea
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_intf.h"
8 #include "dpu_kms.h"
9
10 #define INTF_TIMING_ENGINE_EN 0x000
11 #define INTF_CONFIG 0x004
12 #define INTF_HSYNC_CTL 0x008
13 #define INTF_VSYNC_PERIOD_F0 0x00C
14 #define INTF_VSYNC_PERIOD_F1 0x010
15 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
16 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
17 #define INTF_DISPLAY_V_START_F0 0x01C
18 #define INTF_DISPLAY_V_START_F1 0x020
19 #define INTF_DISPLAY_V_END_F0 0x024
20 #define INTF_DISPLAY_V_END_F1 0x028
21 #define INTF_ACTIVE_V_START_F0 0x02C
22 #define INTF_ACTIVE_V_START_F1 0x030
23 #define INTF_ACTIVE_V_END_F0 0x034
24 #define INTF_ACTIVE_V_END_F1 0x038
25 #define INTF_DISPLAY_HCTL 0x03C
26 #define INTF_ACTIVE_HCTL 0x040
27 #define INTF_BORDER_COLOR 0x044
28 #define INTF_UNDERFLOW_COLOR 0x048
29 #define INTF_HSYNC_SKEW 0x04C
30 #define INTF_POLARITY_CTL 0x050
31 #define INTF_TEST_CTL 0x054
32 #define INTF_TP_COLOR0 0x058
33 #define INTF_TP_COLOR1 0x05C
34 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
35 #define INTF_FRAME_COUNT 0x0AC
36 #define INTF_LINE_COUNT 0x0B0
37
38 #define INTF_DEFLICKER_CONFIG 0x0F0
39 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
40 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
41
42 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
43 #define INTF_PANEL_FORMAT 0x090
44 #define INTF_TPG_ENABLE 0x100
45 #define INTF_TPG_MAIN_CONTROL 0x104
46 #define INTF_TPG_VIDEO_CONFIG 0x108
47 #define INTF_TPG_COMPONENT_LIMITS 0x10C
48 #define INTF_TPG_RECTANGLE 0x110
49 #define INTF_TPG_INITIAL_VALUE 0x114
50 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
51 #define INTF_TPG_RGB_MAPPING 0x11C
52 #define INTF_PROG_FETCH_START 0x170
53 #define INTF_PROG_ROT_START 0x174
54
55 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
56 #define INTF_FRAME_COUNT 0x0AC
57 #define INTF_LINE_COUNT 0x0B0
58
59 #define INTF_MUX 0x25C
60
61 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
62 const struct dpu_mdss_cfg *m,
63 void __iomem *addr,
64 struct dpu_hw_blk_reg_map *b)
65 {
66 int i;
67
68 for (i = 0; i < m->intf_count; i++) {
69 if ((intf == m->intf[i].id) &&
70 (m->intf[i].type != INTF_NONE)) {
71 b->base_off = addr;
72 b->blk_off = m->intf[i].base;
73 b->length = m->intf[i].len;
74 b->hwversion = m->hwversion;
75 b->log_mask = DPU_DBG_MASK_INTF;
76 return &m->intf[i];
77 }
78 }
79
80 return ERR_PTR(-EINVAL);
81 }
82
83 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
84 const struct intf_timing_params *p,
85 const struct dpu_format *fmt)
86 {
87 struct dpu_hw_blk_reg_map *c = &ctx->hw;
88 u32 hsync_period, vsync_period;
89 u32 display_v_start, display_v_end;
90 u32 hsync_start_x, hsync_end_x;
91 u32 active_h_start, active_h_end;
92 u32 active_v_start, active_v_end;
93 u32 active_hctl, display_hctl, hsync_ctl;
94 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
95 u32 panel_format;
96 u32 intf_cfg;
97
98 /* read interface_cfg */
99 intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
100 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
101 p->h_front_porch;
102 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
103 p->v_front_porch;
104
105 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
106 hsync_period) + p->hsync_skew;
107 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
108 p->hsync_skew - 1;
109
110 if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
111 display_v_start += p->hsync_pulse_width + p->h_back_porch;
112 display_v_end -= p->h_front_porch;
113 }
114
115 hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
116 hsync_end_x = hsync_period - p->h_front_porch - 1;
117
118 if (p->width != p->xres) {
119 active_h_start = hsync_start_x;
120 active_h_end = active_h_start + p->xres - 1;
121 } else {
122 active_h_start = 0;
123 active_h_end = 0;
124 }
125
126 if (p->height != p->yres) {
127 active_v_start = display_v_start;
128 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
129 } else {
130 active_v_start = 0;
131 active_v_end = 0;
132 }
133
134 if (active_h_end) {
135 active_hctl = (active_h_end << 16) | active_h_start;
136 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
137 } else {
138 active_hctl = 0;
139 }
140
141 if (active_v_end)
142 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
143
144 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
145 display_hctl = (hsync_end_x << 16) | hsync_start_x;
146
147 den_polarity = 0;
148 if (ctx->cap->type == INTF_HDMI) {
149 hsync_polarity = p->yres >= 720 ? 0 : 1;
150 vsync_polarity = p->yres >= 720 ? 0 : 1;
151 } else {
152 hsync_polarity = 0;
153 vsync_polarity = 0;
154 }
155 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
156 (vsync_polarity << 1) | /* VSYNC Polarity */
157 (hsync_polarity << 0); /* HSYNC Polarity */
158
159 if (!DPU_FORMAT_IS_YUV(fmt))
160 panel_format = (fmt->bits[C0_G_Y] |
161 (fmt->bits[C1_B_Cb] << 2) |
162 (fmt->bits[C2_R_Cr] << 4) |
163 (0x21 << 8));
164 else
165 /* Interface treats all the pixel data in RGB888 format */
166 panel_format = (COLOR_8BIT |
167 (COLOR_8BIT << 2) |
168 (COLOR_8BIT << 4) |
169 (0x21 << 8));
170
171 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
172 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
173 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
174 p->vsync_pulse_width * hsync_period);
175 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
176 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
177 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
178 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
179 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
180 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
181 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
182 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
183 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
184 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
185 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
186 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
187 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
188 }
189
190 static void dpu_hw_intf_enable_timing_engine(
191 struct dpu_hw_intf *intf,
192 u8 enable)
193 {
194 struct dpu_hw_blk_reg_map *c = &intf->hw;
195 /* Note: Display interface select is handled in top block hw layer */
196 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
197 }
198
199 static void dpu_hw_intf_setup_prg_fetch(
200 struct dpu_hw_intf *intf,
201 const struct intf_prog_fetch *fetch)
202 {
203 struct dpu_hw_blk_reg_map *c = &intf->hw;
204 int fetch_enable;
205
206 /*
207 * Fetch should always be outside the active lines. If the fetching
208 * is programmed within active region, hardware behavior is unknown.
209 */
210
211 fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
212 if (fetch->enable) {
213 fetch_enable |= BIT(31);
214 DPU_REG_WRITE(c, INTF_PROG_FETCH_START,
215 fetch->fetch_start);
216 } else {
217 fetch_enable &= ~BIT(31);
218 }
219
220 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
221 }
222
223 static void dpu_hw_intf_bind_pingpong_blk(
224 struct dpu_hw_intf *intf,
225 bool enable,
226 const enum dpu_pingpong pp)
227 {
228 struct dpu_hw_blk_reg_map *c;
229 u32 mux_cfg;
230
231 if (!intf)
232 return;
233
234 c = &intf->hw;
235
236 mux_cfg = DPU_REG_READ(c, INTF_MUX);
237 mux_cfg &= ~0xf;
238
239 if (enable)
240 mux_cfg |= (pp - PINGPONG_0) & 0x7;
241 else
242 mux_cfg |= 0xf;
243
244 DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
245 }
246
247 static void dpu_hw_intf_get_status(
248 struct dpu_hw_intf *intf,
249 struct intf_status *s)
250 {
251 struct dpu_hw_blk_reg_map *c = &intf->hw;
252
253 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
254 if (s->is_en) {
255 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
256 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
257 } else {
258 s->line_count = 0;
259 s->frame_count = 0;
260 }
261 }
262
263 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
264 {
265 struct dpu_hw_blk_reg_map *c;
266
267 if (!intf)
268 return 0;
269
270 c = &intf->hw;
271
272 return DPU_REG_READ(c, INTF_LINE_COUNT);
273 }
274
275 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
276 unsigned long cap)
277 {
278 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
279 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
280 ops->get_status = dpu_hw_intf_get_status;
281 ops->enable_timing = dpu_hw_intf_enable_timing_engine;
282 ops->get_line_count = dpu_hw_intf_get_line_count;
283 if (cap & BIT(DPU_CTL_ACTIVE_CFG))
284 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
285 }
286
287 static struct dpu_hw_blk_ops dpu_hw_ops;
288
289 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
290 void __iomem *addr,
291 const struct dpu_mdss_cfg *m)
292 {
293 struct dpu_hw_intf *c;
294 const struct dpu_intf_cfg *cfg;
295
296 c = kzalloc(sizeof(*c), GFP_KERNEL);
297 if (!c)
298 return ERR_PTR(-ENOMEM);
299
300 cfg = _intf_offset(idx, m, addr, &c->hw);
301 if (IS_ERR_OR_NULL(cfg)) {
302 kfree(c);
303 pr_err("failed to create dpu_hw_intf %d\n", idx);
304 return ERR_PTR(-EINVAL);
305 }
306
307 /*
308 * Assign ops
309 */
310 c->idx = idx;
311 c->cap = cfg;
312 c->mdss = m;
313 _setup_intf_ops(&c->ops, c->cap->features);
314
315 dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
316
317 return c;
318 }
319
320 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
321 {
322 if (intf)
323 dpu_hw_blk_destroy(&intf->base);
324 kfree(intf);
325 }
326
Linux with added FPC-III support