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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / msm / disp / mdp5 / mdp5_cfg.c
blobe3c4c250238b70c63d153e432cfa3c10b8b1ef5b
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 */
5
6 #include "mdp5_kms.h"
7 #include "mdp5_cfg.h"
8
9 struct mdp5_cfg_handler {
10 int revision;
11 struct mdp5_cfg config;
12 };
13
14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
16
17 static const struct mdp5_cfg_hw msm8x74v1_config = {
18 .name = "msm8x74v1",
19 .mdp = {
20 .count = 1,
21 .caps = MDP_CAP_SMP |
22 0,
23 },
24 .smp = {
25 .mmb_count = 22,
26 .mmb_size = 4096,
27 .clients = {
28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
31 },
32 },
33 .ctl = {
34 .count = 5,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
37 },
38 .pipe_vig = {
39 .count = 3,
40 .base = { 0x01100, 0x01500, 0x01900 },
41 .caps = MDP_PIPE_CAP_HFLIP |
42 MDP_PIPE_CAP_VFLIP |
43 MDP_PIPE_CAP_SCALE |
44 MDP_PIPE_CAP_CSC |
45 0,
46 },
47 .pipe_rgb = {
48 .count = 3,
49 .base = { 0x01d00, 0x02100, 0x02500 },
50 .caps = MDP_PIPE_CAP_HFLIP |
51 MDP_PIPE_CAP_VFLIP |
52 MDP_PIPE_CAP_SCALE |
53 0,
54 },
55 .pipe_dma = {
56 .count = 2,
57 .base = { 0x02900, 0x02d00 },
58 .caps = MDP_PIPE_CAP_HFLIP |
59 MDP_PIPE_CAP_VFLIP |
60 0,
61 },
62 .lm = {
63 .count = 5,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
65 .instances = {
66 { .id = 0, .pp = 0, .dspp = 0,
67 .caps = MDP_LM_CAP_DISPLAY, },
68 { .id = 1, .pp = 1, .dspp = 1,
69 .caps = MDP_LM_CAP_DISPLAY, },
70 { .id = 2, .pp = 2, .dspp = 2,
71 .caps = MDP_LM_CAP_DISPLAY, },
72 { .id = 3, .pp = -1, .dspp = -1,
73 .caps = MDP_LM_CAP_WB },
74 { .id = 4, .pp = -1, .dspp = -1,
75 .caps = MDP_LM_CAP_WB },
76 },
77 .nb_stages = 5,
78 .max_width = 2048,
79 .max_height = 0xFFFF,
80 },
81 .dspp = {
82 .count = 3,
83 .base = { 0x04500, 0x04900, 0x04d00 },
84 },
85 .pp = {
86 .count = 3,
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
88 },
89 .intf = {
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
91 .connect = {
92 [0] = INTF_eDP,
93 [1] = INTF_DSI,
94 [2] = INTF_DSI,
95 [3] = INTF_HDMI,
96 },
97 },
98 .max_clk = 200000000,
99 };
100
101 static const struct mdp5_cfg_hw msm8x74v2_config = {
102 .name = "msm8x74",
103 .mdp = {
104 .count = 1,
105 .caps = MDP_CAP_SMP |
106 0,
107 },
108 .smp = {
109 .mmb_count = 22,
110 .mmb_size = 4096,
111 .clients = {
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
113 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
114 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
115 },
116 },
117 .ctl = {
118 .count = 5,
119 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
120 .flush_hw_mask = 0x0003ffff,
121 },
122 .pipe_vig = {
123 .count = 3,
124 .base = { 0x01100, 0x01500, 0x01900 },
125 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
126 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
127 MDP_PIPE_CAP_DECIMATION,
128 },
129 .pipe_rgb = {
130 .count = 3,
131 .base = { 0x01d00, 0x02100, 0x02500 },
132 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
133 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
134 },
135 .pipe_dma = {
136 .count = 2,
137 .base = { 0x02900, 0x02d00 },
138 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
139 },
140 .lm = {
141 .count = 5,
142 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
143 .instances = {
144 { .id = 0, .pp = 0, .dspp = 0,
145 .caps = MDP_LM_CAP_DISPLAY, },
146 { .id = 1, .pp = 1, .dspp = 1,
147 .caps = MDP_LM_CAP_DISPLAY, },
148 { .id = 2, .pp = 2, .dspp = 2,
149 .caps = MDP_LM_CAP_DISPLAY, },
150 { .id = 3, .pp = -1, .dspp = -1,
151 .caps = MDP_LM_CAP_WB, },
152 { .id = 4, .pp = -1, .dspp = -1,
153 .caps = MDP_LM_CAP_WB, },
154 },
155 .nb_stages = 5,
156 .max_width = 2048,
157 .max_height = 0xFFFF,
158 },
159 .dspp = {
160 .count = 3,
161 .base = { 0x04500, 0x04900, 0x04d00 },
162 },
163 .ad = {
164 .count = 2,
165 .base = { 0x13000, 0x13200 },
166 },
167 .pp = {
168 .count = 3,
169 .base = { 0x12c00, 0x12d00, 0x12e00 },
170 },
171 .intf = {
172 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
173 .connect = {
174 [0] = INTF_eDP,
175 [1] = INTF_DSI,
176 [2] = INTF_DSI,
177 [3] = INTF_HDMI,
178 },
179 },
180 .max_clk = 200000000,
181 };
182
183 static const struct mdp5_cfg_hw apq8084_config = {
184 .name = "apq8084",
185 .mdp = {
186 .count = 1,
187 .caps = MDP_CAP_SMP |
188 MDP_CAP_SRC_SPLIT |
189 0,
190 },
191 .smp = {
192 .mmb_count = 44,
193 .mmb_size = 8192,
194 .clients = {
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
196 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
197 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
198 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
199 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
200 },
201 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
202 .reserved = {
203 /* Two SMP blocks are statically tied to RGB pipes: */
204 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
205 },
206 },
207 .ctl = {
208 .count = 5,
209 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
210 .flush_hw_mask = 0x003fffff,
211 },
212 .pipe_vig = {
213 .count = 4,
214 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
215 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
216 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
217 MDP_PIPE_CAP_DECIMATION,
218 },
219 .pipe_rgb = {
220 .count = 4,
221 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
222 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
223 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
224 },
225 .pipe_dma = {
226 .count = 2,
227 .base = { 0x03100, 0x03500 },
228 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
229 },
230 .lm = {
231 .count = 6,
232 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
233 .instances = {
234 { .id = 0, .pp = 0, .dspp = 0,
235 .caps = MDP_LM_CAP_DISPLAY |
236 MDP_LM_CAP_PAIR, },
237 { .id = 1, .pp = 1, .dspp = 1,
238 .caps = MDP_LM_CAP_DISPLAY, },
239 { .id = 2, .pp = 2, .dspp = 2,
240 .caps = MDP_LM_CAP_DISPLAY |
241 MDP_LM_CAP_PAIR, },
242 { .id = 3, .pp = -1, .dspp = -1,
243 .caps = MDP_LM_CAP_WB, },
244 { .id = 4, .pp = -1, .dspp = -1,
245 .caps = MDP_LM_CAP_WB, },
246 { .id = 5, .pp = 3, .dspp = 3,
247 .caps = MDP_LM_CAP_DISPLAY, },
248 },
249 .nb_stages = 5,
250 .max_width = 2048,
251 .max_height = 0xFFFF,
252 },
253 .dspp = {
254 .count = 4,
255 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
256
257 },
258 .ad = {
259 .count = 3,
260 .base = { 0x13400, 0x13600, 0x13800 },
261 },
262 .pp = {
263 .count = 4,
264 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
265 },
266 .intf = {
267 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
268 .connect = {
269 [0] = INTF_eDP,
270 [1] = INTF_DSI,
271 [2] = INTF_DSI,
272 [3] = INTF_HDMI,
273 },
274 },
275 .max_clk = 320000000,
276 };
277
278 static const struct mdp5_cfg_hw msm8x16_config = {
279 .name = "msm8x16",
280 .mdp = {
281 .count = 1,
282 .base = { 0x0 },
283 .caps = MDP_CAP_SMP |
284 0,
285 },
286 .smp = {
287 .mmb_count = 8,
288 .mmb_size = 8192,
289 .clients = {
290 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
291 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
292 },
293 },
294 .ctl = {
295 .count = 5,
296 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
297 .flush_hw_mask = 0x4003ffff,
298 },
299 .pipe_vig = {
300 .count = 1,
301 .base = { 0x04000 },
302 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
303 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
304 MDP_PIPE_CAP_DECIMATION,
305 },
306 .pipe_rgb = {
307 .count = 2,
308 .base = { 0x14000, 0x16000 },
309 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
310 MDP_PIPE_CAP_DECIMATION,
311 },
312 .pipe_dma = {
313 .count = 1,
314 .base = { 0x24000 },
315 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
316 },
317 .lm = {
318 .count = 2, /* LM0 and LM3 */
319 .base = { 0x44000, 0x47000 },
320 .instances = {
321 { .id = 0, .pp = 0, .dspp = 0,
322 .caps = MDP_LM_CAP_DISPLAY, },
323 { .id = 3, .pp = -1, .dspp = -1,
324 .caps = MDP_LM_CAP_WB },
325 },
326 .nb_stages = 8,
327 .max_width = 2048,
328 .max_height = 0xFFFF,
329 },
330 .dspp = {
331 .count = 1,
332 .base = { 0x54000 },
333
334 },
335 .intf = {
336 .base = { 0x00000, 0x6a800 },
337 .connect = {
338 [0] = INTF_DISABLED,
339 [1] = INTF_DSI,
340 },
341 },
342 .max_clk = 320000000,
343 };
344
345 static const struct mdp5_cfg_hw msm8x94_config = {
346 .name = "msm8x94",
347 .mdp = {
348 .count = 1,
349 .caps = MDP_CAP_SMP |
350 MDP_CAP_SRC_SPLIT |
351 0,
352 },
353 .smp = {
354 .mmb_count = 44,
355 .mmb_size = 8192,
356 .clients = {
357 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
358 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
359 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
360 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
361 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
362 },
363 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
364 .reserved = {
365 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
366 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
367 },
368 },
369 .ctl = {
370 .count = 5,
371 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
372 .flush_hw_mask = 0xf0ffffff,
373 },
374 .pipe_vig = {
375 .count = 4,
376 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
377 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
378 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
379 MDP_PIPE_CAP_DECIMATION,
380 },
381 .pipe_rgb = {
382 .count = 4,
383 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
384 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
385 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
386 },
387 .pipe_dma = {
388 .count = 2,
389 .base = { 0x24000, 0x26000 },
390 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
391 },
392 .lm = {
393 .count = 6,
394 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
395 .instances = {
396 { .id = 0, .pp = 0, .dspp = 0,
397 .caps = MDP_LM_CAP_DISPLAY |
398 MDP_LM_CAP_PAIR, },
399 { .id = 1, .pp = 1, .dspp = 1,
400 .caps = MDP_LM_CAP_DISPLAY, },
401 { .id = 2, .pp = 2, .dspp = 2,
402 .caps = MDP_LM_CAP_DISPLAY |
403 MDP_LM_CAP_PAIR, },
404 { .id = 3, .pp = -1, .dspp = -1,
405 .caps = MDP_LM_CAP_WB, },
406 { .id = 4, .pp = -1, .dspp = -1,
407 .caps = MDP_LM_CAP_WB, },
408 { .id = 5, .pp = 3, .dspp = 3,
409 .caps = MDP_LM_CAP_DISPLAY, },
410 },
411 .nb_stages = 8,
412 .max_width = 2048,
413 .max_height = 0xFFFF,
414 },
415 .dspp = {
416 .count = 4,
417 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
418
419 },
420 .ad = {
421 .count = 3,
422 .base = { 0x78000, 0x78800, 0x79000 },
423 },
424 .pp = {
425 .count = 4,
426 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
427 },
428 .intf = {
429 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
430 .connect = {
431 [0] = INTF_DISABLED,
432 [1] = INTF_DSI,
433 [2] = INTF_DSI,
434 [3] = INTF_HDMI,
435 },
436 },
437 .max_clk = 400000000,
438 };
439
440 static const struct mdp5_cfg_hw msm8x96_config = {
441 .name = "msm8x96",
442 .mdp = {
443 .count = 1,
444 .caps = MDP_CAP_DSC |
445 MDP_CAP_CDM |
446 MDP_CAP_SRC_SPLIT |
447 0,
448 },
449 .ctl = {
450 .count = 5,
451 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
452 .flush_hw_mask = 0xf4ffffff,
453 },
454 .pipe_vig = {
455 .count = 4,
456 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
457 .caps = MDP_PIPE_CAP_HFLIP |
458 MDP_PIPE_CAP_VFLIP |
459 MDP_PIPE_CAP_SCALE |
460 MDP_PIPE_CAP_CSC |
461 MDP_PIPE_CAP_DECIMATION |
462 MDP_PIPE_CAP_SW_PIX_EXT |
463 0,
464 },
465 .pipe_rgb = {
466 .count = 4,
467 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
468 .caps = MDP_PIPE_CAP_HFLIP |
469 MDP_PIPE_CAP_VFLIP |
470 MDP_PIPE_CAP_SCALE |
471 MDP_PIPE_CAP_DECIMATION |
472 MDP_PIPE_CAP_SW_PIX_EXT |
473 0,
474 },
475 .pipe_dma = {
476 .count = 2,
477 .base = { 0x24000, 0x26000 },
478 .caps = MDP_PIPE_CAP_HFLIP |
479 MDP_PIPE_CAP_VFLIP |
480 MDP_PIPE_CAP_SW_PIX_EXT |
481 0,
482 },
483 .pipe_cursor = {
484 .count = 2,
485 .base = { 0x34000, 0x36000 },
486 .caps = MDP_PIPE_CAP_HFLIP |
487 MDP_PIPE_CAP_VFLIP |
488 MDP_PIPE_CAP_SW_PIX_EXT |
489 MDP_PIPE_CAP_CURSOR |
490 0,
491 },
492
493 .lm = {
494 .count = 6,
495 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
496 .instances = {
497 { .id = 0, .pp = 0, .dspp = 0,
498 .caps = MDP_LM_CAP_DISPLAY |
499 MDP_LM_CAP_PAIR, },
500 { .id = 1, .pp = 1, .dspp = 1,
501 .caps = MDP_LM_CAP_DISPLAY, },
502 { .id = 2, .pp = 2, .dspp = -1,
503 .caps = MDP_LM_CAP_DISPLAY |
504 MDP_LM_CAP_PAIR, },
505 { .id = 3, .pp = -1, .dspp = -1,
506 .caps = MDP_LM_CAP_WB, },
507 { .id = 4, .pp = -1, .dspp = -1,
508 .caps = MDP_LM_CAP_WB, },
509 { .id = 5, .pp = 3, .dspp = -1,
510 .caps = MDP_LM_CAP_DISPLAY, },
511 },
512 .nb_stages = 8,
513 .max_width = 2560,
514 .max_height = 0xFFFF,
515 },
516 .dspp = {
517 .count = 2,
518 .base = { 0x54000, 0x56000 },
519 },
520 .ad = {
521 .count = 3,
522 .base = { 0x78000, 0x78800, 0x79000 },
523 },
524 .pp = {
525 .count = 4,
526 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
527 },
528 .cdm = {
529 .count = 1,
530 .base = { 0x79200 },
531 },
532 .dsc = {
533 .count = 2,
534 .base = { 0x80000, 0x80400 },
535 },
536 .intf = {
537 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
538 .connect = {
539 [0] = INTF_DISABLED,
540 [1] = INTF_DSI,
541 [2] = INTF_DSI,
542 [3] = INTF_HDMI,
543 },
544 },
545 .max_clk = 412500000,
546 };
547
548 const struct mdp5_cfg_hw msm8x76_config = {
549 .name = "msm8x76",
550 .mdp = {
551 .count = 1,
552 .caps = MDP_CAP_SMP |
553 MDP_CAP_DSC |
554 MDP_CAP_SRC_SPLIT |
555 0,
556 },
557 .ctl = {
558 .count = 3,
559 .base = { 0x01000, 0x01200, 0x01400 },
560 .flush_hw_mask = 0xffffffff,
561 },
562 .smp = {
563 .mmb_count = 10,
564 .mmb_size = 10240,
565 .clients = {
566 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
567 [SSPP_DMA0] = 4,
568 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
569 },
570 },
571 .pipe_vig = {
572 .count = 2,
573 .base = { 0x04000, 0x06000 },
574 .caps = MDP_PIPE_CAP_HFLIP |
575 MDP_PIPE_CAP_VFLIP |
576 MDP_PIPE_CAP_SCALE |
577 MDP_PIPE_CAP_CSC |
578 MDP_PIPE_CAP_DECIMATION |
579 MDP_PIPE_CAP_SW_PIX_EXT |
580 0,
581 },
582 .pipe_rgb = {
583 .count = 2,
584 .base = { 0x14000, 0x16000 },
585 .caps = MDP_PIPE_CAP_HFLIP |
586 MDP_PIPE_CAP_VFLIP |
587 MDP_PIPE_CAP_DECIMATION |
588 MDP_PIPE_CAP_SW_PIX_EXT |
589 0,
590 },
591 .pipe_dma = {
592 .count = 1,
593 .base = { 0x24000 },
594 .caps = MDP_PIPE_CAP_HFLIP |
595 MDP_PIPE_CAP_VFLIP |
596 MDP_PIPE_CAP_SW_PIX_EXT |
597 0,
598 },
599 .pipe_cursor = {
600 .count = 1,
601 .base = { 0x440DC },
602 .caps = MDP_PIPE_CAP_HFLIP |
603 MDP_PIPE_CAP_VFLIP |
604 MDP_PIPE_CAP_SW_PIX_EXT |
605 MDP_PIPE_CAP_CURSOR |
606 0,
607 },
608 .lm = {
609 .count = 2,
610 .base = { 0x44000, 0x45000 },
611 .instances = {
612 { .id = 0, .pp = 0, .dspp = 0,
613 .caps = MDP_LM_CAP_DISPLAY, },
614 { .id = 1, .pp = -1, .dspp = -1,
615 .caps = MDP_LM_CAP_WB },
616 },
617 .nb_stages = 8,
618 .max_width = 2560,
619 .max_height = 0xFFFF,
620 },
621 .dspp = {
622 .count = 1,
623 .base = { 0x54000 },
624
625 },
626 .pp = {
627 .count = 3,
628 .base = { 0x70000, 0x70800, 0x72000 },
629 },
630 .dsc = {
631 .count = 2,
632 .base = { 0x80000, 0x80400 },
633 },
634 .intf = {
635 .base = { 0x6a000, 0x6a800, 0x6b000 },
636 .connect = {
637 [0] = INTF_DISABLED,
638 [1] = INTF_DSI,
639 [2] = INTF_DSI,
640 },
641 },
642 .max_clk = 360000000,
643 };
644
645 static const struct mdp5_cfg_hw msm8917_config = {
646 .name = "msm8917",
647 .mdp = {
648 .count = 1,
649 .caps = MDP_CAP_CDM,
650 },
651 .ctl = {
652 .count = 3,
653 .base = { 0x01000, 0x01200, 0x01400 },
654 .flush_hw_mask = 0xffffffff,
655 },
656 .pipe_vig = {
657 .count = 1,
658 .base = { 0x04000 },
659 .caps = MDP_PIPE_CAP_HFLIP |
660 MDP_PIPE_CAP_VFLIP |
661 MDP_PIPE_CAP_SCALE |
662 MDP_PIPE_CAP_CSC |
663 MDP_PIPE_CAP_DECIMATION |
664 MDP_PIPE_CAP_SW_PIX_EXT |
665 0,
666 },
667 .pipe_rgb = {
668 .count = 2,
669 .base = { 0x14000, 0x16000 },
670 .caps = MDP_PIPE_CAP_HFLIP |
671 MDP_PIPE_CAP_VFLIP |
672 MDP_PIPE_CAP_DECIMATION |
673 MDP_PIPE_CAP_SW_PIX_EXT |
674 0,
675 },
676 .pipe_dma = {
677 .count = 1,
678 .base = { 0x24000 },
679 .caps = MDP_PIPE_CAP_HFLIP |
680 MDP_PIPE_CAP_VFLIP |
681 MDP_PIPE_CAP_SW_PIX_EXT |
682 0,
683 },
684 .pipe_cursor = {
685 .count = 1,
686 .base = { 0x34000 },
687 .caps = MDP_PIPE_CAP_HFLIP |
688 MDP_PIPE_CAP_VFLIP |
689 MDP_PIPE_CAP_SW_PIX_EXT |
690 MDP_PIPE_CAP_CURSOR |
691 0,
692 },
693
694 .lm = {
695 .count = 2,
696 .base = { 0x44000, 0x45000 },
697 .instances = {
698 { .id = 0, .pp = 0, .dspp = 0,
699 .caps = MDP_LM_CAP_DISPLAY, },
700 { .id = 1, .pp = -1, .dspp = -1,
701 .caps = MDP_LM_CAP_WB },
702 },
703 .nb_stages = 8,
704 .max_width = 2048,
705 .max_height = 0xFFFF,
706 },
707 .dspp = {
708 .count = 1,
709 .base = { 0x54000 },
710
711 },
712 .pp = {
713 .count = 1,
714 .base = { 0x70000 },
715 },
716 .cdm = {
717 .count = 1,
718 .base = { 0x79200 },
719 },
720 .intf = {
721 .base = { 0x6a000, 0x6a800 },
722 .connect = {
723 [0] = INTF_DISABLED,
724 [1] = INTF_DSI,
725 },
726 },
727 .max_clk = 320000000,
728 };
729
730 static const struct mdp5_cfg_hw msm8998_config = {
731 .name = "msm8998",
732 .mdp = {
733 .count = 1,
734 .caps = MDP_CAP_DSC |
735 MDP_CAP_CDM |
736 MDP_CAP_SRC_SPLIT |
737 0,
738 },
739 .ctl = {
740 .count = 5,
741 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
742 .flush_hw_mask = 0xf7ffffff,
743 },
744 .pipe_vig = {
745 .count = 4,
746 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
747 .caps = MDP_PIPE_CAP_HFLIP |
748 MDP_PIPE_CAP_VFLIP |
749 MDP_PIPE_CAP_SCALE |
750 MDP_PIPE_CAP_CSC |
751 MDP_PIPE_CAP_DECIMATION |
752 MDP_PIPE_CAP_SW_PIX_EXT |
753 0,
754 },
755 .pipe_rgb = {
756 .count = 4,
757 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
758 .caps = MDP_PIPE_CAP_HFLIP |
759 MDP_PIPE_CAP_VFLIP |
760 MDP_PIPE_CAP_SCALE |
761 MDP_PIPE_CAP_DECIMATION |
762 MDP_PIPE_CAP_SW_PIX_EXT |
763 0,
764 },
765 .pipe_dma = {
766 .count = 2, /* driver supports max of 2 currently */
767 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
768 .caps = MDP_PIPE_CAP_HFLIP |
769 MDP_PIPE_CAP_VFLIP |
770 MDP_PIPE_CAP_SW_PIX_EXT |
771 0,
772 },
773 .pipe_cursor = {
774 .count = 2,
775 .base = { 0x34000, 0x36000 },
776 .caps = MDP_PIPE_CAP_HFLIP |
777 MDP_PIPE_CAP_VFLIP |
778 MDP_PIPE_CAP_SW_PIX_EXT |
779 MDP_PIPE_CAP_CURSOR |
780 0,
781 },
782
783 .lm = {
784 .count = 6,
785 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
786 .instances = {
787 { .id = 0, .pp = 0, .dspp = 0,
788 .caps = MDP_LM_CAP_DISPLAY |
789 MDP_LM_CAP_PAIR, },
790 { .id = 1, .pp = 1, .dspp = 1,
791 .caps = MDP_LM_CAP_DISPLAY, },
792 { .id = 2, .pp = 2, .dspp = -1,
793 .caps = MDP_LM_CAP_DISPLAY |
794 MDP_LM_CAP_PAIR, },
795 { .id = 3, .pp = -1, .dspp = -1,
796 .caps = MDP_LM_CAP_WB, },
797 { .id = 4, .pp = -1, .dspp = -1,
798 .caps = MDP_LM_CAP_WB, },
799 { .id = 5, .pp = 3, .dspp = -1,
800 .caps = MDP_LM_CAP_DISPLAY, },
801 },
802 .nb_stages = 8,
803 .max_width = 2560,
804 .max_height = 0xFFFF,
805 },
806 .dspp = {
807 .count = 2,
808 .base = { 0x54000, 0x56000 },
809 },
810 .ad = {
811 .count = 3,
812 .base = { 0x78000, 0x78800, 0x79000 },
813 },
814 .pp = {
815 .count = 4,
816 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
817 },
818 .cdm = {
819 .count = 1,
820 .base = { 0x79200 },
821 },
822 .dsc = {
823 .count = 2,
824 .base = { 0x80000, 0x80400 },
825 },
826 .intf = {
827 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
828 .connect = {
829 [0] = INTF_eDP,
830 [1] = INTF_DSI,
831 [2] = INTF_DSI,
832 [3] = INTF_HDMI,
833 },
834 },
835 .max_clk = 412500000,
836 };
837
838 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
839 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
840 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
841 { .revision = 3, .config = { .hw = &apq8084_config } },
842 { .revision = 6, .config = { .hw = &msm8x16_config } },
843 { .revision = 9, .config = { .hw = &msm8x94_config } },
844 { .revision = 7, .config = { .hw = &msm8x96_config } },
845 { .revision = 11, .config = { .hw = &msm8x76_config } },
846 { .revision = 15, .config = { .hw = &msm8917_config } },
847 };
848
849 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
850 { .revision = 0, .config = { .hw = &msm8998_config } },
851 };
852
853 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
854
855 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
856 {
857 return cfg_handler->config.hw;
858 }
859
860 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
861 {
862 return &cfg_handler->config;
863 }
864
865 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
866 {
867 return cfg_handler->revision;
868 }
869
870 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
871 {
872 kfree(cfg_handler);
873 }
874
875 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
876 uint32_t major, uint32_t minor)
877 {
878 struct drm_device *dev = mdp5_kms->dev;
879 struct platform_device *pdev = to_platform_device(dev->dev);
880 struct mdp5_cfg_handler *cfg_handler;
881 const struct mdp5_cfg_handler *cfg_handlers;
882 struct mdp5_cfg_platform *pconfig;
883 int i, ret = 0, num_handlers;
884
885 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
886 if (unlikely(!cfg_handler)) {
887 ret = -ENOMEM;
888 goto fail;
889 }
890
891 switch (major) {
892 case 1:
893 cfg_handlers = cfg_handlers_v1;
894 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
895 break;
896 case 3:
897 cfg_handlers = cfg_handlers_v3;
898 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
899 break;
900 default:
901 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
902 major, minor);
903 ret = -ENXIO;
904 goto fail;
905 }
906
907 /* only after mdp5_cfg global pointer's init can we access the hw */
908 for (i = 0; i < num_handlers; i++) {
909 if (cfg_handlers[i].revision != minor)
910 continue;
911 mdp5_cfg = cfg_handlers[i].config.hw;
912
913 break;
914 }
915 if (unlikely(!mdp5_cfg)) {
916 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
917 major, minor);
918 ret = -ENXIO;
919 goto fail;
920 }
921
922 cfg_handler->revision = minor;
923 cfg_handler->config.hw = mdp5_cfg;
924
925 pconfig = mdp5_get_config(pdev);
926 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
927
928 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
929
930 return cfg_handler;
931
932 fail:
933 if (cfg_handler)
934 mdp5_cfg_destroy(cfg_handler);
935
936 return ERR_PTR(ret);
937 }
938
939 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
940 {
941 static struct mdp5_cfg_platform config = {};
942
943 config.iommu = iommu_domain_alloc(&platform_bus_type);
944 if (config.iommu) {
945 config.iommu->geometry.aperture_start = 0x1000;
946 config.iommu->geometry.aperture_end = 0xffffffff;
947 }
948
949 return &config;
950 }
Linux with added FPC-III support