?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / msm / disp / mdp5 / mdp5_kms.c
blobe43ecd4be10a3e1b441c0824263042496a1869eb
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interconnect.h>
10 #include <linux/of_irq.h>
11
12 #include <drm/drm_debugfs.h>
13 #include <drm/drm_drv.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_vblank.h>
16
17 #include "msm_drv.h"
18 #include "msm_gem.h"
19 #include "msm_mmu.h"
20 #include "mdp5_kms.h"
21
22 static int mdp5_hw_init(struct msm_kms *kms)
23 {
24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
25 struct device *dev = &mdp5_kms->pdev->dev;
26 unsigned long flags;
27
28 pm_runtime_get_sync(dev);
29
30 /* Magic unknown register writes:
31 *
32 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
41 *
42 * Downstream fbdev driver gets these register offsets/values
43 * from DT.. not really sure what these registers are or if
44 * different values for different boards/SoC's, etc. I guess
45 * they are the golden registers.
46 *
47 * Not setting these does not seem to cause any problem. But
48 * we may be getting lucky with the bootloader initializing
49 * them for us. OTOH, if we can always count on the bootloader
50 * setting the golden registers, then perhaps we don't need to
51 * care.
52 */
53
54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
57
58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
59
60 pm_runtime_put_sync(dev);
61
62 return 0;
63 }
64
65 /* Global/shared object state funcs */
66
67 /*
68 * This is a helper that returns the private state currently in operation.
69 * Note that this would return the "old_state" if called in the atomic check
70 * path, and the "new_state" after the atomic swap has been done.
71 */
72 struct mdp5_global_state *
73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
74 {
75 return to_mdp5_global_state(mdp5_kms->glob_state.state);
76 }
77
78 /*
79 * This acquires the modeset lock set aside for global state, creates
80 * a new duplicated private object state.
81 */
82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
83 {
84 struct msm_drm_private *priv = s->dev->dev_private;
85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
86 struct drm_private_state *priv_state;
87 int ret;
88
89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
90 if (ret)
91 return ERR_PTR(ret);
92
93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
94 if (IS_ERR(priv_state))
95 return ERR_CAST(priv_state);
96
97 return to_mdp5_global_state(priv_state);
98 }
99
100 static struct drm_private_state *
101 mdp5_global_duplicate_state(struct drm_private_obj *obj)
102 {
103 struct mdp5_global_state *state;
104
105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
106 if (!state)
107 return NULL;
108
109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
110
111 return &state->base;
112 }
113
114 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
115 struct drm_private_state *state)
116 {
117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
118
119 kfree(mdp5_state);
120 }
121
122 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
123 .atomic_duplicate_state = mdp5_global_duplicate_state,
124 .atomic_destroy_state = mdp5_global_destroy_state,
125 };
126
127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
128 {
129 struct mdp5_global_state *state;
130
131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
132
133 state = kzalloc(sizeof(*state), GFP_KERNEL);
134 if (!state)
135 return -ENOMEM;
136
137 state->mdp5_kms = mdp5_kms;
138
139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
140 &state->base,
141 &mdp5_global_state_funcs);
142 return 0;
143 }
144
145 static void mdp5_enable_commit(struct msm_kms *kms)
146 {
147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
148 pm_runtime_get_sync(&mdp5_kms->pdev->dev);
149 }
150
151 static void mdp5_disable_commit(struct msm_kms *kms)
152 {
153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
154 pm_runtime_put_sync(&mdp5_kms->pdev->dev);
155 }
156
157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
158 {
159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
160 struct mdp5_global_state *global_state;
161
162 global_state = mdp5_get_existing_global_state(mdp5_kms);
163
164 if (mdp5_kms->smp)
165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
166 }
167
168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
169 {
170 /* TODO */
171 }
172
173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
174 {
175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
176 struct drm_crtc *crtc;
177
178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)
179 mdp5_crtc_wait_for_commit_done(crtc);
180 }
181
182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
183 {
184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
185 struct mdp5_global_state *global_state;
186
187 global_state = mdp5_get_existing_global_state(mdp5_kms);
188
189 if (mdp5_kms->smp)
190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
191 }
192
193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
194 struct drm_encoder *encoder)
195 {
196 return rate;
197 }
198
199 static int mdp5_set_split_display(struct msm_kms *kms,
200 struct drm_encoder *encoder,
201 struct drm_encoder *slave_encoder,
202 bool is_cmd_mode)
203 {
204 if (is_cmd_mode)
205 return mdp5_cmd_encoder_set_split_display(encoder,
206 slave_encoder);
207 else
208 return mdp5_vid_encoder_set_split_display(encoder,
209 slave_encoder);
210 }
211
212 static void mdp5_set_encoder_mode(struct msm_kms *kms,
213 struct drm_encoder *encoder,
214 bool cmd_mode)
215 {
216 mdp5_encoder_set_intf_mode(encoder, cmd_mode);
217 }
218
219 static void mdp5_kms_destroy(struct msm_kms *kms)
220 {
221 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
222 struct msm_gem_address_space *aspace = kms->aspace;
223 int i;
224
225 for (i = 0; i < mdp5_kms->num_hwmixers; i++)
226 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
227
228 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
229 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
230
231 if (aspace) {
232 aspace->mmu->funcs->detach(aspace->mmu);
233 msm_gem_address_space_put(aspace);
234 }
235 }
236
237 #ifdef CONFIG_DEBUG_FS
238 static int smp_show(struct seq_file *m, void *arg)
239 {
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct msm_drm_private *priv = dev->dev_private;
243 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
244 struct drm_printer p = drm_seq_file_printer(m);
245
246 if (!mdp5_kms->smp) {
247 drm_printf(&p, "no SMP pool\n");
248 return 0;
249 }
250
251 mdp5_smp_dump(mdp5_kms->smp, &p);
252
253 return 0;
254 }
255
256 static struct drm_info_list mdp5_debugfs_list[] = {
257 {"smp", smp_show },
258 };
259
260 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
261 {
262 struct drm_device *dev = minor->dev;
263 int ret;
264
265 ret = drm_debugfs_create_files(mdp5_debugfs_list,
266 ARRAY_SIZE(mdp5_debugfs_list),
267 minor->debugfs_root, minor);
268
269 if (ret) {
270 DRM_DEV_ERROR(dev->dev, "could not install mdp5_debugfs_list\n");
271 return ret;
272 }
273
274 return 0;
275 }
276 #endif
277
278 static const struct mdp_kms_funcs kms_funcs = {
279 .base = {
280 .hw_init = mdp5_hw_init,
281 .irq_preinstall = mdp5_irq_preinstall,
282 .irq_postinstall = mdp5_irq_postinstall,
283 .irq_uninstall = mdp5_irq_uninstall,
284 .irq = mdp5_irq,
285 .enable_vblank = mdp5_enable_vblank,
286 .disable_vblank = mdp5_disable_vblank,
287 .flush_commit = mdp5_flush_commit,
288 .enable_commit = mdp5_enable_commit,
289 .disable_commit = mdp5_disable_commit,
290 .prepare_commit = mdp5_prepare_commit,
291 .wait_flush = mdp5_wait_flush,
292 .complete_commit = mdp5_complete_commit,
293 .get_format = mdp_get_format,
294 .round_pixclk = mdp5_round_pixclk,
295 .set_split_display = mdp5_set_split_display,
296 .set_encoder_mode = mdp5_set_encoder_mode,
297 .destroy = mdp5_kms_destroy,
298 #ifdef CONFIG_DEBUG_FS
299 .debugfs_init = mdp5_kms_debugfs_init,
300 #endif
301 },
302 .set_irqmask = mdp5_set_irqmask,
303 };
304
305 int mdp5_disable(struct mdp5_kms *mdp5_kms)
306 {
307 DBG("");
308
309 mdp5_kms->enable_count--;
310 WARN_ON(mdp5_kms->enable_count < 0);
311
312 if (mdp5_kms->tbu_rt_clk)
313 clk_disable_unprepare(mdp5_kms->tbu_rt_clk);
314 if (mdp5_kms->tbu_clk)
315 clk_disable_unprepare(mdp5_kms->tbu_clk);
316 clk_disable_unprepare(mdp5_kms->ahb_clk);
317 clk_disable_unprepare(mdp5_kms->axi_clk);
318 clk_disable_unprepare(mdp5_kms->core_clk);
319 if (mdp5_kms->lut_clk)
320 clk_disable_unprepare(mdp5_kms->lut_clk);
321
322 return 0;
323 }
324
325 int mdp5_enable(struct mdp5_kms *mdp5_kms)
326 {
327 DBG("");
328
329 mdp5_kms->enable_count++;
330
331 clk_prepare_enable(mdp5_kms->ahb_clk);
332 clk_prepare_enable(mdp5_kms->axi_clk);
333 clk_prepare_enable(mdp5_kms->core_clk);
334 if (mdp5_kms->lut_clk)
335 clk_prepare_enable(mdp5_kms->lut_clk);
336 if (mdp5_kms->tbu_clk)
337 clk_prepare_enable(mdp5_kms->tbu_clk);
338 if (mdp5_kms->tbu_rt_clk)
339 clk_prepare_enable(mdp5_kms->tbu_rt_clk);
340
341 return 0;
342 }
343
344 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
345 struct mdp5_interface *intf,
346 struct mdp5_ctl *ctl)
347 {
348 struct drm_device *dev = mdp5_kms->dev;
349 struct msm_drm_private *priv = dev->dev_private;
350 struct drm_encoder *encoder;
351
352 encoder = mdp5_encoder_init(dev, intf, ctl);
353 if (IS_ERR(encoder)) {
354 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
355 return encoder;
356 }
357
358 priv->encoders[priv->num_encoders++] = encoder;
359
360 return encoder;
361 }
362
363 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
364 {
365 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
366 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
367 int id = 0, i;
368
369 for (i = 0; i < intf_cnt; i++) {
370 if (intfs[i] == INTF_DSI) {
371 if (intf_num == i)
372 return id;
373
374 id++;
375 }
376 }
377
378 return -EINVAL;
379 }
380
381 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
382 struct mdp5_interface *intf)
383 {
384 struct drm_device *dev = mdp5_kms->dev;
385 struct msm_drm_private *priv = dev->dev_private;
386 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
387 struct mdp5_ctl *ctl;
388 struct drm_encoder *encoder;
389 int ret = 0;
390
391 switch (intf->type) {
392 case INTF_eDP:
393 if (!priv->edp)
394 break;
395
396 ctl = mdp5_ctlm_request(ctlm, intf->num);
397 if (!ctl) {
398 ret = -EINVAL;
399 break;
400 }
401
402 encoder = construct_encoder(mdp5_kms, intf, ctl);
403 if (IS_ERR(encoder)) {
404 ret = PTR_ERR(encoder);
405 break;
406 }
407
408 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
409 break;
410 case INTF_HDMI:
411 if (!priv->hdmi)
412 break;
413
414 ctl = mdp5_ctlm_request(ctlm, intf->num);
415 if (!ctl) {
416 ret = -EINVAL;
417 break;
418 }
419
420 encoder = construct_encoder(mdp5_kms, intf, ctl);
421 if (IS_ERR(encoder)) {
422 ret = PTR_ERR(encoder);
423 break;
424 }
425
426 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
427 break;
428 case INTF_DSI:
429 {
430 const struct mdp5_cfg_hw *hw_cfg =
431 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
432 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
433
434 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
435 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
436 intf->num);
437 ret = -EINVAL;
438 break;
439 }
440
441 if (!priv->dsi[dsi_id])
442 break;
443
444 ctl = mdp5_ctlm_request(ctlm, intf->num);
445 if (!ctl) {
446 ret = -EINVAL;
447 break;
448 }
449
450 encoder = construct_encoder(mdp5_kms, intf, ctl);
451 if (IS_ERR(encoder)) {
452 ret = PTR_ERR(encoder);
453 break;
454 }
455
456 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
457 break;
458 }
459 default:
460 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
461 ret = -EINVAL;
462 break;
463 }
464
465 return ret;
466 }
467
468 static int modeset_init(struct mdp5_kms *mdp5_kms)
469 {
470 struct drm_device *dev = mdp5_kms->dev;
471 struct msm_drm_private *priv = dev->dev_private;
472 unsigned int num_crtcs;
473 int i, ret, pi = 0, ci = 0;
474 struct drm_plane *primary[MAX_BASES] = { NULL };
475 struct drm_plane *cursor[MAX_BASES] = { NULL };
476
477 /*
478 * Construct encoders and modeset initialize connector devices
479 * for each external display interface.
480 */
481 for (i = 0; i < mdp5_kms->num_intfs; i++) {
482 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
483 if (ret)
484 goto fail;
485 }
486
487 /*
488 * We should ideally have less number of encoders (set up by parsing
489 * the MDP5 interfaces) than the number of layer mixers present in HW,
490 * but let's be safe here anyway
491 */
492 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
493
494 /*
495 * Construct planes equaling the number of hw pipes, and CRTCs for the
496 * N encoders set up by the driver. The first N planes become primary
497 * planes for the CRTCs, with the remainder as overlay planes:
498 */
499 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
500 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
501 struct drm_plane *plane;
502 enum drm_plane_type type;
503
504 if (i < num_crtcs)
505 type = DRM_PLANE_TYPE_PRIMARY;
506 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
507 type = DRM_PLANE_TYPE_CURSOR;
508 else
509 type = DRM_PLANE_TYPE_OVERLAY;
510
511 plane = mdp5_plane_init(dev, type);
512 if (IS_ERR(plane)) {
513 ret = PTR_ERR(plane);
514 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
515 goto fail;
516 }
517 priv->planes[priv->num_planes++] = plane;
518
519 if (type == DRM_PLANE_TYPE_PRIMARY)
520 primary[pi++] = plane;
521 if (type == DRM_PLANE_TYPE_CURSOR)
522 cursor[ci++] = plane;
523 }
524
525 for (i = 0; i < num_crtcs; i++) {
526 struct drm_crtc *crtc;
527
528 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i);
529 if (IS_ERR(crtc)) {
530 ret = PTR_ERR(crtc);
531 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
532 goto fail;
533 }
534 priv->crtcs[priv->num_crtcs++] = crtc;
535 }
536
537 /*
538 * Now that we know the number of crtcs we've created, set the possible
539 * crtcs for the encoders
540 */
541 for (i = 0; i < priv->num_encoders; i++) {
542 struct drm_encoder *encoder = priv->encoders[i];
543
544 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
545 }
546
547 return 0;
548
549 fail:
550 return ret;
551 }
552
553 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
554 u32 *major, u32 *minor)
555 {
556 struct device *dev = &mdp5_kms->pdev->dev;
557 u32 version;
558
559 pm_runtime_get_sync(dev);
560 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
561 pm_runtime_put_sync(dev);
562
563 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
564 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
565
566 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
567 }
568
569 static int get_clk(struct platform_device *pdev, struct clk **clkp,
570 const char *name, bool mandatory)
571 {
572 struct device *dev = &pdev->dev;
573 struct clk *clk = msm_clk_get(pdev, name);
574 if (IS_ERR(clk) && mandatory) {
575 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
576 return PTR_ERR(clk);
577 }
578 if (IS_ERR(clk))
579 DBG("skipping %s", name);
580 else
581 *clkp = clk;
582
583 return 0;
584 }
585
586 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
587 {
588 struct drm_device *dev = crtc->dev;
589 struct drm_encoder *encoder;
590
591 drm_for_each_encoder(encoder, dev)
592 if (encoder->crtc == crtc)
593 return encoder;
594
595 return NULL;
596 }
597
598 static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
599 bool in_vblank_irq, int *vpos, int *hpos,
600 ktime_t *stime, ktime_t *etime,
601 const struct drm_display_mode *mode)
602 {
603 struct msm_drm_private *priv = dev->dev_private;
604 struct drm_crtc *crtc;
605 struct drm_encoder *encoder;
606 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
607
608 crtc = priv->crtcs[pipe];
609 if (!crtc) {
610 DRM_ERROR("Invalid crtc %d\n", pipe);
611 return false;
612 }
613
614 encoder = get_encoder_from_crtc(crtc);
615 if (!encoder) {
616 DRM_ERROR("no encoder found for crtc %d\n", pipe);
617 return false;
618 }
619
620 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
621 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
622
623 /*
624 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
625 * the end of VFP. Translate the porch values relative to the line
626 * counter positions.
627 */
628
629 vactive_start = vsw + vbp + 1;
630
631 vactive_end = vactive_start + mode->crtc_vdisplay;
632
633 /* last scan line before VSYNC */
634 vfp_end = mode->crtc_vtotal;
635
636 if (stime)
637 *stime = ktime_get();
638
639 line = mdp5_encoder_get_linecount(encoder);
640
641 if (line < vactive_start) {
642 line -= vactive_start;
643 } else if (line > vactive_end) {
644 line = line - vfp_end - vactive_start;
645 } else {
646 line -= vactive_start;
647 }
648
649 *vpos = line;
650 *hpos = 0;
651
652 if (etime)
653 *etime = ktime_get();
654
655 return true;
656 }
657
658 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
659 {
660 struct msm_drm_private *priv = dev->dev_private;
661 struct drm_crtc *crtc;
662 struct drm_encoder *encoder;
663
664 if (pipe >= priv->num_crtcs)
665 return 0;
666
667 crtc = priv->crtcs[pipe];
668 if (!crtc)
669 return 0;
670
671 encoder = get_encoder_from_crtc(crtc);
672 if (!encoder)
673 return 0;
674
675 return mdp5_encoder_get_framecount(encoder);
676 }
677
678 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
679 {
680 struct msm_drm_private *priv = dev->dev_private;
681 struct platform_device *pdev;
682 struct mdp5_kms *mdp5_kms;
683 struct mdp5_cfg *config;
684 struct msm_kms *kms;
685 struct msm_gem_address_space *aspace;
686 int irq, i, ret;
687 struct device *iommu_dev;
688
689 /* priv->kms would have been populated by the MDP5 driver */
690 kms = priv->kms;
691 if (!kms)
692 return NULL;
693
694 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
695
696 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
697
698 pdev = mdp5_kms->pdev;
699
700 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
701 if (irq < 0) {
702 ret = irq;
703 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret);
704 goto fail;
705 }
706
707 kms->irq = irq;
708
709 config = mdp5_cfg_get_config(mdp5_kms->cfg);
710
711 /* make sure things are off before attaching iommu (bootloader could
712 * have left things on, in which case we'll start getting faults if
713 * we don't disable):
714 */
715 pm_runtime_get_sync(&pdev->dev);
716 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
717 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
718 !config->hw->intf.base[i])
719 continue;
720 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
721
722 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
723 }
724 mdelay(16);
725
726 if (config->platform.iommu) {
727 iommu_dev = &pdev->dev;
728 if (!iommu_dev->iommu_fwspec)
729 iommu_dev = iommu_dev->parent;
730
731 aspace = msm_gem_address_space_create(iommu_dev,
732 config->platform.iommu, "mdp5");
733 if (IS_ERR(aspace)) {
734 ret = PTR_ERR(aspace);
735 goto fail;
736 }
737
738 kms->aspace = aspace;
739
740 ret = aspace->mmu->funcs->attach(aspace->mmu);
741 if (ret) {
742 DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu: %d\n",
743 ret);
744 goto fail;
745 }
746 } else {
747 DRM_DEV_INFO(&pdev->dev,
748 "no iommu, fallback to phys contig buffers for scanout\n");
749 aspace = NULL;
750 }
751
752 pm_runtime_put_sync(&pdev->dev);
753
754 ret = modeset_init(mdp5_kms);
755 if (ret) {
756 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
757 goto fail;
758 }
759
760 dev->mode_config.min_width = 0;
761 dev->mode_config.min_height = 0;
762 dev->mode_config.max_width = 0xffff;
763 dev->mode_config.max_height = 0xffff;
764
765 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
766 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
767 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
768 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */
769 dev->vblank_disable_immediate = true;
770
771 return kms;
772 fail:
773 if (kms)
774 mdp5_kms_destroy(kms);
775 return ERR_PTR(ret);
776 }
777
778 static void mdp5_destroy(struct platform_device *pdev)
779 {
780 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
781 int i;
782
783 if (mdp5_kms->ctlm)
784 mdp5_ctlm_destroy(mdp5_kms->ctlm);
785 if (mdp5_kms->smp)
786 mdp5_smp_destroy(mdp5_kms->smp);
787 if (mdp5_kms->cfg)
788 mdp5_cfg_destroy(mdp5_kms->cfg);
789
790 for (i = 0; i < mdp5_kms->num_intfs; i++)
791 kfree(mdp5_kms->intfs[i]);
792
793 if (mdp5_kms->rpm_enabled)
794 pm_runtime_disable(&pdev->dev);
795
796 drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
797 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
798 }
799
800 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
801 const enum mdp5_pipe *pipes, const uint32_t *offsets,
802 uint32_t caps)
803 {
804 struct drm_device *dev = mdp5_kms->dev;
805 int i, ret;
806
807 for (i = 0; i < cnt; i++) {
808 struct mdp5_hw_pipe *hwpipe;
809
810 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
811 if (IS_ERR(hwpipe)) {
812 ret = PTR_ERR(hwpipe);
813 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
814 pipe2name(pipes[i]), ret);
815 return ret;
816 }
817 hwpipe->idx = mdp5_kms->num_hwpipes;
818 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
819 }
820
821 return 0;
822 }
823
824 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
825 {
826 static const enum mdp5_pipe rgb_planes[] = {
827 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
828 };
829 static const enum mdp5_pipe vig_planes[] = {
830 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
831 };
832 static const enum mdp5_pipe dma_planes[] = {
833 SSPP_DMA0, SSPP_DMA1,
834 };
835 static const enum mdp5_pipe cursor_planes[] = {
836 SSPP_CURSOR0, SSPP_CURSOR1,
837 };
838 const struct mdp5_cfg_hw *hw_cfg;
839 int ret;
840
841 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
842
843 /* Construct RGB pipes: */
844 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
845 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
846 if (ret)
847 return ret;
848
849 /* Construct video (VIG) pipes: */
850 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
851 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
852 if (ret)
853 return ret;
854
855 /* Construct DMA pipes: */
856 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
857 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
858 if (ret)
859 return ret;
860
861 /* Construct cursor pipes: */
862 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
863 cursor_planes, hw_cfg->pipe_cursor.base,
864 hw_cfg->pipe_cursor.caps);
865 if (ret)
866 return ret;
867
868 return 0;
869 }
870
871 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
872 {
873 struct drm_device *dev = mdp5_kms->dev;
874 const struct mdp5_cfg_hw *hw_cfg;
875 int i, ret;
876
877 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
878
879 for (i = 0; i < hw_cfg->lm.count; i++) {
880 struct mdp5_hw_mixer *mixer;
881
882 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
883 if (IS_ERR(mixer)) {
884 ret = PTR_ERR(mixer);
885 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
886 i, ret);
887 return ret;
888 }
889
890 mixer->idx = mdp5_kms->num_hwmixers;
891 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
892 }
893
894 return 0;
895 }
896
897 static int interface_init(struct mdp5_kms *mdp5_kms)
898 {
899 struct drm_device *dev = mdp5_kms->dev;
900 const struct mdp5_cfg_hw *hw_cfg;
901 const enum mdp5_intf_type *intf_types;
902 int i;
903
904 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
905 intf_types = hw_cfg->intf.connect;
906
907 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
908 struct mdp5_interface *intf;
909
910 if (intf_types[i] == INTF_DISABLED)
911 continue;
912
913 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
914 if (!intf) {
915 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
916 return -ENOMEM;
917 }
918
919 intf->num = i;
920 intf->type = intf_types[i];
921 intf->mode = MDP5_INTF_MODE_NONE;
922 intf->idx = mdp5_kms->num_intfs;
923 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
924 }
925
926 return 0;
927 }
928
929 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
930 {
931 struct msm_drm_private *priv = dev->dev_private;
932 struct mdp5_kms *mdp5_kms;
933 struct mdp5_cfg *config;
934 u32 major, minor;
935 int ret;
936
937 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
938 if (!mdp5_kms) {
939 ret = -ENOMEM;
940 goto fail;
941 }
942
943 platform_set_drvdata(pdev, mdp5_kms);
944
945 spin_lock_init(&mdp5_kms->resource_lock);
946
947 mdp5_kms->dev = dev;
948 mdp5_kms->pdev = pdev;
949
950 ret = mdp5_global_obj_init(mdp5_kms);
951 if (ret)
952 goto fail;
953
954 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
955 if (IS_ERR(mdp5_kms->mmio)) {
956 ret = PTR_ERR(mdp5_kms->mmio);
957 goto fail;
958 }
959
960 /* mandatory clocks: */
961 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
962 if (ret)
963 goto fail;
964 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
965 if (ret)
966 goto fail;
967 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
968 if (ret)
969 goto fail;
970 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
971 if (ret)
972 goto fail;
973
974 /* optional clocks: */
975 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
976 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);
977 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);
978
979 /* we need to set a default rate before enabling. Set a safe
980 * rate first, then figure out hw revision, and then set a
981 * more optimal rate:
982 */
983 clk_set_rate(mdp5_kms->core_clk, 200000000);
984
985 pm_runtime_enable(&pdev->dev);
986 mdp5_kms->rpm_enabled = true;
987
988 read_mdp_hw_revision(mdp5_kms, &major, &minor);
989
990 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
991 if (IS_ERR(mdp5_kms->cfg)) {
992 ret = PTR_ERR(mdp5_kms->cfg);
993 mdp5_kms->cfg = NULL;
994 goto fail;
995 }
996
997 config = mdp5_cfg_get_config(mdp5_kms->cfg);
998 mdp5_kms->caps = config->hw->mdp.caps;
999
1000 /* TODO: compute core clock rate at runtime */
1001 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
1002
1003 /*
1004 * Some chipsets have a Shared Memory Pool (SMP), while others
1005 * have dedicated latency buffering per source pipe instead;
1006 * this section initializes the SMP:
1007 */
1008 if (mdp5_kms->caps & MDP_CAP_SMP) {
1009 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
1010 if (IS_ERR(mdp5_kms->smp)) {
1011 ret = PTR_ERR(mdp5_kms->smp);
1012 mdp5_kms->smp = NULL;
1013 goto fail;
1014 }
1015 }
1016
1017 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
1018 if (IS_ERR(mdp5_kms->ctlm)) {
1019 ret = PTR_ERR(mdp5_kms->ctlm);
1020 mdp5_kms->ctlm = NULL;
1021 goto fail;
1022 }
1023
1024 ret = hwpipe_init(mdp5_kms);
1025 if (ret)
1026 goto fail;
1027
1028 ret = hwmixer_init(mdp5_kms);
1029 if (ret)
1030 goto fail;
1031
1032 ret = interface_init(mdp5_kms);
1033 if (ret)
1034 goto fail;
1035
1036 /* set uninit-ed kms */
1037 priv->kms = &mdp5_kms->base.base;
1038
1039 return 0;
1040 fail:
1041 mdp5_destroy(pdev);
1042 return ret;
1043 }
1044
1045 static int mdp5_bind(struct device *dev, struct device *master, void *data)
1046 {
1047 struct drm_device *ddev = dev_get_drvdata(master);
1048 struct platform_device *pdev = to_platform_device(dev);
1049
1050 DBG("");
1051
1052 return mdp5_init(pdev, ddev);
1053 }
1054
1055 static void mdp5_unbind(struct device *dev, struct device *master,
1056 void *data)
1057 {
1058 struct platform_device *pdev = to_platform_device(dev);
1059
1060 mdp5_destroy(pdev);
1061 }
1062
1063 static const struct component_ops mdp5_ops = {
1064 .bind = mdp5_bind,
1065 .unbind = mdp5_unbind,
1066 };
1067
1068 static int mdp5_setup_interconnect(struct platform_device *pdev)
1069 {
1070 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
1071 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
1072 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
1073
1074 if (IS_ERR(path0))
1075 return PTR_ERR(path0);
1076
1077 if (!path0) {
1078 /* no interconnect support is not necessarily a fatal
1079 * condition, the platform may simply not have an
1080 * interconnect driver yet. But warn about it in case
1081 * bootloader didn't setup bus clocks high enough for
1082 * scanout.
1083 */
1084 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
1085 return 0;
1086 }
1087
1088 icc_set_bw(path0, 0, MBps_to_icc(6400));
1089
1090 if (!IS_ERR_OR_NULL(path1))
1091 icc_set_bw(path1, 0, MBps_to_icc(6400));
1092 if (!IS_ERR_OR_NULL(path_rot))
1093 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
1094
1095 return 0;
1096 }
1097
1098 static int mdp5_dev_probe(struct platform_device *pdev)
1099 {
1100 int ret;
1101
1102 DBG("");
1103
1104 ret = mdp5_setup_interconnect(pdev);
1105 if (ret)
1106 return ret;
1107
1108 return component_add(&pdev->dev, &mdp5_ops);
1109 }
1110
1111 static int mdp5_dev_remove(struct platform_device *pdev)
1112 {
1113 DBG("");
1114 component_del(&pdev->dev, &mdp5_ops);
1115 return 0;
1116 }
1117
1118 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1119 {
1120 struct platform_device *pdev = to_platform_device(dev);
1121 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1122
1123 DBG("");
1124
1125 return mdp5_disable(mdp5_kms);
1126 }
1127
1128 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1129 {
1130 struct platform_device *pdev = to_platform_device(dev);
1131 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1132
1133 DBG("");
1134
1135 return mdp5_enable(mdp5_kms);
1136 }
1137
1138 static const struct dev_pm_ops mdp5_pm_ops = {
1139 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1140 };
1141
1142 static const struct of_device_id mdp5_dt_match[] = {
1143 { .compatible = "qcom,mdp5", },
1144 /* to support downstream DT files */
1145 { .compatible = "qcom,mdss_mdp", },
1146 {}
1147 };
1148 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1149
1150 static struct platform_driver mdp5_driver = {
1151 .probe = mdp5_dev_probe,
1152 .remove = mdp5_dev_remove,
1153 .driver = {
1154 .name = "msm_mdp",
1155 .of_match_table = mdp5_dt_match,
1156 .pm = &mdp5_pm_ops,
1157 },
1158 };
1159
1160 void __init msm_mdp_register(void)
1161 {
1162 DBG("");
1163 platform_driver_register(&mdp5_driver);
1164 }
1165
1166 void __exit msm_mdp_unregister(void)
1167 {
1168 DBG("");
1169 platform_driver_unregister(&mdp5_driver);
1170 }
Linux with added FPC-III support