drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include "dsi_phy.h"
   7 #include "dsi.xml.h"
   8
   9 static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
  10                 struct msm_dsi_dphy_timing *timing)
  11 {
  12         void __iomem *base = phy->base;
  13
  14         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
  15                 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
  16         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
  17                 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
  18         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
  19                 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
  20         if (timing->clk_zero & BIT(8))
  21                 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
  22                         DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
  23         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
  24                 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
  25         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
  26                 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
  27         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
  28                 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
  29         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
  30                 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
  31         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
  32                 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
  33         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
  34                 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
  35                 DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
  36         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
  37                 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
  38         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
  39                 DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
  40 }
  41
  42 static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
  43 {
  44         void __iomem *base = phy->reg_base;
  45
  46         if (!enable) {
  47                 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
  48                 return;
  49         }
  50
  51         if (phy->regulator_ldo_mode) {
  52                 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
  53                 return;
  54         }
  55
  56         /* non LDO mode */
  57         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
  58         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
  59         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
  60         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
  61         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
  62         dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
  63         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
  64 }
  65
  66 static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
  67                                 struct msm_dsi_phy_clk_request *clk_req)
  68 {
  69         struct msm_dsi_dphy_timing *timing = &phy->timing;
  70         int i;
  71         void __iomem *base = phy->base;
  72         u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
  73
  74         DBG("");
  75
  76         if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
  77                 DRM_DEV_ERROR(&phy->pdev->dev,
  78                         "%s: D-PHY timing calculation failed\n", __func__);
  79                 return -EINVAL;
  80         }
  81
  82         dsi_20nm_phy_regulator_ctrl(phy, true);
  83
  84         dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
  85
  86         msm_dsi_phy_set_src_pll(phy, src_pll_id,
  87                                 REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
  88                                 DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
  89
  90         for (i = 0; i < 4; i++) {
  91                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
  92                                                         (i >> 1) * 0x40);
  93                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
  94                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
  95                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
  96                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
  97                 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
  98         }
  99
 100         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
 101         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
 102         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
 103         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
 104         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
 105         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
 106         dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
 107
 108         dsi_20nm_dphy_set_timing(phy, timing);
 109
 110         dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
 111
 112         dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
 113
 114         /* make sure everything is written before enable */
 115         wmb();
 116         dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
 117
 118         return 0;
 119 }
 120
 121 static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
 122 {
 123         dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
 124         dsi_20nm_phy_regulator_ctrl(phy, false);
 125 }
 126
 127 const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
 128         .type = MSM_DSI_PHY_20NM,
 129         .src_pll_truthtable = { {false, true}, {false, true} },
 130         .reg_cfg = {
 131                 .num = 2,
 132                 .regs = {
 133                         {"vddio", 100000, 100}, /* 1.8 V */
 134                         {"vcca", 10000, 100},   /* 1.0 V */
 135                 },
 136         },
 137         .ops = {
 138                 .enable = dsi_20nm_phy_enable,
 139                 .disable = dsi_20nm_phy_disable,
 140                 .init = msm_dsi_phy_init_common,
 141         },
 142         .io_start = { 0xfd998300, 0xfd9a0300 },
 143         .num_dsi_phy = 2,
 144 };
 145