1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
7 #ifndef __HDMI_CONNECTOR_H__
8 #define __HDMI_CONNECTOR_H__
10 #include <linux/i2c.h>
11 #include <linux/clk.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/hdmi.h>
17 #include <drm/drm_bridge.h>
22 #define HDMI_MAX_NUM_GPIO 6
25 struct hdmi_platform_config
;
27 struct hdmi_gpio_data
{
28 struct gpio_desc
*gpiod
;
35 struct hdmi_audio_infoframe infoframe
;
39 struct hdmi_hdcp_ctrl
;
42 struct drm_device
*dev
;
43 struct platform_device
*pdev
;
44 struct platform_device
*audio_pdev
;
46 const struct hdmi_platform_config
*config
;
49 struct hdmi_audio audio
;
53 unsigned long int pixclock
;
56 void __iomem
*qfprom_mmio
;
57 phys_addr_t mmio_phy_addr
;
59 struct regulator
**hpd_regs
;
60 struct regulator
**pwr_regs
;
61 struct clk
**hpd_clks
;
62 struct clk
**pwr_clks
;
65 struct device
*phy_dev
;
67 struct i2c_adapter
*i2c
;
68 struct drm_connector
*connector
;
69 struct drm_bridge
*bridge
;
71 /* the encoder we are hooked to (outside of hdmi block) */
72 struct drm_encoder
*encoder
;
74 bool hdmi_mode
; /* are we in hdmi mode? */
77 struct workqueue_struct
*workq
;
79 struct hdmi_hdcp_ctrl
*hdcp_ctrl
;
82 * spinlock to protect registers shared by different execution
84 * REG_HDMI_DDC_ARBITRATION
85 * REG_HDMI_HDCP_INT_CTRL
91 /* platform config data (ie. from DT, or pdata) */
92 struct hdmi_platform_config
{
93 const char *mmio_name
;
94 const char *qfprom_mmio_name
;
96 /* regulators that need to be on for hpd: */
97 const char **hpd_reg_names
;
100 /* regulators that need to be on for screen pwr: */
101 const char **pwr_reg_names
;
104 /* clks that need to be on for hpd: */
105 const char **hpd_clk_names
;
106 const long unsigned *hpd_freq
;
109 /* clks that need to be on for screen pwr (ie pixel clk): */
110 const char **pwr_clk_names
;
114 struct hdmi_gpio_data gpios
[HDMI_MAX_NUM_GPIO
];
117 void msm_hdmi_set_mode(struct hdmi
*hdmi
, bool power_on
);
119 static inline void hdmi_write(struct hdmi
*hdmi
, u32 reg
, u32 data
)
121 msm_writel(data
, hdmi
->mmio
+ reg
);
124 static inline u32
hdmi_read(struct hdmi
*hdmi
, u32 reg
)
126 return msm_readl(hdmi
->mmio
+ reg
);
129 static inline u32
hdmi_qfprom_read(struct hdmi
*hdmi
, u32 reg
)
131 return msm_readl(hdmi
->qfprom_mmio
+ reg
);
146 struct hdmi_phy_cfg
{
147 enum hdmi_phy_type type
;
148 void (*powerup
)(struct hdmi_phy
*phy
, unsigned long int pixclock
);
149 void (*powerdown
)(struct hdmi_phy
*phy
);
150 const char * const *reg_names
;
152 const char * const *clk_names
;
156 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg
;
157 extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg
;
158 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg
;
159 extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg
;
162 struct platform_device
*pdev
;
164 struct hdmi_phy_cfg
*cfg
;
165 const struct hdmi_phy_funcs
*funcs
;
166 struct regulator
**regs
;
170 static inline void hdmi_phy_write(struct hdmi_phy
*phy
, u32 reg
, u32 data
)
172 msm_writel(data
, phy
->mmio
+ reg
);
175 static inline u32
hdmi_phy_read(struct hdmi_phy
*phy
, u32 reg
)
177 return msm_readl(phy
->mmio
+ reg
);
180 int msm_hdmi_phy_resource_enable(struct hdmi_phy
*phy
);
181 void msm_hdmi_phy_resource_disable(struct hdmi_phy
*phy
);
182 void msm_hdmi_phy_powerup(struct hdmi_phy
*phy
, unsigned long int pixclock
);
183 void msm_hdmi_phy_powerdown(struct hdmi_phy
*phy
);
184 void __init
msm_hdmi_phy_driver_register(void);
185 void __exit
msm_hdmi_phy_driver_unregister(void);
187 #ifdef CONFIG_COMMON_CLK
188 int msm_hdmi_pll_8960_init(struct platform_device
*pdev
);
189 int msm_hdmi_pll_8996_init(struct platform_device
*pdev
);
191 static inline int msm_hdmi_pll_8960_init(struct platform_device
*pdev
)
196 static inline int msm_hdmi_pll_8996_init(struct platform_device
*pdev
)
205 /* Supported HDMI Audio channels and rates */
206 #define MSM_HDMI_AUDIO_CHANNEL_2 0
207 #define MSM_HDMI_AUDIO_CHANNEL_4 1
208 #define MSM_HDMI_AUDIO_CHANNEL_6 2
209 #define MSM_HDMI_AUDIO_CHANNEL_8 3
211 #define HDMI_SAMPLE_RATE_32KHZ 0
212 #define HDMI_SAMPLE_RATE_44_1KHZ 1
213 #define HDMI_SAMPLE_RATE_48KHZ 2
214 #define HDMI_SAMPLE_RATE_88_2KHZ 3
215 #define HDMI_SAMPLE_RATE_96KHZ 4
216 #define HDMI_SAMPLE_RATE_176_4KHZ 5
217 #define HDMI_SAMPLE_RATE_192KHZ 6
219 int msm_hdmi_audio_update(struct hdmi
*hdmi
);
220 int msm_hdmi_audio_info_setup(struct hdmi
*hdmi
, bool enabled
,
221 uint32_t num_of_channels
, uint32_t channel_allocation
,
222 uint32_t level_shift
, bool down_mix
);
223 void msm_hdmi_audio_set_sample_rate(struct hdmi
*hdmi
, int rate
);
230 struct drm_bridge
*msm_hdmi_bridge_init(struct hdmi
*hdmi
);
231 void msm_hdmi_bridge_destroy(struct drm_bridge
*bridge
);
237 void msm_hdmi_connector_irq(struct drm_connector
*connector
);
238 struct drm_connector
*msm_hdmi_connector_init(struct hdmi
*hdmi
);
239 int msm_hdmi_hpd_enable(struct drm_connector
*connector
);
242 * i2c adapter for ddc:
245 void msm_hdmi_i2c_irq(struct i2c_adapter
*i2c
);
246 void msm_hdmi_i2c_destroy(struct i2c_adapter
*i2c
);
247 struct i2c_adapter
*msm_hdmi_i2c_init(struct hdmi
*hdmi
);
252 #ifdef CONFIG_DRM_MSM_HDMI_HDCP
253 struct hdmi_hdcp_ctrl
*msm_hdmi_hdcp_init(struct hdmi
*hdmi
);
254 void msm_hdmi_hdcp_destroy(struct hdmi
*hdmi
);
255 void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl
*hdcp_ctrl
);
256 void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl
*hdcp_ctrl
);
257 void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl
*hdcp_ctrl
);
259 static inline struct hdmi_hdcp_ctrl
*msm_hdmi_hdcp_init(struct hdmi
*hdmi
)
261 return ERR_PTR(-ENXIO
);
263 static inline void msm_hdmi_hdcp_destroy(struct hdmi
*hdmi
) {}
264 static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl
*hdcp_ctrl
) {}
265 static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl
*hdcp_ctrl
) {}
266 static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl
*hdcp_ctrl
) {}
269 #endif /* __HDMI_CONNECTOR_H__ */