2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nouveau_drv.h"
28 #include <subdev/bios/pll.h>
30 #define CHIPSET_NFORCE 0x01a0
31 #define CHIPSET_NFORCE2 0x01f0
34 * misc hw access wrappers/control functions
38 NVWriteVgaSeq(struct drm_device
*dev
, int head
, uint8_t index
, uint8_t value
)
40 NVWritePRMVIO(dev
, head
, NV_PRMVIO_SRX
, index
);
41 NVWritePRMVIO(dev
, head
, NV_PRMVIO_SR
, value
);
45 NVReadVgaSeq(struct drm_device
*dev
, int head
, uint8_t index
)
47 NVWritePRMVIO(dev
, head
, NV_PRMVIO_SRX
, index
);
48 return NVReadPRMVIO(dev
, head
, NV_PRMVIO_SR
);
52 NVWriteVgaGr(struct drm_device
*dev
, int head
, uint8_t index
, uint8_t value
)
54 NVWritePRMVIO(dev
, head
, NV_PRMVIO_GRX
, index
);
55 NVWritePRMVIO(dev
, head
, NV_PRMVIO_GX
, value
);
59 NVReadVgaGr(struct drm_device
*dev
, int head
, uint8_t index
)
61 NVWritePRMVIO(dev
, head
, NV_PRMVIO_GRX
, index
);
62 return NVReadPRMVIO(dev
, head
, NV_PRMVIO_GX
);
65 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
66 * it affects only the 8 bit vga io regs, which we access using mmio at
67 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
68 * in general, the set value of cr44 does not matter: reg access works as
69 * expected and values can be set for the appropriate head by using a 0x2000
72 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
73 * cr44 must be set to 0 or 3 for accessing values on the correct head
74 * through the common 0xc03c* addresses
75 * b) in tied mode (4) head B is programmed to the values set on head A, and
76 * access using the head B addresses can have strange results, ergo we leave
77 * tied mode in init once we know to what cr44 should be restored on exit
79 * the owner parameter is slightly abused:
80 * 0 and 1 are treated as head values and so the set value is (owner * 3)
81 * other values are treated as literal values to set
84 NVSetOwner(struct drm_device
*dev
, int owner
)
86 struct nouveau_drm
*drm
= nouveau_drm(dev
);
91 if (drm
->client
.device
.info
.chipset
== 0x11) {
92 /* This might seem stupid, but the blob does it and
93 * omitting it often locks the system up.
95 NVReadVgaCrtc(dev
, 0, NV_CIO_SR_LOCK_INDEX
);
96 NVReadVgaCrtc(dev
, 1, NV_CIO_SR_LOCK_INDEX
);
99 /* CR44 is always changed on CRTC0 */
100 NVWriteVgaCrtc(dev
, 0, NV_CIO_CRE_44
, owner
);
102 if (drm
->client
.device
.info
.chipset
== 0x11) { /* set me harder */
103 NVWriteVgaCrtc(dev
, 0, NV_CIO_CRE_2E
, owner
);
104 NVWriteVgaCrtc(dev
, 0, NV_CIO_CRE_2E
, owner
);
109 NVBlankScreen(struct drm_device
*dev
, int head
, bool blank
)
113 if (nv_two_heads(dev
))
114 NVSetOwner(dev
, head
);
116 seq1
= NVReadVgaSeq(dev
, head
, NV_VIO_SR_CLOCK_INDEX
);
118 NVVgaSeqReset(dev
, head
, true);
120 NVWriteVgaSeq(dev
, head
, NV_VIO_SR_CLOCK_INDEX
, seq1
| 0x20);
122 NVWriteVgaSeq(dev
, head
, NV_VIO_SR_CLOCK_INDEX
, seq1
& ~0x20);
123 NVVgaSeqReset(dev
, head
, false);
131 nouveau_hw_decode_pll(struct drm_device
*dev
, uint32_t reg1
, uint32_t pll1
,
132 uint32_t pll2
, struct nvkm_pll_vals
*pllvals
)
134 struct nouveau_drm
*drm
= nouveau_drm(dev
);
136 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
138 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
139 pllvals
->log2P
= (pll1
>> 16) & 0x7;
140 pllvals
->N2
= pllvals
->M2
= 1;
142 if (reg1
<= 0x405c) {
143 pllvals
->NM1
= pll2
& 0xffff;
144 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
145 if (!(pll1
& 0x1100))
146 pllvals
->NM2
= pll2
>> 16;
148 pllvals
->NM1
= pll1
& 0xffff;
149 if (nv_two_reg_pll(dev
) && pll2
& NV31_RAMDAC_ENABLE_VCO2
)
150 pllvals
->NM2
= pll2
& 0xffff;
151 else if (drm
->client
.device
.info
.chipset
== 0x30 || drm
->client
.device
.info
.chipset
== 0x35) {
152 pllvals
->M1
&= 0xf; /* only 4 bits */
153 if (pll1
& NV30_RAMDAC_ENABLE_VCO2
) {
154 pllvals
->M2
= (pll1
>> 4) & 0x7;
155 pllvals
->N2
= ((pll1
>> 21) & 0x18) |
156 ((pll1
>> 19) & 0x7);
163 nouveau_hw_get_pllvals(struct drm_device
*dev
, enum nvbios_pll_type plltype
,
164 struct nvkm_pll_vals
*pllvals
)
166 struct nouveau_drm
*drm
= nouveau_drm(dev
);
167 struct nvif_object
*device
= &drm
->client
.device
.object
;
168 struct nvkm_bios
*bios
= nvxx_bios(&drm
->client
.device
);
169 uint32_t reg1
, pll1
, pll2
= 0;
170 struct nvbios_pll pll_lim
;
173 ret
= nvbios_pll_parse(bios
, plltype
, &pll_lim
);
174 if (ret
|| !(reg1
= pll_lim
.reg
))
177 pll1
= nvif_rd32(device
, reg1
);
179 pll2
= nvif_rd32(device
, reg1
+ 4);
180 else if (nv_two_reg_pll(dev
)) {
181 uint32_t reg2
= reg1
+ (reg1
== NV_RAMDAC_VPLL2
? 0x5c : 0x70);
183 pll2
= nvif_rd32(device
, reg2
);
186 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CELSIUS
&& reg1
>= NV_PRAMDAC_VPLL_COEFF
) {
187 uint32_t ramdac580
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_580
);
189 /* check whether vpll has been forced into single stage mode */
190 if (reg1
== NV_PRAMDAC_VPLL_COEFF
) {
191 if (ramdac580
& NV_RAMDAC_580_VPLL1_ACTIVE
)
194 if (ramdac580
& NV_RAMDAC_580_VPLL2_ACTIVE
)
198 nouveau_hw_decode_pll(dev
, reg1
, pll1
, pll2
, pllvals
);
199 pllvals
->refclk
= pll_lim
.refclk
;
204 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals
*pv
)
206 /* Avoid divide by zero if called at an inappropriate time */
207 if (!pv
->M1
|| !pv
->M2
)
210 return pv
->N1
* pv
->N2
* pv
->refclk
/ (pv
->M1
* pv
->M2
) >> pv
->log2P
;
214 nouveau_hw_get_clock(struct drm_device
*dev
, enum nvbios_pll_type plltype
)
216 struct nvkm_pll_vals pllvals
;
220 domain
= pci_domain_nr(dev
->pdev
->bus
);
222 if (plltype
== PLL_MEMORY
&&
223 (dev
->pdev
->device
& 0x0ff0) == CHIPSET_NFORCE
) {
225 pci_read_config_dword(pci_get_domain_bus_and_slot(domain
, 0, 3),
227 mpllP
= (mpllP
>> 8) & 0xf;
231 return 400000 / mpllP
;
233 if (plltype
== PLL_MEMORY
&&
234 (dev
->pdev
->device
& 0xff0) == CHIPSET_NFORCE2
) {
237 pci_read_config_dword(pci_get_domain_bus_and_slot(domain
, 0, 5),
242 ret
= nouveau_hw_get_pllvals(dev
, plltype
, &pllvals
);
246 return nouveau_hw_pllvals_to_clk(&pllvals
);
250 nouveau_hw_fix_bad_vpll(struct drm_device
*dev
, int head
)
252 /* the vpll on an unused head can come up with a random value, way
253 * beyond the pll limits. for some reason this causes the chip to
254 * lock up when reading the dac palette regs, so set a valid pll here
255 * when such a condition detected. only seen on nv11 to date
258 struct nouveau_drm
*drm
= nouveau_drm(dev
);
259 struct nvif_device
*device
= &drm
->client
.device
;
260 struct nvkm_clk
*clk
= nvxx_clk(device
);
261 struct nvkm_bios
*bios
= nvxx_bios(device
);
262 struct nvbios_pll pll_lim
;
263 struct nvkm_pll_vals pv
;
264 enum nvbios_pll_type pll
= head
? PLL_VPLL1
: PLL_VPLL0
;
266 if (nvbios_pll_parse(bios
, pll
, &pll_lim
))
268 nouveau_hw_get_pllvals(dev
, pll
, &pv
);
270 if (pv
.M1
>= pll_lim
.vco1
.min_m
&& pv
.M1
<= pll_lim
.vco1
.max_m
&&
271 pv
.N1
>= pll_lim
.vco1
.min_n
&& pv
.N1
<= pll_lim
.vco1
.max_n
&&
272 pv
.log2P
<= pll_lim
.max_p
)
275 NV_WARN(drm
, "VPLL %d outwith limits, attempting to fix\n", head
+ 1);
277 /* set lowest clock within static limits */
278 pv
.M1
= pll_lim
.vco1
.max_m
;
279 pv
.N1
= pll_lim
.vco1
.min_n
;
280 pv
.log2P
= pll_lim
.max_p_usable
;
281 clk
->pll_prog(clk
, pll_lim
.reg
, &pv
);
285 * vga font save/restore
288 static void nouveau_vga_font_io(struct drm_device
*dev
,
289 void __iomem
*iovram
,
290 bool save
, unsigned plane
)
294 NVWriteVgaSeq(dev
, 0, NV_VIO_SR_PLANE_MASK_INDEX
, 1 << plane
);
295 NVWriteVgaGr(dev
, 0, NV_VIO_GX_READ_MAP_INDEX
, plane
);
296 for (i
= 0; i
< 16384; i
++) {
298 nv04_display(dev
)->saved_vga_font
[plane
][i
] =
299 ioread32_native(iovram
+ i
* 4);
301 iowrite32_native(nv04_display(dev
)->saved_vga_font
[plane
][i
],
308 nouveau_hw_save_vga_fonts(struct drm_device
*dev
, bool save
)
310 struct nouveau_drm
*drm
= nouveau_drm(dev
);
311 uint8_t misc
, gr4
, gr5
, gr6
, seq2
, seq4
;
314 void __iomem
*iovram
;
316 if (nv_two_heads(dev
))
319 NVSetEnablePalette(dev
, 0, true);
320 graphicsmode
= NVReadVgaAttr(dev
, 0, NV_CIO_AR_MODE_INDEX
) & 1;
321 NVSetEnablePalette(dev
, 0, false);
323 if (graphicsmode
) /* graphics mode => framebuffer => no need to save */
326 NV_INFO(drm
, "%sing VGA fonts\n", save
? "Sav" : "Restor");
328 /* map first 64KiB of VRAM, holds VGA fonts etc */
329 iovram
= ioremap(pci_resource_start(dev
->pdev
, 1), 65536);
331 NV_ERROR(drm
, "Failed to map VRAM, "
332 "cannot save/restore VGA fonts.\n");
336 if (nv_two_heads(dev
))
337 NVBlankScreen(dev
, 1, true);
338 NVBlankScreen(dev
, 0, true);
340 /* save control regs */
341 misc
= NVReadPRMVIO(dev
, 0, NV_PRMVIO_MISC__READ
);
342 seq2
= NVReadVgaSeq(dev
, 0, NV_VIO_SR_PLANE_MASK_INDEX
);
343 seq4
= NVReadVgaSeq(dev
, 0, NV_VIO_SR_MEM_MODE_INDEX
);
344 gr4
= NVReadVgaGr(dev
, 0, NV_VIO_GX_READ_MAP_INDEX
);
345 gr5
= NVReadVgaGr(dev
, 0, NV_VIO_GX_MODE_INDEX
);
346 gr6
= NVReadVgaGr(dev
, 0, NV_VIO_GX_MISC_INDEX
);
348 NVWritePRMVIO(dev
, 0, NV_PRMVIO_MISC__WRITE
, 0x67);
349 NVWriteVgaSeq(dev
, 0, NV_VIO_SR_MEM_MODE_INDEX
, 0x6);
350 NVWriteVgaGr(dev
, 0, NV_VIO_GX_MODE_INDEX
, 0x0);
351 NVWriteVgaGr(dev
, 0, NV_VIO_GX_MISC_INDEX
, 0x5);
353 /* store font in planes 0..3 */
354 for (plane
= 0; plane
< 4; plane
++)
355 nouveau_vga_font_io(dev
, iovram
, save
, plane
);
357 /* restore control regs */
358 NVWritePRMVIO(dev
, 0, NV_PRMVIO_MISC__WRITE
, misc
);
359 NVWriteVgaGr(dev
, 0, NV_VIO_GX_READ_MAP_INDEX
, gr4
);
360 NVWriteVgaGr(dev
, 0, NV_VIO_GX_MODE_INDEX
, gr5
);
361 NVWriteVgaGr(dev
, 0, NV_VIO_GX_MISC_INDEX
, gr6
);
362 NVWriteVgaSeq(dev
, 0, NV_VIO_SR_PLANE_MASK_INDEX
, seq2
);
363 NVWriteVgaSeq(dev
, 0, NV_VIO_SR_MEM_MODE_INDEX
, seq4
);
365 if (nv_two_heads(dev
))
366 NVBlankScreen(dev
, 1, false);
367 NVBlankScreen(dev
, 0, false);
373 * mode state save/load
377 rd_cio_state(struct drm_device
*dev
, int head
,
378 struct nv04_crtc_reg
*crtcstate
, int index
)
380 crtcstate
->CRTC
[index
] = NVReadVgaCrtc(dev
, head
, index
);
384 wr_cio_state(struct drm_device
*dev
, int head
,
385 struct nv04_crtc_reg
*crtcstate
, int index
)
387 NVWriteVgaCrtc(dev
, head
, index
, crtcstate
->CRTC
[index
]);
391 nv_save_state_ramdac(struct drm_device
*dev
, int head
,
392 struct nv04_mode_state
*state
)
394 struct nouveau_drm
*drm
= nouveau_drm(dev
);
395 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
398 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
)
399 regp
->nv10_cursync
= NVReadRAMDAC(dev
, head
, NV_RAMDAC_NV10_CURSYNC
);
401 nouveau_hw_get_pllvals(dev
, head
? PLL_VPLL1
: PLL_VPLL0
, ®p
->pllvals
);
402 state
->pllsel
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_PLL_COEFF_SELECT
);
403 if (nv_two_heads(dev
))
404 state
->sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
);
405 if (drm
->client
.device
.info
.chipset
== 0x11)
406 regp
->dither
= NVReadRAMDAC(dev
, head
, NV_RAMDAC_DITHER_NV11
);
408 regp
->ramdac_gen_ctrl
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_GENERAL_CONTROL
);
410 if (nv_gf4_disp_arch(dev
))
411 regp
->ramdac_630
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_630
);
412 if (drm
->client
.device
.info
.chipset
>= 0x30)
413 regp
->ramdac_634
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_634
);
415 regp
->tv_setup
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_SETUP
);
416 regp
->tv_vtotal
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_VTOTAL
);
417 regp
->tv_vskew
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_VSKEW
);
418 regp
->tv_vsync_delay
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_VSYNC_DELAY
);
419 regp
->tv_htotal
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_HTOTAL
);
420 regp
->tv_hskew
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSKEW
);
421 regp
->tv_hsync_delay
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSYNC_DELAY
);
422 regp
->tv_hsync_delay2
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSYNC_DELAY2
);
424 for (i
= 0; i
< 7; i
++) {
425 uint32_t ramdac_reg
= NV_PRAMDAC_FP_VDISPLAY_END
+ (i
* 4);
426 regp
->fp_vert_regs
[i
] = NVReadRAMDAC(dev
, head
, ramdac_reg
);
427 regp
->fp_horiz_regs
[i
] = NVReadRAMDAC(dev
, head
, ramdac_reg
+ 0x20);
430 if (nv_gf4_disp_arch(dev
)) {
431 regp
->dither
= NVReadRAMDAC(dev
, head
, NV_RAMDAC_FP_DITHER
);
432 for (i
= 0; i
< 3; i
++) {
433 regp
->dither_regs
[i
] = NVReadRAMDAC(dev
, head
, NV_PRAMDAC_850
+ i
* 4);
434 regp
->dither_regs
[i
+ 3] = NVReadRAMDAC(dev
, head
, NV_PRAMDAC_85C
+ i
* 4);
438 regp
->fp_control
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_TG_CONTROL
);
439 regp
->fp_debug_0
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_0
);
440 if (!nv_gf4_disp_arch(dev
) && head
== 0) {
441 /* early chips don't allow access to PRAMDAC_TMDS_* without
442 * the head A FPCLK on (nv11 even locks up) */
443 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_FP_DEBUG_0
, regp
->fp_debug_0
&
444 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK
);
446 regp
->fp_debug_1
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_1
);
447 regp
->fp_debug_2
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_2
);
449 regp
->fp_margin_color
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_MARGIN_COLOR
);
451 if (nv_gf4_disp_arch(dev
))
452 regp
->ramdac_8c0
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_8C0
);
454 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CURIE
) {
455 regp
->ramdac_a20
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_A20
);
456 regp
->ramdac_a24
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_A24
);
457 regp
->ramdac_a34
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_A34
);
459 for (i
= 0; i
< 38; i
++)
460 regp
->ctv_regs
[i
] = NVReadRAMDAC(dev
, head
,
461 NV_PRAMDAC_CTV
+ 4*i
);
466 nv_load_state_ramdac(struct drm_device
*dev
, int head
,
467 struct nv04_mode_state
*state
)
469 struct nouveau_drm
*drm
= nouveau_drm(dev
);
470 struct nvkm_clk
*clk
= nvxx_clk(&drm
->client
.device
);
471 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
472 uint32_t pllreg
= head
? NV_RAMDAC_VPLL2
: NV_PRAMDAC_VPLL_COEFF
;
475 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
)
476 NVWriteRAMDAC(dev
, head
, NV_RAMDAC_NV10_CURSYNC
, regp
->nv10_cursync
);
478 clk
->pll_prog(clk
, pllreg
, ®p
->pllvals
);
479 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_PLL_COEFF_SELECT
, state
->pllsel
);
480 if (nv_two_heads(dev
))
481 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, state
->sel_clk
);
482 if (drm
->client
.device
.info
.chipset
== 0x11)
483 NVWriteRAMDAC(dev
, head
, NV_RAMDAC_DITHER_NV11
, regp
->dither
);
485 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_GENERAL_CONTROL
, regp
->ramdac_gen_ctrl
);
487 if (nv_gf4_disp_arch(dev
))
488 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_630
, regp
->ramdac_630
);
489 if (drm
->client
.device
.info
.chipset
>= 0x30)
490 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_634
, regp
->ramdac_634
);
492 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_SETUP
, regp
->tv_setup
);
493 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_VTOTAL
, regp
->tv_vtotal
);
494 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_VSKEW
, regp
->tv_vskew
);
495 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_VSYNC_DELAY
, regp
->tv_vsync_delay
);
496 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_HTOTAL
, regp
->tv_htotal
);
497 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSKEW
, regp
->tv_hskew
);
498 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSYNC_DELAY
, regp
->tv_hsync_delay
);
499 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_TV_HSYNC_DELAY2
, regp
->tv_hsync_delay2
);
501 for (i
= 0; i
< 7; i
++) {
502 uint32_t ramdac_reg
= NV_PRAMDAC_FP_VDISPLAY_END
+ (i
* 4);
504 NVWriteRAMDAC(dev
, head
, ramdac_reg
, regp
->fp_vert_regs
[i
]);
505 NVWriteRAMDAC(dev
, head
, ramdac_reg
+ 0x20, regp
->fp_horiz_regs
[i
]);
508 if (nv_gf4_disp_arch(dev
)) {
509 NVWriteRAMDAC(dev
, head
, NV_RAMDAC_FP_DITHER
, regp
->dither
);
510 for (i
= 0; i
< 3; i
++) {
511 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_850
+ i
* 4, regp
->dither_regs
[i
]);
512 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_85C
+ i
* 4, regp
->dither_regs
[i
+ 3]);
516 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_TG_CONTROL
, regp
->fp_control
);
517 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_0
, regp
->fp_debug_0
);
518 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_1
, regp
->fp_debug_1
);
519 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_DEBUG_2
, regp
->fp_debug_2
);
521 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_MARGIN_COLOR
, regp
->fp_margin_color
);
523 if (nv_gf4_disp_arch(dev
))
524 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_8C0
, regp
->ramdac_8c0
);
526 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CURIE
) {
527 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_A20
, regp
->ramdac_a20
);
528 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_A24
, regp
->ramdac_a24
);
529 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_A34
, regp
->ramdac_a34
);
531 for (i
= 0; i
< 38; i
++)
532 NVWriteRAMDAC(dev
, head
,
533 NV_PRAMDAC_CTV
+ 4*i
, regp
->ctv_regs
[i
]);
538 nv_save_state_vga(struct drm_device
*dev
, int head
,
539 struct nv04_mode_state
*state
)
541 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
544 regp
->MiscOutReg
= NVReadPRMVIO(dev
, head
, NV_PRMVIO_MISC__READ
);
546 for (i
= 0; i
< 25; i
++)
547 rd_cio_state(dev
, head
, regp
, i
);
549 NVSetEnablePalette(dev
, head
, true);
550 for (i
= 0; i
< 21; i
++)
551 regp
->Attribute
[i
] = NVReadVgaAttr(dev
, head
, i
);
552 NVSetEnablePalette(dev
, head
, false);
554 for (i
= 0; i
< 9; i
++)
555 regp
->Graphics
[i
] = NVReadVgaGr(dev
, head
, i
);
557 for (i
= 0; i
< 5; i
++)
558 regp
->Sequencer
[i
] = NVReadVgaSeq(dev
, head
, i
);
562 nv_load_state_vga(struct drm_device
*dev
, int head
,
563 struct nv04_mode_state
*state
)
565 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
568 NVWritePRMVIO(dev
, head
, NV_PRMVIO_MISC__WRITE
, regp
->MiscOutReg
);
570 for (i
= 0; i
< 5; i
++)
571 NVWriteVgaSeq(dev
, head
, i
, regp
->Sequencer
[i
]);
573 nv_lock_vga_crtc_base(dev
, head
, false);
574 for (i
= 0; i
< 25; i
++)
575 wr_cio_state(dev
, head
, regp
, i
);
576 nv_lock_vga_crtc_base(dev
, head
, true);
578 for (i
= 0; i
< 9; i
++)
579 NVWriteVgaGr(dev
, head
, i
, regp
->Graphics
[i
]);
581 NVSetEnablePalette(dev
, head
, true);
582 for (i
= 0; i
< 21; i
++)
583 NVWriteVgaAttr(dev
, head
, i
, regp
->Attribute
[i
]);
584 NVSetEnablePalette(dev
, head
, false);
588 nv_save_state_ext(struct drm_device
*dev
, int head
,
589 struct nv04_mode_state
*state
)
591 struct nouveau_drm
*drm
= nouveau_drm(dev
);
592 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
595 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_LCD__INDEX
);
596 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_RPC0_INDEX
);
597 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_RPC1_INDEX
);
598 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_LSR_INDEX
);
599 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_PIXEL_INDEX
);
600 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_HEB__INDEX
);
601 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_ENH_INDEX
);
603 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_FF_INDEX
);
604 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_FFLWM__INDEX
);
605 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_21
);
607 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_KELVIN
)
608 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_47
);
610 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_RANKINE
)
611 rd_cio_state(dev
, head
, regp
, 0x9f);
613 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_49
);
614 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR0_INDEX
);
615 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR1_INDEX
);
616 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR2_INDEX
);
617 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_ILACE__INDEX
);
619 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
) {
620 regp
->crtc_830
= NVReadCRTC(dev
, head
, NV_PCRTC_830
);
621 regp
->crtc_834
= NVReadCRTC(dev
, head
, NV_PCRTC_834
);
623 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_RANKINE
)
624 regp
->gpio_ext
= NVReadCRTC(dev
, head
, NV_PCRTC_GPIO_EXT
);
626 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CURIE
)
627 regp
->crtc_850
= NVReadCRTC(dev
, head
, NV_PCRTC_850
);
629 if (nv_two_heads(dev
))
630 regp
->crtc_eng_ctrl
= NVReadCRTC(dev
, head
, NV_PCRTC_ENGINE_CTRL
);
631 regp
->cursor_cfg
= NVReadCRTC(dev
, head
, NV_PCRTC_CURSOR_CONFIG
);
634 regp
->crtc_cfg
= NVReadCRTC(dev
, head
, NV_PCRTC_CONFIG
);
636 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_SCRATCH3__INDEX
);
637 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_SCRATCH4__INDEX
);
638 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
) {
639 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_EBR_INDEX
);
640 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_CSB
);
641 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_4B
);
642 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_TVOUT_LATENCY
);
644 /* NV11 and NV20 don't have this, they stop at 0x52. */
645 if (nv_gf4_disp_arch(dev
)) {
646 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_42
);
647 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_53
);
648 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_54
);
650 for (i
= 0; i
< 0x10; i
++)
651 regp
->CR58
[i
] = NVReadVgaCrtc5758(dev
, head
, i
);
652 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_59
);
653 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_5B
);
655 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_85
);
656 rd_cio_state(dev
, head
, regp
, NV_CIO_CRE_86
);
659 regp
->fb_start
= NVReadCRTC(dev
, head
, NV_PCRTC_START
);
663 nv_load_state_ext(struct drm_device
*dev
, int head
,
664 struct nv04_mode_state
*state
)
666 struct nouveau_drm
*drm
= nouveau_drm(dev
);
667 struct nvif_object
*device
= &drm
->client
.device
.object
;
668 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[head
];
672 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
) {
673 if (nv_two_heads(dev
))
674 /* setting ENGINE_CTRL (EC) *must* come before
675 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
676 * EC that should not be overwritten by writing stale EC
678 NVWriteCRTC(dev
, head
, NV_PCRTC_ENGINE_CTRL
, regp
->crtc_eng_ctrl
);
680 nvif_wr32(device
, NV_PVIDEO_STOP
, 1);
681 nvif_wr32(device
, NV_PVIDEO_INTR_EN
, 0);
682 nvif_wr32(device
, NV_PVIDEO_OFFSET_BUFF(0), 0);
683 nvif_wr32(device
, NV_PVIDEO_OFFSET_BUFF(1), 0);
684 nvif_wr32(device
, NV_PVIDEO_LIMIT(0), drm
->client
.device
.info
.ram_size
- 1);
685 nvif_wr32(device
, NV_PVIDEO_LIMIT(1), drm
->client
.device
.info
.ram_size
- 1);
686 nvif_wr32(device
, NV_PVIDEO_UVPLANE_LIMIT(0), drm
->client
.device
.info
.ram_size
- 1);
687 nvif_wr32(device
, NV_PVIDEO_UVPLANE_LIMIT(1), drm
->client
.device
.info
.ram_size
- 1);
688 nvif_wr32(device
, NV_PBUS_POWERCTRL_2
, 0);
690 NVWriteCRTC(dev
, head
, NV_PCRTC_CURSOR_CONFIG
, regp
->cursor_cfg
);
691 NVWriteCRTC(dev
, head
, NV_PCRTC_830
, regp
->crtc_830
);
692 NVWriteCRTC(dev
, head
, NV_PCRTC_834
, regp
->crtc_834
);
694 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_RANKINE
)
695 NVWriteCRTC(dev
, head
, NV_PCRTC_GPIO_EXT
, regp
->gpio_ext
);
697 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CURIE
) {
698 NVWriteCRTC(dev
, head
, NV_PCRTC_850
, regp
->crtc_850
);
700 reg900
= NVReadRAMDAC(dev
, head
, NV_PRAMDAC_900
);
701 if (regp
->crtc_cfg
== NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC
)
702 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_900
, reg900
| 0x10000);
704 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_900
, reg900
& ~0x10000);
708 NVWriteCRTC(dev
, head
, NV_PCRTC_CONFIG
, regp
->crtc_cfg
);
710 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_RPC0_INDEX
);
711 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_RPC1_INDEX
);
712 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_LSR_INDEX
);
713 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_PIXEL_INDEX
);
714 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_LCD__INDEX
);
715 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_HEB__INDEX
);
716 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_ENH_INDEX
);
717 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_FF_INDEX
);
718 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_FFLWM__INDEX
);
720 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_KELVIN
)
721 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_47
);
723 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_RANKINE
)
724 wr_cio_state(dev
, head
, regp
, 0x9f);
726 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_49
);
727 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR0_INDEX
);
728 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR1_INDEX
);
729 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_HCUR_ADDR2_INDEX
);
730 if (drm
->client
.device
.info
.family
== NV_DEVICE_INFO_V0_CURIE
)
731 nv_fix_nv40_hw_cursor(dev
, head
);
732 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_ILACE__INDEX
);
734 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_SCRATCH3__INDEX
);
735 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_SCRATCH4__INDEX
);
736 if (drm
->client
.device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
) {
737 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_EBR_INDEX
);
738 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_CSB
);
739 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_4B
);
740 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_TVOUT_LATENCY
);
742 /* NV11 and NV20 stop at 0x52. */
743 if (nv_gf4_disp_arch(dev
)) {
744 if (drm
->client
.device
.info
.family
< NV_DEVICE_INFO_V0_KELVIN
) {
745 /* Not waiting for vertical retrace before modifying
746 CRE_53/CRE_54 causes lockups. */
747 nvif_msec(&drm
->client
.device
, 650,
748 if ( (nvif_rd32(device
, NV_PRMCIO_INP0__COLOR
) & 8))
751 nvif_msec(&drm
->client
.device
, 650,
752 if (!(nvif_rd32(device
, NV_PRMCIO_INP0__COLOR
) & 8))
757 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_42
);
758 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_53
);
759 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_54
);
761 for (i
= 0; i
< 0x10; i
++)
762 NVWriteVgaCrtc5758(dev
, head
, i
, regp
->CR58
[i
]);
763 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_59
);
764 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_5B
);
766 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_85
);
767 wr_cio_state(dev
, head
, regp
, NV_CIO_CRE_86
);
770 NVWriteCRTC(dev
, head
, NV_PCRTC_START
, regp
->fb_start
);
774 nv_save_state_palette(struct drm_device
*dev
, int head
,
775 struct nv04_mode_state
*state
)
777 struct nvif_object
*device
= &nouveau_drm(dev
)->client
.device
.object
;
778 int head_offset
= head
* NV_PRMDIO_SIZE
, i
;
780 nvif_wr08(device
, NV_PRMDIO_PIXEL_MASK
+ head_offset
,
781 NV_PRMDIO_PIXEL_MASK_MASK
);
782 nvif_wr08(device
, NV_PRMDIO_READ_MODE_ADDRESS
+ head_offset
, 0x0);
784 for (i
= 0; i
< 768; i
++) {
785 state
->crtc_reg
[head
].DAC
[i
] = nvif_rd08(device
,
786 NV_PRMDIO_PALETTE_DATA
+ head_offset
);
789 NVSetEnablePalette(dev
, head
, false);
793 nouveau_hw_load_state_palette(struct drm_device
*dev
, int head
,
794 struct nv04_mode_state
*state
)
796 struct nvif_object
*device
= &nouveau_drm(dev
)->client
.device
.object
;
797 int head_offset
= head
* NV_PRMDIO_SIZE
, i
;
799 nvif_wr08(device
, NV_PRMDIO_PIXEL_MASK
+ head_offset
,
800 NV_PRMDIO_PIXEL_MASK_MASK
);
801 nvif_wr08(device
, NV_PRMDIO_WRITE_MODE_ADDRESS
+ head_offset
, 0x0);
803 for (i
= 0; i
< 768; i
++) {
804 nvif_wr08(device
, NV_PRMDIO_PALETTE_DATA
+ head_offset
,
805 state
->crtc_reg
[head
].DAC
[i
]);
808 NVSetEnablePalette(dev
, head
, false);
811 void nouveau_hw_save_state(struct drm_device
*dev
, int head
,
812 struct nv04_mode_state
*state
)
814 struct nouveau_drm
*drm
= nouveau_drm(dev
);
816 if (drm
->client
.device
.info
.chipset
== 0x11)
817 /* NB: no attempt is made to restore the bad pll later on */
818 nouveau_hw_fix_bad_vpll(dev
, head
);
819 nv_save_state_ramdac(dev
, head
, state
);
820 nv_save_state_vga(dev
, head
, state
);
821 nv_save_state_palette(dev
, head
, state
);
822 nv_save_state_ext(dev
, head
, state
);
825 void nouveau_hw_load_state(struct drm_device
*dev
, int head
,
826 struct nv04_mode_state
*state
)
828 NVVgaProtect(dev
, head
, true);
829 nv_load_state_ramdac(dev
, head
, state
);
830 nv_load_state_ext(dev
, head
, state
);
831 nouveau_hw_load_state_palette(dev
, head
, state
);
832 nv_load_state_vga(dev
, head
, state
);
833 NVVgaProtect(dev
, head
, false);