drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c

   1 /*
   2  * Copyright 2019 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include <core/subdev.h>
  23 #include <nvfw/acr.h>
  24
  25 void
  26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)
  27 {
  28         nvkm_debug(subdev, "wprHeader\n");
  29         nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
  30         nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
  31         nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
  32         nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
  33         nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
  34 }
  35
  36 void
  37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)
  38 {
  39         nvkm_debug(subdev, "wprHeader\n");
  40         nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
  41         nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
  42         nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
  43         nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
  44         nvkm_debug(subdev, "\tbinVersion    : %d\n", hdr->bin_version);
  45         nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
  46 }
  47
  48 void
  49 lsb_header_tail_dump(struct nvkm_subdev *subdev,
  50                         struct lsb_header_tail *hdr)
  51 {
  52         nvkm_debug(subdev, "lsbHeader\n");
  53         nvkm_debug(subdev, "\tucodeOff      : 0x%x\n", hdr->ucode_off);
  54         nvkm_debug(subdev, "\tucodeSize     : 0x%x\n", hdr->ucode_size);
  55         nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
  56         nvkm_debug(subdev, "\tblCodeSize    : 0x%x\n", hdr->bl_code_size);
  57         nvkm_debug(subdev, "\tblImemOff     : 0x%x\n", hdr->bl_imem_off);
  58         nvkm_debug(subdev, "\tblDataOff     : 0x%x\n", hdr->bl_data_off);
  59         nvkm_debug(subdev, "\tblDataSize    : 0x%x\n", hdr->bl_data_size);
  60         nvkm_debug(subdev, "\tappCodeOff    : 0x%x\n", hdr->app_code_off);
  61         nvkm_debug(subdev, "\tappCodeSize   : 0x%x\n", hdr->app_code_size);
  62         nvkm_debug(subdev, "\tappDataOff    : 0x%x\n", hdr->app_data_off);
  63         nvkm_debug(subdev, "\tappDataSize   : 0x%x\n", hdr->app_data_size);
  64         nvkm_debug(subdev, "\tflags         : 0x%x\n", hdr->flags);
  65 }
  66
  67 void
  68 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)
  69 {
  70         lsb_header_tail_dump(subdev, &hdr->tail);
  71 }
  72
  73 void
  74 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)
  75 {
  76         lsb_header_tail_dump(subdev, &hdr->tail);
  77 }
  78
  79 void
  80 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)
  81 {
  82         int i;
  83
  84         nvkm_debug(subdev, "acrDesc\n");
  85         nvkm_debug(subdev, "\twprRegionId  : %d\n", hdr->wpr_region_id);
  86         nvkm_debug(subdev, "\twprOffset    : 0x%x\n", hdr->wpr_offset);
  87         nvkm_debug(subdev, "\tmmuMemRange  : 0x%x\n",
  88                    hdr->mmu_mem_range);
  89         nvkm_debug(subdev, "\tnoRegions    : %d\n",
  90                    hdr->regions.no_regions);
  91
  92         for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
  93                 nvkm_debug(subdev, "\tregion[%d]    :\n", i);
  94                 nvkm_debug(subdev, "\t  startAddr  : 0x%x\n",
  95                            hdr->regions.region_props[i].start_addr);
  96                 nvkm_debug(subdev, "\t  endAddr    : 0x%x\n",
  97                            hdr->regions.region_props[i].end_addr);
  98                 nvkm_debug(subdev, "\t  regionId   : %d\n",
  99                            hdr->regions.region_props[i].region_id);
 100                 nvkm_debug(subdev, "\t  readMask   : 0x%x\n",
 101                            hdr->regions.region_props[i].read_mask);
 102                 nvkm_debug(subdev, "\t  writeMask  : 0x%x\n",
 103                            hdr->regions.region_props[i].write_mask);
 104                 nvkm_debug(subdev, "\t  clientMask : 0x%x\n",
 105                            hdr->regions.region_props[i].client_mask);
 106         }
 107
 108         nvkm_debug(subdev, "\tucodeBlobSize: %d\n",
 109                    hdr->ucode_blob_size);
 110         nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",
 111                    hdr->ucode_blob_base);
 112         nvkm_debug(subdev, "\tvprEnabled   : %d\n",
 113                    hdr->vpr_desc.vpr_enabled);
 114         nvkm_debug(subdev, "\tvprStart     : 0x%x\n",
 115                    hdr->vpr_desc.vpr_start);
 116         nvkm_debug(subdev, "\tvprEnd       : 0x%x\n",
 117                    hdr->vpr_desc.vpr_end);
 118         nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
 119                    hdr->vpr_desc.hdcp_policies);
 120 }
 121
 122 void
 123 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)
 124 {
 125         int i;
 126
 127         nvkm_debug(subdev, "acrDesc\n");
 128         nvkm_debug(subdev, "\twprRegionId         : %d\n", hdr->wpr_region_id);
 129         nvkm_debug(subdev, "\twprOffset           : 0x%x\n", hdr->wpr_offset);
 130         nvkm_debug(subdev, "\tmmuMemoryRange      : 0x%x\n",
 131                    hdr->mmu_memory_range);
 132         nvkm_debug(subdev, "\tnoRegions           : %d\n",
 133                    hdr->regions.no_regions);
 134
 135         for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
 136                 nvkm_debug(subdev, "\tregion[%d]           :\n", i);
 137                 nvkm_debug(subdev, "\t  startAddr         : 0x%x\n",
 138                            hdr->regions.region_props[i].start_addr);
 139                 nvkm_debug(subdev, "\t  endAddr           : 0x%x\n",
 140                            hdr->regions.region_props[i].end_addr);
 141                 nvkm_debug(subdev, "\t  regionId          : %d\n",
 142                            hdr->regions.region_props[i].region_id);
 143                 nvkm_debug(subdev, "\t  readMask          : 0x%x\n",
 144                            hdr->regions.region_props[i].read_mask);
 145                 nvkm_debug(subdev, "\t  writeMask         : 0x%x\n",
 146                            hdr->regions.region_props[i].write_mask);
 147                 nvkm_debug(subdev, "\t  clientMask        : 0x%x\n",
 148                            hdr->regions.region_props[i].client_mask);
 149                 nvkm_debug(subdev, "\t  shadowMemStartAddr: 0x%x\n",
 150                            hdr->regions.region_props[i].shadow_mem_start_addr);
 151         }
 152
 153         nvkm_debug(subdev, "\tucodeBlobSize       : %d\n",
 154                    hdr->ucode_blob_size);
 155         nvkm_debug(subdev, "\tucodeBlobBase       : 0x%llx\n",
 156                    hdr->ucode_blob_base);
 157         nvkm_debug(subdev, "\tvprEnabled          : %d\n",
 158                    hdr->vpr_desc.vpr_enabled);
 159         nvkm_debug(subdev, "\tvprStart            : 0x%x\n",
 160                    hdr->vpr_desc.vpr_start);
 161         nvkm_debug(subdev, "\tvprEnd              : 0x%x\n",
 162                    hdr->vpr_desc.vpr_end);
 163         nvkm_debug(subdev, "\thdcpPolicies        : 0x%x\n",
 164                    hdr->vpr_desc.hdcp_policies);
 165 }