drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c

   1 /*
   2  * Copyright 2019 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "priv.h"
  23
  24 #include <core/firmware.h>
  25 #include <core/memory.h>
  26 #include <subdev/gsp.h>
  27 #include <subdev/pmu.h>
  28 #include <engine/sec2.h>
  29
  30 #include <nvfw/acr.h>
  31
  32 static int
  33 tu102_acr_init(struct nvkm_acr *acr)
  34 {
  35         int ret = nvkm_acr_hsf_boot(acr, "AHESASC");
  36         if (ret)
  37                 return ret;
  38
  39         return nvkm_acr_hsf_boot(acr, "ASB");
  40 }
  41
  42 static int
  43 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
  44 {
  45         struct nvkm_acr_lsfw *lsfw;
  46         u32 offset = 0;
  47         int ret;
  48
  49         /*XXX: shared sub-WPR headers, fill terminator for now. */
  50         nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
  51
  52         /* Fill per-LSF structures. */
  53         list_for_each_entry(lsfw, &acr->lsfw, head) {
  54                 struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
  55                 struct wpr_header_v1 hdr = {
  56                         .falcon_id = lsfw->id,
  57                         .lsb_offset = lsfw->offset.lsb,
  58                         .bootstrap_owner = NVKM_ACR_LSF_GSPLITE,
  59                         .lazy_bootstrap = 1,
  60                         .bin_version = sig->version,
  61                         .status = WPR_HEADER_V1_STATUS_COPY,
  62                 };
  63
  64                 /* Write WPR header. */
  65                 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
  66                 offset += sizeof(hdr);
  67
  68                 /* Write LSB header. */
  69                 ret = gp102_acr_wpr_build_lsb(acr, lsfw);
  70                 if (ret)
  71                         return ret;
  72
  73                 /* Write ucode image. */
  74                 nvkm_wobj(acr->wpr, lsfw->offset.img,
  75                                     lsfw->img.data,
  76                                     lsfw->img.size);
  77
  78                 /* Write bootloader data. */
  79                 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
  80         }
  81
  82         /* Finalise WPR. */
  83         nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
  84         return 0;
  85 }
  86
  87 static int
  88 tu102_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
  89 {
  90         return gm200_acr_hsfw_boot(acr, hsf, 0, 0);
  91 }
  92
  93 static int
  94 tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw,
  95                     const char *name, int version,
  96                     const struct nvkm_acr_hsf_fwif *fwif)
  97 {
  98         return 0;
  99 }
 100
 101 MODULE_FIRMWARE("nvidia/tu102/acr/unload_bl.bin");
 102 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_unload.bin");
 103
 104 MODULE_FIRMWARE("nvidia/tu104/acr/unload_bl.bin");
 105 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin");
 106
 107 MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
 108 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
 109
 110 static const struct nvkm_acr_hsf_fwif
 111 tu102_acr_unload_fwif[] = {
 112         {  0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
 113         { -1, tu102_acr_hsfw_nofw },
 114         {}
 115 };
 116
 117 static int
 118 tu102_acr_asb_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
 119 {
 120         return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->gsp->falcon);
 121 }
 122
 123 static const struct nvkm_acr_hsf_func
 124 tu102_acr_asb_0 = {
 125         .load = tu102_acr_asb_load,
 126         .boot = tu102_acr_hsfw_boot,
 127         .bld = gp108_acr_hsfw_bld,
 128 };
 129
 130 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
 131 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
 132 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
 133
 134 static const struct nvkm_acr_hsf_fwif
 135 tu102_acr_asb_fwif[] = {
 136         {  0, nvkm_acr_hsfw_load, &tu102_acr_asb_0 },
 137         { -1, tu102_acr_hsfw_nofw },
 138         {}
 139 };
 140
 141 static const struct nvkm_acr_hsf_func
 142 tu102_acr_ahesasc_0 = {
 143         .load = gp102_acr_load_load,
 144         .boot = tu102_acr_hsfw_boot,
 145         .bld = gp108_acr_hsfw_bld,
 146 };
 147
 148 MODULE_FIRMWARE("nvidia/tu102/acr/bl.bin");
 149 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_ahesasc.bin");
 150
 151 MODULE_FIRMWARE("nvidia/tu104/acr/bl.bin");
 152 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin");
 153
 154 MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
 155 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
 156
 157 static const struct nvkm_acr_hsf_fwif
 158 tu102_acr_ahesasc_fwif[] = {
 159         {  0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 },
 160         { -1, tu102_acr_hsfw_nofw },
 161         {}
 162 };
 163
 164 static const struct nvkm_acr_func
 165 tu102_acr = {
 166         .ahesasc = tu102_acr_ahesasc_fwif,
 167         .asb = tu102_acr_asb_fwif,
 168         .unload = tu102_acr_unload_fwif,
 169         .wpr_parse = gp102_acr_wpr_parse,
 170         .wpr_layout = gp102_acr_wpr_layout,
 171         .wpr_alloc = gp102_acr_wpr_alloc,
 172         .wpr_patch = gp102_acr_wpr_patch,
 173         .wpr_build = tu102_acr_wpr_build,
 174         .wpr_check = gm200_acr_wpr_check,
 175         .init = tu102_acr_init,
 176 };
 177
 178 static int
 179 tu102_acr_load(struct nvkm_acr *acr, int version,
 180                const struct nvkm_acr_fwif *fwif)
 181 {
 182         struct nvkm_subdev *subdev = &acr->subdev;
 183         const struct nvkm_acr_hsf_fwif *hsfwif;
 184
 185         hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "AcrAHESASC",
 186                                     acr, "acr/bl", "acr/ucode_ahesasc",
 187                                     "AHESASC");
 188         if (IS_ERR(hsfwif))
 189                 return PTR_ERR(hsfwif);
 190
 191         hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "AcrASB",
 192                                     acr, "acr/bl", "acr/ucode_asb", "ASB");
 193         if (IS_ERR(hsfwif))
 194                 return PTR_ERR(hsfwif);
 195
 196         hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
 197                                     acr, "acr/unload_bl", "acr/ucode_unload",
 198                                     "unload");
 199         if (IS_ERR(hsfwif))
 200                 return PTR_ERR(hsfwif);
 201
 202         return 0;
 203 }
 204
 205 static const struct nvkm_acr_fwif
 206 tu102_acr_fwif[] = {
 207         {  0, tu102_acr_load, &tu102_acr },
 208         {}
 209 };
 210
 211 int
 212 tu102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
 213 {
 214         return nvkm_acr_new_(tu102_acr_fwif, device, index, pacr);
 215 }