drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c

   1 /*
   2  * Copyright 2015 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "nv50.h"
  25
  26 #include <subdev/timer.h>
  27
  28 void
  29 g84_bar_flush(struct nvkm_bar *bar)
  30 {
  31         struct nvkm_device *device = bar->subdev.device;
  32         unsigned long flags;
  33         spin_lock_irqsave(&bar->lock, flags);
  34         nvkm_wr32(device, 0x070000, 0x00000001);
  35         nvkm_msec(device, 2000,
  36                 if (!(nvkm_rd32(device, 0x070000) & 0x00000002))
  37                         break;
  38         );
  39         spin_unlock_irqrestore(&bar->lock, flags);
  40 }
  41
  42 static const struct nvkm_bar_func
  43 g84_bar_func = {
  44         .dtor = nv50_bar_dtor,
  45         .oneinit = nv50_bar_oneinit,
  46         .init = nv50_bar_init,
  47         .bar1.init = nv50_bar_bar1_init,
  48         .bar1.fini = nv50_bar_bar1_fini,
  49         .bar1.wait = nv50_bar_bar1_wait,
  50         .bar1.vmm = nv50_bar_bar1_vmm,
  51         .bar2.init = nv50_bar_bar2_init,
  52         .bar2.fini = nv50_bar_bar2_fini,
  53         .bar2.wait = nv50_bar_bar1_wait,
  54         .bar2.vmm = nv50_bar_bar2_vmm,
  55         .flush = g84_bar_flush,
  56 };
  57
  58 int
  59 g84_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
  60 {
  61         return nv50_bar_new_(&g84_bar_func, device, index, 0x200, pbar);
  62 }