drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NV50_CLK_H__
   3 #define __NV50_CLK_H__
   4 #define nv50_clk(p) container_of((p), struct nv50_clk, base)
   5 #include "priv.h"
   6
   7 #include <subdev/bus/hwsq.h>
   8
   9 struct nv50_clk_hwsq {
  10         struct hwsq base;
  11         struct hwsq_reg r_fifo;
  12         struct hwsq_reg r_spll[2];
  13         struct hwsq_reg r_nvpll[2];
  14         struct hwsq_reg r_divs;
  15         struct hwsq_reg r_mast;
  16 };
  17
  18 struct nv50_clk {
  19         struct nvkm_clk base;
  20         struct nv50_clk_hwsq hwsq;
  21 };
  22
  23 int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
  24                   bool, struct nvkm_clk **);
  25 int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src);
  26 int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
  27 int nv50_clk_prog(struct nvkm_clk *);
  28 void nv50_clk_tidy(struct nvkm_clk *);
  29 #endif