?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / omapdrm / dss / dispc.c
blobdbb90f2d2ccde5973db67530924c358059cec747
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * Some code and ideas taken from drivers/video/omap/ driver
7 * by Imre Deak.
8 */
9
10 #define DSS_SUBSYS_NAME "DISPC"
11
12 #include <linux/kernel.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/vmalloc.h>
15 #include <linux/export.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/jiffies.h>
19 #include <linux/seq_file.h>
20 #include <linux/delay.h>
21 #include <linux/workqueue.h>
22 #include <linux/hardirq.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/sizes.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/component.h>
31 #include <linux/sys_soc.h>
32 #include <drm/drm_fourcc.h>
33 #include <drm/drm_blend.h>
34
35 #include "omapdss.h"
36 #include "dss.h"
37 #include "dispc.h"
38
39 struct dispc_device;
40
41 /* DISPC */
42 #define DISPC_SZ_REGS SZ_4K
43
44 enum omap_burst_size {
45 BURST_SIZE_X2 = 0,
46 BURST_SIZE_X4 = 1,
47 BURST_SIZE_X8 = 2,
48 };
49
50 #define REG_GET(dispc, idx, start, end) \
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
52
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
56
57 /* DISPC has feature id */
58 enum dispc_feature_id {
59 FEAT_LCDENABLEPOL,
60 FEAT_LCDENABLESIGNAL,
61 FEAT_PCKFREEENABLE,
62 FEAT_FUNCGATED,
63 FEAT_MGR_LCD2,
64 FEAT_MGR_LCD3,
65 FEAT_LINEBUFFERSPLIT,
66 FEAT_ROWREPEATENABLE,
67 FEAT_RESIZECONF,
68 /* Independent core clk divider */
69 FEAT_CORE_CLK_DIV,
70 FEAT_HANDLE_UV_SEPARATE,
71 FEAT_ATTR2,
72 FEAT_CPR,
73 FEAT_PRELOAD,
74 FEAT_FIR_COEF_V,
75 FEAT_ALPHA_FIXED_ZORDER,
76 FEAT_ALPHA_FREE_ZORDER,
77 FEAT_FIFO_MERGE,
78 /* An unknown HW bug causing the normal FIFO thresholds not to work */
79 FEAT_OMAP3_DSI_FIFO_BUG,
80 FEAT_BURST_2D,
81 FEAT_MFLAG,
82 };
83
84 struct dispc_features {
85 u8 sw_start;
86 u8 fp_start;
87 u8 bp_start;
88 u16 sw_max;
89 u16 vp_max;
90 u16 hp_max;
91 u8 mgr_width_start;
92 u8 mgr_height_start;
93 u16 mgr_width_max;
94 u16 mgr_height_max;
95 unsigned long max_lcd_pclk;
96 unsigned long max_tv_pclk;
97 unsigned int max_downscale;
98 unsigned int max_line_width;
99 unsigned int min_pcd;
100 int (*calc_scaling)(struct dispc_device *dispc,
101 unsigned long pclk, unsigned long lclk,
102 const struct videomode *vm,
103 u16 width, u16 height, u16 out_width, u16 out_height,
104 u32 fourcc, bool *five_taps,
105 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
106 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
107 unsigned long (*calc_core_clk) (unsigned long pclk,
108 u16 width, u16 height, u16 out_width, u16 out_height,
109 bool mem_to_mem);
110 u8 num_fifos;
111 const enum dispc_feature_id *features;
112 unsigned int num_features;
113 const struct dss_reg_field *reg_fields;
114 const unsigned int num_reg_fields;
115 const enum omap_overlay_caps *overlay_caps;
116 const u32 **supported_color_modes;
117 const u32 *supported_scaler_color_modes;
118 unsigned int num_mgrs;
119 unsigned int num_ovls;
120 unsigned int buffer_size_unit;
121 unsigned int burst_size_unit;
122
123 /* swap GFX & WB fifos */
124 bool gfx_fifo_workaround:1;
125
126 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
127 bool no_framedone_tv:1;
128
129 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
130 bool mstandby_workaround:1;
131
132 bool set_max_preload:1;
133
134 /* PIXEL_INC is not added to the last pixel of a line */
135 bool last_pixel_inc_missing:1;
136
137 /* POL_FREQ has ALIGN bit */
138 bool supports_sync_align:1;
139
140 bool has_writeback:1;
141
142 bool supports_double_pixel:1;
143
144 /*
145 * Field order for VENC is different than HDMI. We should handle this in
146 * some intelligent manner, but as the SoCs have either HDMI or VENC,
147 * never both, we can just use this flag for now.
148 */
149 bool reverse_ilace_field_order:1;
150
151 bool has_gamma_table:1;
152
153 bool has_gamma_i734_bug:1;
154 };
155
156 #define DISPC_MAX_NR_FIFOS 5
157 #define DISPC_MAX_CHANNEL_GAMMA 4
158
159 struct dispc_device {
160 struct platform_device *pdev;
161 void __iomem *base;
162 struct dss_device *dss;
163
164 struct dss_debugfs_entry *debugfs;
165
166 int irq;
167 irq_handler_t user_handler;
168 void *user_data;
169
170 unsigned long core_clk_rate;
171 unsigned long tv_pclk_rate;
172
173 u32 fifo_size[DISPC_MAX_NR_FIFOS];
174 /* maps which plane is using a fifo. fifo-id -> plane-id */
175 int fifo_assignment[DISPC_MAX_NR_FIFOS];
176
177 bool ctx_valid;
178 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
179
180 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
181
182 const struct dispc_features *feat;
183
184 bool is_enabled;
185
186 struct regmap *syscon_pol;
187 u32 syscon_pol_offset;
188 };
189
190 enum omap_color_component {
191 /* used for all color formats for OMAP3 and earlier
192 * and for RGB and Y color component on OMAP4
193 */
194 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
195 /* used for UV component for
196 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12
197 * color formats on OMAP4
198 */
199 DISPC_COLOR_COMPONENT_UV = 1 << 1,
200 };
201
202 enum mgr_reg_fields {
203 DISPC_MGR_FLD_ENABLE,
204 DISPC_MGR_FLD_STNTFT,
205 DISPC_MGR_FLD_GO,
206 DISPC_MGR_FLD_TFTDATALINES,
207 DISPC_MGR_FLD_STALLMODE,
208 DISPC_MGR_FLD_TCKENABLE,
209 DISPC_MGR_FLD_TCKSELECTION,
210 DISPC_MGR_FLD_CPR,
211 DISPC_MGR_FLD_FIFOHANDCHECK,
212 /* used to maintain a count of the above fields */
213 DISPC_MGR_FLD_NUM,
214 };
215
216 /* DISPC register field id */
217 enum dispc_feat_reg_field {
218 FEAT_REG_FIRHINC,
219 FEAT_REG_FIRVINC,
220 FEAT_REG_FIFOHIGHTHRESHOLD,
221 FEAT_REG_FIFOLOWTHRESHOLD,
222 FEAT_REG_FIFOSIZE,
223 FEAT_REG_HORIZONTALACCU,
224 FEAT_REG_VERTICALACCU,
225 };
226
227 struct dispc_reg_field {
228 u16 reg;
229 u8 high;
230 u8 low;
231 };
232
233 struct dispc_gamma_desc {
234 u32 len;
235 u32 bits;
236 u16 reg;
237 bool has_index;
238 };
239
240 static const struct {
241 const char *name;
242 u32 vsync_irq;
243 u32 framedone_irq;
244 u32 sync_lost_irq;
245 struct dispc_gamma_desc gamma;
246 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
247 } mgr_desc[] = {
248 [OMAP_DSS_CHANNEL_LCD] = {
249 .name = "LCD",
250 .vsync_irq = DISPC_IRQ_VSYNC,
251 .framedone_irq = DISPC_IRQ_FRAMEDONE,
252 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
253 .gamma = {
254 .len = 256,
255 .bits = 8,
256 .reg = DISPC_GAMMA_TABLE0,
257 .has_index = true,
258 },
259 .reg_desc = {
260 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
261 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
262 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
263 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
264 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
265 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
266 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
267 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
268 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
269 },
270 },
271 [OMAP_DSS_CHANNEL_DIGIT] = {
272 .name = "DIGIT",
273 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
274 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
275 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
276 .gamma = {
277 .len = 1024,
278 .bits = 10,
279 .reg = DISPC_GAMMA_TABLE2,
280 .has_index = false,
281 },
282 .reg_desc = {
283 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
284 [DISPC_MGR_FLD_STNTFT] = { },
285 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
286 [DISPC_MGR_FLD_TFTDATALINES] = { },
287 [DISPC_MGR_FLD_STALLMODE] = { },
288 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
289 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
290 [DISPC_MGR_FLD_CPR] = { },
291 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
292 },
293 },
294 [OMAP_DSS_CHANNEL_LCD2] = {
295 .name = "LCD2",
296 .vsync_irq = DISPC_IRQ_VSYNC2,
297 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
298 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
299 .gamma = {
300 .len = 256,
301 .bits = 8,
302 .reg = DISPC_GAMMA_TABLE1,
303 .has_index = true,
304 },
305 .reg_desc = {
306 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
307 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
308 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
309 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
310 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
311 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
312 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
313 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
314 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
315 },
316 },
317 [OMAP_DSS_CHANNEL_LCD3] = {
318 .name = "LCD3",
319 .vsync_irq = DISPC_IRQ_VSYNC3,
320 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
321 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
322 .gamma = {
323 .len = 256,
324 .bits = 8,
325 .reg = DISPC_GAMMA_TABLE3,
326 .has_index = true,
327 },
328 .reg_desc = {
329 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
330 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
331 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
332 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
333 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
334 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
335 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
336 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
337 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
338 },
339 },
340 };
341
342 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
344 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
345 enum omap_channel channel);
346 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
347 enum omap_channel channel);
348
349 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
350 enum omap_plane_id plane);
351 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
352 enum omap_plane_id plane);
353
354 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
355
356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)
357 {
358 __raw_writel(val, dispc->base + idx);
359 }
360
361 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx)
362 {
363 return __raw_readl(dispc->base + idx);
364 }
365
366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel,
367 enum mgr_reg_fields regfld)
368 {
369 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
370
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low);
372 }
373
374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel,
375 enum mgr_reg_fields regfld, int val)
376 {
377 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
378
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low);
380 }
381
382 static int dispc_get_num_ovls(struct dispc_device *dispc)
383 {
384 return dispc->feat->num_ovls;
385 }
386
387 static int dispc_get_num_mgrs(struct dispc_device *dispc)
388 {
389 return dispc->feat->num_mgrs;
390 }
391
392 static void dispc_get_reg_field(struct dispc_device *dispc,
393 enum dispc_feat_reg_field id,
394 u8 *start, u8 *end)
395 {
396 BUG_ON(id >= dispc->feat->num_reg_fields);
397
398 *start = dispc->feat->reg_fields[id].start;
399 *end = dispc->feat->reg_fields[id].end;
400 }
401
402 static bool dispc_has_feature(struct dispc_device *dispc,
403 enum dispc_feature_id id)
404 {
405 unsigned int i;
406
407 for (i = 0; i < dispc->feat->num_features; i++) {
408 if (dispc->feat->features[i] == id)
409 return true;
410 }
411
412 return false;
413 }
414
415 #define SR(dispc, reg) \
416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
417 #define RR(dispc, reg) \
418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
419
420 static void dispc_save_context(struct dispc_device *dispc)
421 {
422 int i, j;
423
424 DSSDBG("dispc_save_context\n");
425
426 SR(dispc, IRQENABLE);
427 SR(dispc, CONTROL);
428 SR(dispc, CONFIG);
429 SR(dispc, LINE_NUMBER);
430 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
431 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
432 SR(dispc, GLOBAL_ALPHA);
433 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
434 SR(dispc, CONTROL2);
435 SR(dispc, CONFIG2);
436 }
437 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
438 SR(dispc, CONTROL3);
439 SR(dispc, CONFIG3);
440 }
441
442 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
443 SR(dispc, DEFAULT_COLOR(i));
444 SR(dispc, TRANS_COLOR(i));
445 SR(dispc, SIZE_MGR(i));
446 if (i == OMAP_DSS_CHANNEL_DIGIT)
447 continue;
448 SR(dispc, TIMING_H(i));
449 SR(dispc, TIMING_V(i));
450 SR(dispc, POL_FREQ(i));
451 SR(dispc, DIVISORo(i));
452
453 SR(dispc, DATA_CYCLE1(i));
454 SR(dispc, DATA_CYCLE2(i));
455 SR(dispc, DATA_CYCLE3(i));
456
457 if (dispc_has_feature(dispc, FEAT_CPR)) {
458 SR(dispc, CPR_COEF_R(i));
459 SR(dispc, CPR_COEF_G(i));
460 SR(dispc, CPR_COEF_B(i));
461 }
462 }
463
464 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
465 SR(dispc, OVL_BA0(i));
466 SR(dispc, OVL_BA1(i));
467 SR(dispc, OVL_POSITION(i));
468 SR(dispc, OVL_SIZE(i));
469 SR(dispc, OVL_ATTRIBUTES(i));
470 SR(dispc, OVL_FIFO_THRESHOLD(i));
471 SR(dispc, OVL_ROW_INC(i));
472 SR(dispc, OVL_PIXEL_INC(i));
473 if (dispc_has_feature(dispc, FEAT_PRELOAD))
474 SR(dispc, OVL_PRELOAD(i));
475 if (i == OMAP_DSS_GFX) {
476 SR(dispc, OVL_WINDOW_SKIP(i));
477 SR(dispc, OVL_TABLE_BA(i));
478 continue;
479 }
480 SR(dispc, OVL_FIR(i));
481 SR(dispc, OVL_PICTURE_SIZE(i));
482 SR(dispc, OVL_ACCU0(i));
483 SR(dispc, OVL_ACCU1(i));
484
485 for (j = 0; j < 8; j++)
486 SR(dispc, OVL_FIR_COEF_H(i, j));
487
488 for (j = 0; j < 8; j++)
489 SR(dispc, OVL_FIR_COEF_HV(i, j));
490
491 for (j = 0; j < 5; j++)
492 SR(dispc, OVL_CONV_COEF(i, j));
493
494 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
495 for (j = 0; j < 8; j++)
496 SR(dispc, OVL_FIR_COEF_V(i, j));
497 }
498
499 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
500 SR(dispc, OVL_BA0_UV(i));
501 SR(dispc, OVL_BA1_UV(i));
502 SR(dispc, OVL_FIR2(i));
503 SR(dispc, OVL_ACCU2_0(i));
504 SR(dispc, OVL_ACCU2_1(i));
505
506 for (j = 0; j < 8; j++)
507 SR(dispc, OVL_FIR_COEF_H2(i, j));
508
509 for (j = 0; j < 8; j++)
510 SR(dispc, OVL_FIR_COEF_HV2(i, j));
511
512 for (j = 0; j < 8; j++)
513 SR(dispc, OVL_FIR_COEF_V2(i, j));
514 }
515 if (dispc_has_feature(dispc, FEAT_ATTR2))
516 SR(dispc, OVL_ATTRIBUTES2(i));
517 }
518
519 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
520 SR(dispc, DIVISOR);
521
522 dispc->ctx_valid = true;
523
524 DSSDBG("context saved\n");
525 }
526
527 static void dispc_restore_context(struct dispc_device *dispc)
528 {
529 int i, j;
530
531 DSSDBG("dispc_restore_context\n");
532
533 if (!dispc->ctx_valid)
534 return;
535
536 /*RR(dispc, IRQENABLE);*/
537 /*RR(dispc, CONTROL);*/
538 RR(dispc, CONFIG);
539 RR(dispc, LINE_NUMBER);
540 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
541 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
542 RR(dispc, GLOBAL_ALPHA);
543 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
544 RR(dispc, CONFIG2);
545 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
546 RR(dispc, CONFIG3);
547
548 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
549 RR(dispc, DEFAULT_COLOR(i));
550 RR(dispc, TRANS_COLOR(i));
551 RR(dispc, SIZE_MGR(i));
552 if (i == OMAP_DSS_CHANNEL_DIGIT)
553 continue;
554 RR(dispc, TIMING_H(i));
555 RR(dispc, TIMING_V(i));
556 RR(dispc, POL_FREQ(i));
557 RR(dispc, DIVISORo(i));
558
559 RR(dispc, DATA_CYCLE1(i));
560 RR(dispc, DATA_CYCLE2(i));
561 RR(dispc, DATA_CYCLE3(i));
562
563 if (dispc_has_feature(dispc, FEAT_CPR)) {
564 RR(dispc, CPR_COEF_R(i));
565 RR(dispc, CPR_COEF_G(i));
566 RR(dispc, CPR_COEF_B(i));
567 }
568 }
569
570 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
571 RR(dispc, OVL_BA0(i));
572 RR(dispc, OVL_BA1(i));
573 RR(dispc, OVL_POSITION(i));
574 RR(dispc, OVL_SIZE(i));
575 RR(dispc, OVL_ATTRIBUTES(i));
576 RR(dispc, OVL_FIFO_THRESHOLD(i));
577 RR(dispc, OVL_ROW_INC(i));
578 RR(dispc, OVL_PIXEL_INC(i));
579 if (dispc_has_feature(dispc, FEAT_PRELOAD))
580 RR(dispc, OVL_PRELOAD(i));
581 if (i == OMAP_DSS_GFX) {
582 RR(dispc, OVL_WINDOW_SKIP(i));
583 RR(dispc, OVL_TABLE_BA(i));
584 continue;
585 }
586 RR(dispc, OVL_FIR(i));
587 RR(dispc, OVL_PICTURE_SIZE(i));
588 RR(dispc, OVL_ACCU0(i));
589 RR(dispc, OVL_ACCU1(i));
590
591 for (j = 0; j < 8; j++)
592 RR(dispc, OVL_FIR_COEF_H(i, j));
593
594 for (j = 0; j < 8; j++)
595 RR(dispc, OVL_FIR_COEF_HV(i, j));
596
597 for (j = 0; j < 5; j++)
598 RR(dispc, OVL_CONV_COEF(i, j));
599
600 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
601 for (j = 0; j < 8; j++)
602 RR(dispc, OVL_FIR_COEF_V(i, j));
603 }
604
605 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
606 RR(dispc, OVL_BA0_UV(i));
607 RR(dispc, OVL_BA1_UV(i));
608 RR(dispc, OVL_FIR2(i));
609 RR(dispc, OVL_ACCU2_0(i));
610 RR(dispc, OVL_ACCU2_1(i));
611
612 for (j = 0; j < 8; j++)
613 RR(dispc, OVL_FIR_COEF_H2(i, j));
614
615 for (j = 0; j < 8; j++)
616 RR(dispc, OVL_FIR_COEF_HV2(i, j));
617
618 for (j = 0; j < 8; j++)
619 RR(dispc, OVL_FIR_COEF_V2(i, j));
620 }
621 if (dispc_has_feature(dispc, FEAT_ATTR2))
622 RR(dispc, OVL_ATTRIBUTES2(i));
623 }
624
625 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
626 RR(dispc, DIVISOR);
627
628 /* enable last, because LCD & DIGIT enable are here */
629 RR(dispc, CONTROL);
630 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
631 RR(dispc, CONTROL2);
632 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
633 RR(dispc, CONTROL3);
634 /* clear spurious SYNC_LOST_DIGIT interrupts */
635 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT);
636
637 /*
638 * enable last so IRQs won't trigger before
639 * the context is fully restored
640 */
641 RR(dispc, IRQENABLE);
642
643 DSSDBG("context restored\n");
644 }
645
646 #undef SR
647 #undef RR
648
649 int dispc_runtime_get(struct dispc_device *dispc)
650 {
651 int r;
652
653 DSSDBG("dispc_runtime_get\n");
654
655 r = pm_runtime_get_sync(&dispc->pdev->dev);
656 WARN_ON(r < 0);
657 return r < 0 ? r : 0;
658 }
659
660 void dispc_runtime_put(struct dispc_device *dispc)
661 {
662 int r;
663
664 DSSDBG("dispc_runtime_put\n");
665
666 r = pm_runtime_put_sync(&dispc->pdev->dev);
667 WARN_ON(r < 0 && r != -ENOSYS);
668 }
669
670 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
671 enum omap_channel channel)
672 {
673 return mgr_desc[channel].vsync_irq;
674 }
675
676 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
677 enum omap_channel channel)
678 {
679 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv)
680 return 0;
681
682 return mgr_desc[channel].framedone_irq;
683 }
684
685 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
686 enum omap_channel channel)
687 {
688 return mgr_desc[channel].sync_lost_irq;
689 }
690
691 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc)
692 {
693 return DISPC_IRQ_FRAMEDONEWB;
694 }
695
696 static void dispc_mgr_enable(struct dispc_device *dispc,
697 enum omap_channel channel, bool enable)
698 {
699 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
700 /* flush posted write */
701 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
702 }
703
704 static bool dispc_mgr_is_enabled(struct dispc_device *dispc,
705 enum omap_channel channel)
706 {
707 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
708 }
709
710 static bool dispc_mgr_go_busy(struct dispc_device *dispc,
711 enum omap_channel channel)
712 {
713 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;
714 }
715
716 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)
717 {
718 WARN_ON(!dispc_mgr_is_enabled(dispc, channel));
719 WARN_ON(dispc_mgr_go_busy(dispc, channel));
720
721 DSSDBG("GO %s\n", mgr_desc[channel].name);
722
723 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);
724 }
725
726 static bool dispc_wb_go_busy(struct dispc_device *dispc)
727 {
728 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
729 }
730
731 static void dispc_wb_go(struct dispc_device *dispc)
732 {
733 enum omap_plane_id plane = OMAP_DSS_WB;
734 bool enable, go;
735
736 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
737
738 if (!enable)
739 return;
740
741 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
742 if (go) {
743 DSSERR("GO bit not down for WB\n");
744 return;
745 }
746
747 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6);
748 }
749
750 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc,
751 enum omap_plane_id plane, int reg,
752 u32 value)
753 {
754 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);
755 }
756
757 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc,
758 enum omap_plane_id plane, int reg,
759 u32 value)
760 {
761 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);
762 }
763
764 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc,
765 enum omap_plane_id plane, int reg,
766 u32 value)
767 {
768 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);
769 }
770
771 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc,
772 enum omap_plane_id plane, int reg,
773 u32 value)
774 {
775 BUG_ON(plane == OMAP_DSS_GFX);
776
777 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);
778 }
779
780 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc,
781 enum omap_plane_id plane, int reg,
782 u32 value)
783 {
784 BUG_ON(plane == OMAP_DSS_GFX);
785
786 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
787 }
788
789 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc,
790 enum omap_plane_id plane, int reg,
791 u32 value)
792 {
793 BUG_ON(plane == OMAP_DSS_GFX);
794
795 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);
796 }
797
798 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc,
799 enum omap_plane_id plane, int fir_hinc,
800 int fir_vinc, int five_taps,
801 enum omap_color_component color_comp)
802 {
803 const struct dispc_coef *h_coef, *v_coef;
804 int i;
805
806 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
807 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
808
809 if (!h_coef || !v_coef) {
810 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n",
811 __func__);
812 return;
813 }
814
815 for (i = 0; i < 8; i++) {
816 u32 h, hv;
817
818 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
819 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
820 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
821 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
822 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
823 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
824 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
825 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
826
827 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
828 dispc_ovl_write_firh_reg(dispc, plane, i, h);
829 dispc_ovl_write_firhv_reg(dispc, plane, i, hv);
830 } else {
831 dispc_ovl_write_firh2_reg(dispc, plane, i, h);
832 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv);
833 }
834
835 }
836
837 if (five_taps) {
838 for (i = 0; i < 8; i++) {
839 u32 v;
840 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
841 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
842 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
843 dispc_ovl_write_firv_reg(dispc, plane, i, v);
844 else
845 dispc_ovl_write_firv2_reg(dispc, plane, i, v);
846 }
847 }
848 }
849
850 struct csc_coef_yuv2rgb {
851 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr;
852 bool full_range;
853 };
854
855 struct csc_coef_rgb2yuv {
856 int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb;
857 bool full_range;
858 };
859
860 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc,
861 enum omap_plane_id plane,
862 const struct csc_coef_yuv2rgb *ct)
863 {
864 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
865
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
871
872 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
873
874 #undef CVAL
875 }
876
877 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc,
878 const struct csc_coef_rgb2yuv *ct)
879 {
880 const enum omap_plane_id plane = OMAP_DSS_WB;
881
882 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
883
884 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr));
885 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));
886 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));
887 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));
888 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));
889
890 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
891
892 #undef CVAL
893 }
894
895 static void dispc_setup_color_conv_coef(struct dispc_device *dispc)
896 {
897 int i;
898 int num_ovl = dispc_get_num_ovls(dispc);
899
900 /* YUV -> RGB, ITU-R BT.601, limited range */
901 const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = {
902 298, 0, 409, /* ry, rcb, rcr */
903 298, -100, -208, /* gy, gcb, gcr */
904 298, 516, 0, /* by, bcb, bcr */
905 false, /* limited range */
906 };
907
908 /* RGB -> YUV, ITU-R BT.601, limited range */
909 const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = {
910 66, 129, 25, /* yr, yg, yb */
911 -38, -74, 112, /* cbr, cbg, cbb */
912 112, -94, -18, /* crr, crg, crb */
913 false, /* limited range */
914 };
915
916 for (i = 1; i < num_ovl; i++)
917 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim);
918
919 if (dispc->feat->has_writeback)
920 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim);
921 }
922
923 static void dispc_ovl_set_ba0(struct dispc_device *dispc,
924 enum omap_plane_id plane, u32 paddr)
925 {
926 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);
927 }
928
929 static void dispc_ovl_set_ba1(struct dispc_device *dispc,
930 enum omap_plane_id plane, u32 paddr)
931 {
932 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);
933 }
934
935 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc,
936 enum omap_plane_id plane, u32 paddr)
937 {
938 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);
939 }
940
941 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc,
942 enum omap_plane_id plane, u32 paddr)
943 {
944 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);
945 }
946
947 static void dispc_ovl_set_pos(struct dispc_device *dispc,
948 enum omap_plane_id plane,
949 enum omap_overlay_caps caps, int x, int y)
950 {
951 u32 val;
952
953 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
954 return;
955
956 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
957
958 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
959 }
960
961 static void dispc_ovl_set_input_size(struct dispc_device *dispc,
962 enum omap_plane_id plane, int width,
963 int height)
964 {
965 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
966
967 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
968 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
969 else
970 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
971 }
972
973 static void dispc_ovl_set_output_size(struct dispc_device *dispc,
974 enum omap_plane_id plane, int width,
975 int height)
976 {
977 u32 val;
978
979 BUG_ON(plane == OMAP_DSS_GFX);
980
981 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
982
983 if (plane == OMAP_DSS_WB)
984 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
985 else
986 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
987 }
988
989 static void dispc_ovl_set_zorder(struct dispc_device *dispc,
990 enum omap_plane_id plane,
991 enum omap_overlay_caps caps, u8 zorder)
992 {
993 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
994 return;
995
996 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
997 }
998
999 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc)
1000 {
1001 int i;
1002
1003 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
1004 return;
1005
1006 for (i = 0; i < dispc_get_num_ovls(dispc); i++)
1007 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
1008 }
1009
1010 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc,
1011 enum omap_plane_id plane,
1012 enum omap_overlay_caps caps,
1013 bool enable)
1014 {
1015 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
1016 return;
1017
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1019 }
1020
1021 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc,
1022 enum omap_plane_id plane,
1023 enum omap_overlay_caps caps,
1024 u8 global_alpha)
1025 {
1026 static const unsigned int shifts[] = { 0, 8, 16, 24, };
1027 int shift;
1028
1029 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
1030 return;
1031
1032 shift = shifts[plane];
1033 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
1034 }
1035
1036 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc,
1037 enum omap_plane_id plane, s32 inc)
1038 {
1039 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);
1040 }
1041
1042 static void dispc_ovl_set_row_inc(struct dispc_device *dispc,
1043 enum omap_plane_id plane, s32 inc)
1044 {
1045 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);
1046 }
1047
1048 static void dispc_ovl_set_color_mode(struct dispc_device *dispc,
1049 enum omap_plane_id plane, u32 fourcc)
1050 {
1051 u32 m = 0;
1052 if (plane != OMAP_DSS_GFX) {
1053 switch (fourcc) {
1054 case DRM_FORMAT_NV12:
1055 m = 0x0; break;
1056 case DRM_FORMAT_XRGB4444:
1057 m = 0x1; break;
1058 case DRM_FORMAT_RGBA4444:
1059 m = 0x2; break;
1060 case DRM_FORMAT_RGBX4444:
1061 m = 0x4; break;
1062 case DRM_FORMAT_ARGB4444:
1063 m = 0x5; break;
1064 case DRM_FORMAT_RGB565:
1065 m = 0x6; break;
1066 case DRM_FORMAT_ARGB1555:
1067 m = 0x7; break;
1068 case DRM_FORMAT_XRGB8888:
1069 m = 0x8; break;
1070 case DRM_FORMAT_RGB888:
1071 m = 0x9; break;
1072 case DRM_FORMAT_YUYV:
1073 m = 0xa; break;
1074 case DRM_FORMAT_UYVY:
1075 m = 0xb; break;
1076 case DRM_FORMAT_ARGB8888:
1077 m = 0xc; break;
1078 case DRM_FORMAT_RGBA8888:
1079 m = 0xd; break;
1080 case DRM_FORMAT_RGBX8888:
1081 m = 0xe; break;
1082 case DRM_FORMAT_XRGB1555:
1083 m = 0xf; break;
1084 default:
1085 BUG(); return;
1086 }
1087 } else {
1088 switch (fourcc) {
1089 case DRM_FORMAT_RGBX4444:
1090 m = 0x4; break;
1091 case DRM_FORMAT_ARGB4444:
1092 m = 0x5; break;
1093 case DRM_FORMAT_RGB565:
1094 m = 0x6; break;
1095 case DRM_FORMAT_ARGB1555:
1096 m = 0x7; break;
1097 case DRM_FORMAT_XRGB8888:
1098 m = 0x8; break;
1099 case DRM_FORMAT_RGB888:
1100 m = 0x9; break;
1101 case DRM_FORMAT_XRGB4444:
1102 m = 0xa; break;
1103 case DRM_FORMAT_RGBA4444:
1104 m = 0xb; break;
1105 case DRM_FORMAT_ARGB8888:
1106 m = 0xc; break;
1107 case DRM_FORMAT_RGBA8888:
1108 m = 0xd; break;
1109 case DRM_FORMAT_RGBX8888:
1110 m = 0xe; break;
1111 case DRM_FORMAT_XRGB1555:
1112 m = 0xf; break;
1113 default:
1114 BUG(); return;
1115 }
1116 }
1117
1118 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1119 }
1120
1121 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc,
1122 enum omap_plane_id plane,
1123 enum omap_dss_rotation_type rotation)
1124 {
1125 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0)
1126 return;
1127
1128 if (rotation == OMAP_DSS_ROT_TILER)
1129 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1130 else
1131 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1132 }
1133
1134 static void dispc_ovl_set_channel_out(struct dispc_device *dispc,
1135 enum omap_plane_id plane,
1136 enum omap_channel channel)
1137 {
1138 int shift;
1139 u32 val;
1140 int chan = 0, chan2 = 0;
1141
1142 switch (plane) {
1143 case OMAP_DSS_GFX:
1144 shift = 8;
1145 break;
1146 case OMAP_DSS_VIDEO1:
1147 case OMAP_DSS_VIDEO2:
1148 case OMAP_DSS_VIDEO3:
1149 shift = 16;
1150 break;
1151 default:
1152 BUG();
1153 return;
1154 }
1155
1156 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1157 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
1158 switch (channel) {
1159 case OMAP_DSS_CHANNEL_LCD:
1160 chan = 0;
1161 chan2 = 0;
1162 break;
1163 case OMAP_DSS_CHANNEL_DIGIT:
1164 chan = 1;
1165 chan2 = 0;
1166 break;
1167 case OMAP_DSS_CHANNEL_LCD2:
1168 chan = 0;
1169 chan2 = 1;
1170 break;
1171 case OMAP_DSS_CHANNEL_LCD3:
1172 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
1173 chan = 0;
1174 chan2 = 2;
1175 } else {
1176 BUG();
1177 return;
1178 }
1179 break;
1180 case OMAP_DSS_CHANNEL_WB:
1181 chan = 0;
1182 chan2 = 3;
1183 break;
1184 default:
1185 BUG();
1186 return;
1187 }
1188
1189 val = FLD_MOD(val, chan, shift, shift);
1190 val = FLD_MOD(val, chan2, 31, 30);
1191 } else {
1192 val = FLD_MOD(val, channel, shift, shift);
1193 }
1194 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1195 }
1196
1197 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc,
1198 enum omap_plane_id plane)
1199 {
1200 int shift;
1201 u32 val;
1202
1203 switch (plane) {
1204 case OMAP_DSS_GFX:
1205 shift = 8;
1206 break;
1207 case OMAP_DSS_VIDEO1:
1208 case OMAP_DSS_VIDEO2:
1209 case OMAP_DSS_VIDEO3:
1210 shift = 16;
1211 break;
1212 default:
1213 BUG();
1214 return 0;
1215 }
1216
1217 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1218
1219 if (FLD_GET(val, shift, shift) == 1)
1220 return OMAP_DSS_CHANNEL_DIGIT;
1221
1222 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2))
1223 return OMAP_DSS_CHANNEL_LCD;
1224
1225 switch (FLD_GET(val, 31, 30)) {
1226 case 0:
1227 default:
1228 return OMAP_DSS_CHANNEL_LCD;
1229 case 1:
1230 return OMAP_DSS_CHANNEL_LCD2;
1231 case 2:
1232 return OMAP_DSS_CHANNEL_LCD3;
1233 case 3:
1234 return OMAP_DSS_CHANNEL_WB;
1235 }
1236 }
1237
1238 static void dispc_ovl_set_burst_size(struct dispc_device *dispc,
1239 enum omap_plane_id plane,
1240 enum omap_burst_size burst_size)
1241 {
1242 static const unsigned int shifts[] = { 6, 14, 14, 14, 14, };
1243 int shift;
1244
1245 shift = shifts[plane];
1246 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,
1247 shift + 1, shift);
1248 }
1249
1250 static void dispc_configure_burst_sizes(struct dispc_device *dispc)
1251 {
1252 int i;
1253 const int burst_size = BURST_SIZE_X8;
1254
1255 /* Configure burst size always to maximum size */
1256 for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1257 dispc_ovl_set_burst_size(dispc, i, burst_size);
1258 if (dispc->feat->has_writeback)
1259 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size);
1260 }
1261
1262 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc,
1263 enum omap_plane_id plane)
1264 {
1265 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1266 return dispc->feat->burst_size_unit * 8;
1267 }
1268
1269 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
1270 enum omap_plane_id plane, u32 fourcc)
1271 {
1272 const u32 *modes;
1273 unsigned int i;
1274
1275 modes = dispc->feat->supported_color_modes[plane];
1276
1277 for (i = 0; modes[i]; ++i) {
1278 if (modes[i] == fourcc)
1279 return true;
1280 }
1281
1282 return false;
1283 }
1284
1285 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
1286 enum omap_plane_id plane)
1287 {
1288 return dispc->feat->supported_color_modes[plane];
1289 }
1290
1291 static void dispc_mgr_enable_cpr(struct dispc_device *dispc,
1292 enum omap_channel channel, bool enable)
1293 {
1294 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1295 return;
1296
1297 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1298 }
1299
1300 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc,
1301 enum omap_channel channel,
1302 const struct omap_dss_cpr_coefs *coefs)
1303 {
1304 u32 coef_r, coef_g, coef_b;
1305
1306 if (!dss_mgr_is_lcd(channel))
1307 return;
1308
1309 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1310 FLD_VAL(coefs->rb, 9, 0);
1311 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1312 FLD_VAL(coefs->gb, 9, 0);
1313 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1314 FLD_VAL(coefs->bb, 9, 0);
1315
1316 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r);
1317 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g);
1318 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b);
1319 }
1320
1321 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc,
1322 enum omap_plane_id plane, bool enable)
1323 {
1324 u32 val;
1325
1326 BUG_ON(plane == OMAP_DSS_GFX);
1327
1328 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1329 val = FLD_MOD(val, enable, 9, 9);
1330 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1331 }
1332
1333 static void dispc_ovl_enable_replication(struct dispc_device *dispc,
1334 enum omap_plane_id plane,
1335 enum omap_overlay_caps caps,
1336 bool enable)
1337 {
1338 static const unsigned int shifts[] = { 5, 10, 10, 10 };
1339 int shift;
1340
1341 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1342 return;
1343
1344 shift = shifts[plane];
1345 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1346 }
1347
1348 static void dispc_mgr_set_size(struct dispc_device *dispc,
1349 enum omap_channel channel, u16 width, u16 height)
1350 {
1351 u32 val;
1352
1353 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) |
1354 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0);
1355
1356 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);
1357 }
1358
1359 static void dispc_init_fifos(struct dispc_device *dispc)
1360 {
1361 u32 size;
1362 int fifo;
1363 u8 start, end;
1364 u32 unit;
1365 int i;
1366
1367 unit = dispc->feat->buffer_size_unit;
1368
1369 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end);
1370
1371 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1372 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo),
1373 start, end);
1374 size *= unit;
1375 dispc->fifo_size[fifo] = size;
1376
1377 /*
1378 * By default fifos are mapped directly to overlays, fifo 0 to
1379 * ovl 0, fifo 1 to ovl 1, etc.
1380 */
1381 dispc->fifo_assignment[fifo] = fifo;
1382 }
1383
1384 /*
1385 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1386 * causes problems with certain use cases, like using the tiler in 2D
1387 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1388 * giving GFX plane a larger fifo. WB but should work fine with a
1389 * smaller fifo.
1390 */
1391 if (dispc->feat->gfx_fifo_workaround) {
1392 u32 v;
1393
1394 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER);
1395
1396 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1397 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1398 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1399 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1400
1401 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v);
1402
1403 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1404 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1405 }
1406
1407 /*
1408 * Setup default fifo thresholds.
1409 */
1410 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1411 u32 low, high;
1412 const bool use_fifomerge = false;
1413 const bool manual_update = false;
1414
1415 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high,
1416 use_fifomerge, manual_update);
1417
1418 dispc_ovl_set_fifo_threshold(dispc, i, low, high);
1419 }
1420
1421 if (dispc->feat->has_writeback) {
1422 u32 low, high;
1423 const bool use_fifomerge = false;
1424 const bool manual_update = false;
1425
1426 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB,
1427 &low, &high, use_fifomerge,
1428 manual_update);
1429
1430 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high);
1431 }
1432 }
1433
1434 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc,
1435 enum omap_plane_id plane)
1436 {
1437 int fifo;
1438 u32 size = 0;
1439
1440 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1441 if (dispc->fifo_assignment[fifo] == plane)
1442 size += dispc->fifo_size[fifo];
1443 }
1444
1445 return size;
1446 }
1447
1448 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
1449 enum omap_plane_id plane,
1450 u32 low, u32 high)
1451 {
1452 u8 hi_start, hi_end, lo_start, lo_end;
1453 u32 unit;
1454
1455 unit = dispc->feat->buffer_size_unit;
1456
1457 WARN_ON(low % unit != 0);
1458 WARN_ON(high % unit != 0);
1459
1460 low /= unit;
1461 high /= unit;
1462
1463 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD,
1464 &hi_start, &hi_end);
1465 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD,
1466 &lo_start, &lo_end);
1467
1468 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1469 plane,
1470 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1471 lo_start, lo_end) * unit,
1472 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1473 hi_start, hi_end) * unit,
1474 low * unit, high * unit);
1475
1476 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1477 FLD_VAL(high, hi_start, hi_end) |
1478 FLD_VAL(low, lo_start, lo_end));
1479
1480 /*
1481 * configure the preload to the pipeline's high threhold, if HT it's too
1482 * large for the preload field, set the threshold to the maximum value
1483 * that can be held by the preload register
1484 */
1485 if (dispc_has_feature(dispc, FEAT_PRELOAD) &&
1486 dispc->feat->set_max_preload && plane != OMAP_DSS_WB)
1487 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),
1488 min(high, 0xfffu));
1489 }
1490
1491 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable)
1492 {
1493 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) {
1494 WARN_ON(enable);
1495 return;
1496 }
1497
1498 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1499 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1500 }
1501
1502 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
1503 enum omap_plane_id plane,
1504 u32 *fifo_low, u32 *fifo_high,
1505 bool use_fifomerge, bool manual_update)
1506 {
1507 /*
1508 * All sizes are in bytes. Both the buffer and burst are made of
1509 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1510 */
1511 unsigned int buf_unit = dispc->feat->buffer_size_unit;
1512 unsigned int ovl_fifo_size, total_fifo_size, burst_size;
1513 int i;
1514
1515 burst_size = dispc_ovl_get_burst_size(dispc, plane);
1516 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane);
1517
1518 if (use_fifomerge) {
1519 total_fifo_size = 0;
1520 for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1521 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i);
1522 } else {
1523 total_fifo_size = ovl_fifo_size;
1524 }
1525
1526 /*
1527 * We use the same low threshold for both fifomerge and non-fifomerge
1528 * cases, but for fifomerge we calculate the high threshold using the
1529 * combined fifo size
1530 */
1531
1532 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) {
1533 *fifo_low = ovl_fifo_size - burst_size * 2;
1534 *fifo_high = total_fifo_size - burst_size;
1535 } else if (plane == OMAP_DSS_WB) {
1536 /*
1537 * Most optimal configuration for writeback is to push out data
1538 * to the interconnect the moment writeback pushes enough pixels
1539 * in the FIFO to form a burst
1540 */
1541 *fifo_low = 0;
1542 *fifo_high = burst_size;
1543 } else {
1544 *fifo_low = ovl_fifo_size - burst_size;
1545 *fifo_high = total_fifo_size - buf_unit;
1546 }
1547 }
1548
1549 static void dispc_ovl_set_mflag(struct dispc_device *dispc,
1550 enum omap_plane_id plane, bool enable)
1551 {
1552 int bit;
1553
1554 if (plane == OMAP_DSS_GFX)
1555 bit = 14;
1556 else
1557 bit = 23;
1558
1559 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1560 }
1561
1562 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc,
1563 enum omap_plane_id plane,
1564 int low, int high)
1565 {
1566 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),
1567 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1568 }
1569
1570 static void dispc_init_mflag(struct dispc_device *dispc)
1571 {
1572 int i;
1573
1574 /*
1575 * HACK: NV12 color format and MFLAG seem to have problems working
1576 * together: using two displays, and having an NV12 overlay on one of
1577 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1578 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1579 * remove the errors, but there doesn't seem to be a clear logic on
1580 * which values work and which not.
1581 *
1582 * As a work-around, set force MFLAG to always on.
1583 */
1584 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1585 (1 << 0) | /* MFLAG_CTRL = force always on */
1586 (0 << 2)); /* MFLAG_START = disable */
1587
1588 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1589 u32 size = dispc_ovl_get_fifo_size(dispc, i);
1590 u32 unit = dispc->feat->buffer_size_unit;
1591 u32 low, high;
1592
1593 dispc_ovl_set_mflag(dispc, i, true);
1594
1595 /*
1596 * Simulation team suggests below thesholds:
1597 * HT = fifosize * 5 / 8;
1598 * LT = fifosize * 4 / 8;
1599 */
1600
1601 low = size * 4 / 8 / unit;
1602 high = size * 5 / 8 / unit;
1603
1604 dispc_ovl_set_mflag_threshold(dispc, i, low, high);
1605 }
1606
1607 if (dispc->feat->has_writeback) {
1608 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB);
1609 u32 unit = dispc->feat->buffer_size_unit;
1610 u32 low, high;
1611
1612 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true);
1613
1614 /*
1615 * Simulation team suggests below thesholds:
1616 * HT = fifosize * 5 / 8;
1617 * LT = fifosize * 4 / 8;
1618 */
1619
1620 low = size * 4 / 8 / unit;
1621 high = size * 5 / 8 / unit;
1622
1623 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high);
1624 }
1625 }
1626
1627 static void dispc_ovl_set_fir(struct dispc_device *dispc,
1628 enum omap_plane_id plane,
1629 int hinc, int vinc,
1630 enum omap_color_component color_comp)
1631 {
1632 u32 val;
1633
1634 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1635 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1636
1637 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC,
1638 &hinc_start, &hinc_end);
1639 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC,
1640 &vinc_start, &vinc_end);
1641 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1642 FLD_VAL(hinc, hinc_start, hinc_end);
1643
1644 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1645 } else {
1646 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1647 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1648 }
1649 }
1650
1651 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc,
1652 enum omap_plane_id plane, int haccu,
1653 int vaccu)
1654 {
1655 u32 val;
1656 u8 hor_start, hor_end, vert_start, vert_end;
1657
1658 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1659 &hor_start, &hor_end);
1660 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1661 &vert_start, &vert_end);
1662
1663 val = FLD_VAL(vaccu, vert_start, vert_end) |
1664 FLD_VAL(haccu, hor_start, hor_end);
1665
1666 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1667 }
1668
1669 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc,
1670 enum omap_plane_id plane, int haccu,
1671 int vaccu)
1672 {
1673 u32 val;
1674 u8 hor_start, hor_end, vert_start, vert_end;
1675
1676 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1677 &hor_start, &hor_end);
1678 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1679 &vert_start, &vert_end);
1680
1681 val = FLD_VAL(vaccu, vert_start, vert_end) |
1682 FLD_VAL(haccu, hor_start, hor_end);
1683
1684 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1685 }
1686
1687 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc,
1688 enum omap_plane_id plane, int haccu,
1689 int vaccu)
1690 {
1691 u32 val;
1692
1693 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1695 }
1696
1697 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc,
1698 enum omap_plane_id plane, int haccu,
1699 int vaccu)
1700 {
1701 u32 val;
1702
1703 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
1705 }
1706
1707 static void dispc_ovl_set_scale_param(struct dispc_device *dispc,
1708 enum omap_plane_id plane,
1709 u16 orig_width, u16 orig_height,
1710 u16 out_width, u16 out_height,
1711 bool five_taps, u8 rotation,
1712 enum omap_color_component color_comp)
1713 {
1714 int fir_hinc, fir_vinc;
1715
1716 fir_hinc = 1024 * orig_width / out_width;
1717 fir_vinc = 1024 * orig_height / out_height;
1718
1719 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps,
1720 color_comp);
1721 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp);
1722 }
1723
1724 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc,
1725 enum omap_plane_id plane,
1726 u16 orig_width, u16 orig_height,
1727 u16 out_width, u16 out_height,
1728 bool ilace, u32 fourcc, u8 rotation)
1729 {
1730 int h_accu2_0, h_accu2_1;
1731 int v_accu2_0, v_accu2_1;
1732 int chroma_hinc, chroma_vinc;
1733 int idx;
1734
1735 struct accu {
1736 s8 h0_m, h0_n;
1737 s8 h1_m, h1_n;
1738 s8 v0_m, v0_n;
1739 s8 v1_m, v1_n;
1740 };
1741
1742 const struct accu *accu_table;
1743 const struct accu *accu_val;
1744
1745 static const struct accu accu_nv12[4] = {
1746 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1747 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1748 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1749 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1750 };
1751
1752 static const struct accu accu_nv12_ilace[4] = {
1753 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1754 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1755 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1756 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1757 };
1758
1759 static const struct accu accu_yuv[4] = {
1760 { 0, 1, 0, 1, 0, 1, 0, 1 },
1761 { 0, 1, 0, 1, 0, 1, 0, 1 },
1762 { -1, 1, 0, 1, 0, 1, 0, 1 },
1763 { 0, 1, 0, 1, -1, 1, 0, 1 },
1764 };
1765
1766 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1767 switch (rotation & DRM_MODE_ROTATE_MASK) {
1768 default:
1769 case DRM_MODE_ROTATE_0:
1770 idx = 0;
1771 break;
1772 case DRM_MODE_ROTATE_90:
1773 idx = 3;
1774 break;
1775 case DRM_MODE_ROTATE_180:
1776 idx = 2;
1777 break;
1778 case DRM_MODE_ROTATE_270:
1779 idx = 1;
1780 break;
1781 }
1782
1783 switch (fourcc) {
1784 case DRM_FORMAT_NV12:
1785 if (ilace)
1786 accu_table = accu_nv12_ilace;
1787 else
1788 accu_table = accu_nv12;
1789 break;
1790 case DRM_FORMAT_YUYV:
1791 case DRM_FORMAT_UYVY:
1792 accu_table = accu_yuv;
1793 break;
1794 default:
1795 BUG();
1796 return;
1797 }
1798
1799 accu_val = &accu_table[idx];
1800
1801 chroma_hinc = 1024 * orig_width / out_width;
1802 chroma_vinc = 1024 * orig_height / out_height;
1803
1804 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1805 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1806 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1807 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1808
1809 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0);
1810 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1);
1811 }
1812
1813 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc,
1814 enum omap_plane_id plane,
1815 u16 orig_width, u16 orig_height,
1816 u16 out_width, u16 out_height,
1817 bool ilace, bool five_taps,
1818 bool fieldmode, u32 fourcc,
1819 u8 rotation)
1820 {
1821 int accu0 = 0;
1822 int accu1 = 0;
1823 u32 l;
1824
1825 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1826 out_width, out_height, five_taps,
1827 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1828 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1829
1830 /* RESIZEENABLE and VERTICALTAPS */
1831 l &= ~((0x3 << 5) | (0x1 << 21));
1832 l |= (orig_width != out_width) ? (1 << 5) : 0;
1833 l |= (orig_height != out_height) ? (1 << 6) : 0;
1834 l |= five_taps ? (1 << 21) : 0;
1835
1836 /* VRESIZECONF and HRESIZECONF */
1837 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) {
1838 l &= ~(0x3 << 7);
1839 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1840 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1841 }
1842
1843 /* LINEBUFFERSPLIT */
1844 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) {
1845 l &= ~(0x1 << 22);
1846 l |= five_taps ? (1 << 22) : 0;
1847 }
1848
1849 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
1850
1851 /*
1852 * field 0 = even field = bottom field
1853 * field 1 = odd field = top field
1854 */
1855 if (ilace && !fieldmode) {
1856 accu1 = 0;
1857 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1858 if (accu0 >= 1024/2) {
1859 accu1 = 1024/2;
1860 accu0 -= accu1;
1861 }
1862 }
1863
1864 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0);
1865 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1);
1866 }
1867
1868 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc,
1869 enum omap_plane_id plane,
1870 u16 orig_width, u16 orig_height,
1871 u16 out_width, u16 out_height,
1872 bool ilace, bool five_taps,
1873 bool fieldmode, u32 fourcc,
1874 u8 rotation)
1875 {
1876 int scale_x = out_width != orig_width;
1877 int scale_y = out_height != orig_height;
1878 bool chroma_upscale = plane != OMAP_DSS_WB;
1879 const struct drm_format_info *info;
1880
1881 info = drm_format_info(fourcc);
1882
1883 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE))
1884 return;
1885
1886 if (!info->is_yuv) {
1887 /* reset chroma resampling for RGB formats */
1888 if (plane != OMAP_DSS_WB)
1889 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1890 0, 8, 8);
1891 return;
1892 }
1893
1894 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width,
1895 out_height, ilace, fourcc, rotation);
1896
1897 switch (fourcc) {
1898 case DRM_FORMAT_NV12:
1899 if (chroma_upscale) {
1900 /* UV is subsampled by 2 horizontally and vertically */
1901 orig_height >>= 1;
1902 orig_width >>= 1;
1903 } else {
1904 /* UV is downsampled by 2 horizontally and vertically */
1905 orig_height <<= 1;
1906 orig_width <<= 1;
1907 }
1908
1909 break;
1910 case DRM_FORMAT_YUYV:
1911 case DRM_FORMAT_UYVY:
1912 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1913 if (!drm_rotation_90_or_270(rotation)) {
1914 if (chroma_upscale)
1915 /* UV is subsampled by 2 horizontally */
1916 orig_width >>= 1;
1917 else
1918 /* UV is downsampled by 2 horizontally */
1919 orig_width <<= 1;
1920 }
1921
1922 /* must use FIR for YUV422 if rotated */
1923 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0)
1924 scale_x = scale_y = true;
1925
1926 break;
1927 default:
1928 BUG();
1929 return;
1930 }
1931
1932 if (out_width != orig_width)
1933 scale_x = true;
1934 if (out_height != orig_height)
1935 scale_y = true;
1936
1937 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1938 out_width, out_height, five_taps,
1939 rotation, DISPC_COLOR_COMPONENT_UV);
1940
1941 if (plane != OMAP_DSS_WB)
1942 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1943 (scale_x || scale_y) ? 1 : 0, 8, 8);
1944
1945 /* set H scaling */
1946 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1947 /* set V scaling */
1948 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1949 }
1950
1951 static void dispc_ovl_set_scaling(struct dispc_device *dispc,
1952 enum omap_plane_id plane,
1953 u16 orig_width, u16 orig_height,
1954 u16 out_width, u16 out_height,
1955 bool ilace, bool five_taps,
1956 bool fieldmode, u32 fourcc,
1957 u8 rotation)
1958 {
1959 BUG_ON(plane == OMAP_DSS_GFX);
1960
1961 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height,
1962 out_width, out_height, ilace, five_taps,
1963 fieldmode, fourcc, rotation);
1964
1965 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height,
1966 out_width, out_height, ilace, five_taps,
1967 fieldmode, fourcc, rotation);
1968 }
1969
1970 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc,
1971 enum omap_plane_id plane, u8 rotation,
1972 enum omap_dss_rotation_type rotation_type,
1973 u32 fourcc)
1974 {
1975 bool row_repeat = false;
1976 int vidrot = 0;
1977
1978 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1979 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
1980
1981 if (rotation & DRM_MODE_REFLECT_X) {
1982 switch (rotation & DRM_MODE_ROTATE_MASK) {
1983 case DRM_MODE_ROTATE_0:
1984 vidrot = 2;
1985 break;
1986 case DRM_MODE_ROTATE_90:
1987 vidrot = 1;
1988 break;
1989 case DRM_MODE_ROTATE_180:
1990 vidrot = 0;
1991 break;
1992 case DRM_MODE_ROTATE_270:
1993 vidrot = 3;
1994 break;
1995 }
1996 } else {
1997 switch (rotation & DRM_MODE_ROTATE_MASK) {
1998 case DRM_MODE_ROTATE_0:
1999 vidrot = 0;
2000 break;
2001 case DRM_MODE_ROTATE_90:
2002 vidrot = 3;
2003 break;
2004 case DRM_MODE_ROTATE_180:
2005 vidrot = 2;
2006 break;
2007 case DRM_MODE_ROTATE_270:
2008 vidrot = 1;
2009 break;
2010 }
2011 }
2012
2013 if (drm_rotation_90_or_270(rotation))
2014 row_repeat = true;
2015 else
2016 row_repeat = false;
2017 }
2018
2019 /*
2020 * OMAP4/5 Errata i631:
2021 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
2022 * rows beyond the framebuffer, which may cause OCP error.
2023 */
2024 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER)
2025 vidrot = 1;
2026
2027 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
2028 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE))
2029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2030 row_repeat ? 1 : 0, 18, 18);
2031
2032 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) {
2033 bool doublestride =
2034 fourcc == DRM_FORMAT_NV12 &&
2035 rotation_type == OMAP_DSS_ROT_TILER &&
2036 !drm_rotation_90_or_270(rotation);
2037
2038 /* DOUBLESTRIDE */
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2040 doublestride, 22, 22);
2041 }
2042 }
2043
2044 static int color_mode_to_bpp(u32 fourcc)
2045 {
2046 switch (fourcc) {
2047 case DRM_FORMAT_NV12:
2048 return 8;
2049 case DRM_FORMAT_RGBX4444:
2050 case DRM_FORMAT_RGB565:
2051 case DRM_FORMAT_ARGB4444:
2052 case DRM_FORMAT_YUYV:
2053 case DRM_FORMAT_UYVY:
2054 case DRM_FORMAT_RGBA4444:
2055 case DRM_FORMAT_XRGB4444:
2056 case DRM_FORMAT_ARGB1555:
2057 case DRM_FORMAT_XRGB1555:
2058 return 16;
2059 case DRM_FORMAT_RGB888:
2060 return 24;
2061 case DRM_FORMAT_XRGB8888:
2062 case DRM_FORMAT_ARGB8888:
2063 case DRM_FORMAT_RGBA8888:
2064 case DRM_FORMAT_RGBX8888:
2065 return 32;
2066 default:
2067 BUG();
2068 return 0;
2069 }
2070 }
2071
2072 static s32 pixinc(int pixels, u8 ps)
2073 {
2074 if (pixels == 1)
2075 return 1;
2076 else if (pixels > 1)
2077 return 1 + (pixels - 1) * ps;
2078 else if (pixels < 0)
2079 return 1 - (-pixels + 1) * ps;
2080 else
2081 BUG();
2082 return 0;
2083 }
2084
2085 static void calc_offset(u16 screen_width, u16 width,
2086 u32 fourcc, bool fieldmode, unsigned int field_offset,
2087 unsigned int *offset0, unsigned int *offset1,
2088 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
2089 enum omap_dss_rotation_type rotation_type, u8 rotation)
2090 {
2091 u8 ps;
2092
2093 ps = color_mode_to_bpp(fourcc) / 8;
2094
2095 DSSDBG("scrw %d, width %d\n", screen_width, width);
2096
2097 if (rotation_type == OMAP_DSS_ROT_TILER &&
2098 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) &&
2099 drm_rotation_90_or_270(rotation)) {
2100 /*
2101 * HACK: ROW_INC needs to be calculated with TILER units.
2102 * We get such 'screen_width' that multiplying it with the
2103 * YUV422 pixel size gives the correct TILER container width.
2104 * However, 'width' is in pixels and multiplying it with YUV422
2105 * pixel size gives incorrect result. We thus multiply it here
2106 * with 2 to match the 32 bit TILER unit size.
2107 */
2108 width *= 2;
2109 }
2110
2111 /*
2112 * field 0 = even field = bottom field
2113 * field 1 = odd field = top field
2114 */
2115 *offset0 = field_offset * screen_width * ps;
2116 *offset1 = 0;
2117
2118 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2119 (fieldmode ? screen_width : 0), ps);
2120 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
2121 *pix_inc = pixinc(x_predecim, 2 * ps);
2122 else
2123 *pix_inc = pixinc(x_predecim, ps);
2124 }
2125
2126 /*
2127 * This function is used to avoid synclosts in OMAP3, because of some
2128 * undocumented horizontal position and timing related limitations.
2129 */
2130 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2131 const struct videomode *vm, u16 pos_x,
2132 u16 width, u16 height, u16 out_width, u16 out_height,
2133 bool five_taps)
2134 {
2135 const int ds = DIV_ROUND_UP(height, out_height);
2136 unsigned long nonactive;
2137 static const u8 limits[3] = { 8, 10, 20 };
2138 u64 val, blank;
2139 int i;
2140
2141 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2142 vm->hback_porch - out_width;
2143
2144 i = 0;
2145 if (out_height < height)
2146 i++;
2147 if (out_width < width)
2148 i++;
2149 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2150 lclk, pclk);
2151 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2152 if (blank <= limits[i])
2153 return -EINVAL;
2154
2155 /* FIXME add checks for 3-tap filter once the limitations are known */
2156 if (!five_taps)
2157 return 0;
2158
2159 /*
2160 * Pixel data should be prepared before visible display point starts.
2161 * So, atleast DS-2 lines must have already been fetched by DISPC
2162 * during nonactive - pos_x period.
2163 */
2164 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2165 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2166 val, max(0, ds - 2) * width);
2167 if (val < max(0, ds - 2) * width)
2168 return -EINVAL;
2169
2170 /*
2171 * All lines need to be refilled during the nonactive period of which
2172 * only one line can be loaded during the active period. So, atleast
2173 * DS - 1 lines should be loaded during nonactive period.
2174 */
2175 val = div_u64((u64)nonactive * lclk, pclk);
2176 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2177 val, max(0, ds - 1) * width);
2178 if (val < max(0, ds - 1) * width)
2179 return -EINVAL;
2180
2181 return 0;
2182 }
2183
2184 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2185 const struct videomode *vm, u16 width,
2186 u16 height, u16 out_width, u16 out_height,
2187 u32 fourcc)
2188 {
2189 u32 core_clk = 0;
2190 u64 tmp;
2191
2192 if (height <= out_height && width <= out_width)
2193 return (unsigned long) pclk;
2194
2195 if (height > out_height) {
2196 unsigned int ppl = vm->hactive;
2197
2198 tmp = (u64)pclk * height * out_width;
2199 do_div(tmp, 2 * out_height * ppl);
2200 core_clk = tmp;
2201
2202 if (height > 2 * out_height) {
2203 if (ppl == out_width)
2204 return 0;
2205
2206 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2207 do_div(tmp, 2 * out_height * (ppl - out_width));
2208 core_clk = max_t(u32, core_clk, tmp);
2209 }
2210 }
2211
2212 if (width > out_width) {
2213 tmp = (u64)pclk * width;
2214 do_div(tmp, out_width);
2215 core_clk = max_t(u32, core_clk, tmp);
2216
2217 if (fourcc == DRM_FORMAT_XRGB8888)
2218 core_clk <<= 1;
2219 }
2220
2221 return core_clk;
2222 }
2223
2224 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2225 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2226 {
2227 if (height > out_height && width > out_width)
2228 return pclk * 4;
2229 else
2230 return pclk * 2;
2231 }
2232
2233 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2234 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2235 {
2236 unsigned int hf, vf;
2237
2238 /*
2239 * FIXME how to determine the 'A' factor
2240 * for the no downscaling case ?
2241 */
2242
2243 if (width > 3 * out_width)
2244 hf = 4;
2245 else if (width > 2 * out_width)
2246 hf = 3;
2247 else if (width > out_width)
2248 hf = 2;
2249 else
2250 hf = 1;
2251 if (height > out_height)
2252 vf = 2;
2253 else
2254 vf = 1;
2255
2256 return pclk * vf * hf;
2257 }
2258
2259 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2260 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2261 {
2262 /*
2263 * If the overlay/writeback is in mem to mem mode, there are no
2264 * downscaling limitations with respect to pixel clock, return 1 as
2265 * required core clock to represent that we have sufficient enough
2266 * core clock to do maximum downscaling
2267 */
2268 if (mem_to_mem)
2269 return 1;
2270
2271 if (width > out_width)
2272 return DIV_ROUND_UP(pclk, out_width) * width;
2273 else
2274 return pclk;
2275 }
2276
2277 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc,
2278 unsigned long pclk, unsigned long lclk,
2279 const struct videomode *vm,
2280 u16 width, u16 height,
2281 u16 out_width, u16 out_height,
2282 u32 fourcc, bool *five_taps,
2283 int *x_predecim, int *y_predecim,
2284 int *decim_x, int *decim_y,
2285 u16 pos_x, unsigned long *core_clk,
2286 bool mem_to_mem)
2287 {
2288 int error;
2289 u16 in_width, in_height;
2290 int min_factor = min(*decim_x, *decim_y);
2291 const int maxsinglelinewidth = dispc->feat->max_line_width;
2292
2293 *five_taps = false;
2294
2295 do {
2296 in_height = height / *decim_y;
2297 in_width = width / *decim_x;
2298 *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2299 in_height, out_width, out_height, mem_to_mem);
2300 error = (in_width > maxsinglelinewidth || !*core_clk ||
2301 *core_clk > dispc_core_clk_rate(dispc));
2302 if (error) {
2303 if (*decim_x == *decim_y) {
2304 *decim_x = min_factor;
2305 ++*decim_y;
2306 } else {
2307 swap(*decim_x, *decim_y);
2308 if (*decim_x < *decim_y)
2309 ++*decim_x;
2310 }
2311 }
2312 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2313
2314 if (error) {
2315 DSSERR("failed to find scaling settings\n");
2316 return -EINVAL;
2317 }
2318
2319 if (in_width > maxsinglelinewidth) {
2320 DSSERR("Cannot scale max input width exceeded\n");
2321 return -EINVAL;
2322 }
2323 return 0;
2324 }
2325
2326 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc,
2327 unsigned long pclk, unsigned long lclk,
2328 const struct videomode *vm,
2329 u16 width, u16 height,
2330 u16 out_width, u16 out_height,
2331 u32 fourcc, bool *five_taps,
2332 int *x_predecim, int *y_predecim,
2333 int *decim_x, int *decim_y,
2334 u16 pos_x, unsigned long *core_clk,
2335 bool mem_to_mem)
2336 {
2337 int error;
2338 u16 in_width, in_height;
2339 const int maxsinglelinewidth = dispc->feat->max_line_width;
2340
2341 do {
2342 in_height = height / *decim_y;
2343 in_width = width / *decim_x;
2344 *five_taps = in_height > out_height;
2345
2346 if (in_width > maxsinglelinewidth)
2347 if (in_height > out_height &&
2348 in_height < out_height * 2)
2349 *five_taps = false;
2350 again:
2351 if (*five_taps)
2352 *core_clk = calc_core_clk_five_taps(pclk, vm,
2353 in_width, in_height, out_width,
2354 out_height, fourcc);
2355 else
2356 *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2357 in_height, out_width, out_height,
2358 mem_to_mem);
2359
2360 error = check_horiz_timing_omap3(pclk, lclk, vm,
2361 pos_x, in_width, in_height, out_width,
2362 out_height, *five_taps);
2363 if (error && *five_taps) {
2364 *five_taps = false;
2365 goto again;
2366 }
2367
2368 error = (error || in_width > maxsinglelinewidth * 2 ||
2369 (in_width > maxsinglelinewidth && *five_taps) ||
2370 !*core_clk || *core_clk > dispc_core_clk_rate(dispc));
2371
2372 if (!error) {
2373 /* verify that we're inside the limits of scaler */
2374 if (in_width / 4 > out_width)
2375 error = 1;
2376
2377 if (*five_taps) {
2378 if (in_height / 4 > out_height)
2379 error = 1;
2380 } else {
2381 if (in_height / 2 > out_height)
2382 error = 1;
2383 }
2384 }
2385
2386 if (error)
2387 ++*decim_y;
2388 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2389
2390 if (error) {
2391 DSSERR("failed to find scaling settings\n");
2392 return -EINVAL;
2393 }
2394
2395 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2396 in_height, out_width, out_height, *five_taps)) {
2397 DSSERR("horizontal timing too tight\n");
2398 return -EINVAL;
2399 }
2400
2401 if (in_width > (maxsinglelinewidth * 2)) {
2402 DSSERR("Cannot setup scaling\n");
2403 DSSERR("width exceeds maximum width possible\n");
2404 return -EINVAL;
2405 }
2406
2407 if (in_width > maxsinglelinewidth && *five_taps) {
2408 DSSERR("cannot setup scaling with five taps\n");
2409 return -EINVAL;
2410 }
2411 return 0;
2412 }
2413
2414 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc,
2415 unsigned long pclk, unsigned long lclk,
2416 const struct videomode *vm,
2417 u16 width, u16 height,
2418 u16 out_width, u16 out_height,
2419 u32 fourcc, bool *five_taps,
2420 int *x_predecim, int *y_predecim,
2421 int *decim_x, int *decim_y,
2422 u16 pos_x, unsigned long *core_clk,
2423 bool mem_to_mem)
2424 {
2425 u16 in_width, in_width_max;
2426 int decim_x_min = *decim_x;
2427 u16 in_height = height / *decim_y;
2428 const int maxsinglelinewidth = dispc->feat->max_line_width;
2429 const int maxdownscale = dispc->feat->max_downscale;
2430
2431 if (mem_to_mem) {
2432 in_width_max = out_width * maxdownscale;
2433 } else {
2434 in_width_max = dispc_core_clk_rate(dispc)
2435 / DIV_ROUND_UP(pclk, out_width);
2436 }
2437
2438 *decim_x = DIV_ROUND_UP(width, in_width_max);
2439
2440 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2441 if (*decim_x > *x_predecim)
2442 return -EINVAL;
2443
2444 do {
2445 in_width = width / *decim_x;
2446 } while (*decim_x <= *x_predecim &&
2447 in_width > maxsinglelinewidth && ++*decim_x);
2448
2449 if (in_width > maxsinglelinewidth) {
2450 DSSERR("Cannot scale width exceeds max line width\n");
2451 return -EINVAL;
2452 }
2453
2454 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) {
2455 /*
2456 * Let's disable all scaling that requires horizontal
2457 * decimation with higher factor than 4, until we have
2458 * better estimates of what we can and can not
2459 * do. However, NV12 color format appears to work Ok
2460 * with all decimation factors.
2461 *
2462 * When decimating horizontally by more that 4 the dss
2463 * is not able to fetch the data in burst mode. When
2464 * this happens it is hard to tell if there enough
2465 * bandwidth. Despite what theory says this appears to
2466 * be true also for 16-bit color formats.
2467 */
2468 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x);
2469
2470 return -EINVAL;
2471 }
2472
2473 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height,
2474 out_width, out_height, mem_to_mem);
2475 return 0;
2476 }
2477
2478 #define DIV_FRAC(dividend, divisor) \
2479 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2480
2481 static int dispc_ovl_calc_scaling(struct dispc_device *dispc,
2482 enum omap_plane_id plane,
2483 unsigned long pclk, unsigned long lclk,
2484 enum omap_overlay_caps caps,
2485 const struct videomode *vm,
2486 u16 width, u16 height,
2487 u16 out_width, u16 out_height,
2488 u32 fourcc, bool *five_taps,
2489 int *x_predecim, int *y_predecim, u16 pos_x,
2490 enum omap_dss_rotation_type rotation_type,
2491 bool mem_to_mem)
2492 {
2493 int maxhdownscale = dispc->feat->max_downscale;
2494 int maxvdownscale = dispc->feat->max_downscale;
2495 const int max_decim_limit = 16;
2496 unsigned long core_clk = 0;
2497 int decim_x, decim_y, ret;
2498
2499 if (width == out_width && height == out_height)
2500 return 0;
2501
2502 if (dispc->feat->supported_scaler_color_modes) {
2503 const u32 *modes = dispc->feat->supported_scaler_color_modes;
2504 unsigned int i;
2505
2506 for (i = 0; modes[i]; ++i) {
2507 if (modes[i] == fourcc)
2508 break;
2509 }
2510
2511 if (modes[i] == 0)
2512 return -EINVAL;
2513 }
2514
2515 if (plane == OMAP_DSS_WB) {
2516 switch (fourcc) {
2517 case DRM_FORMAT_NV12:
2518 maxhdownscale = maxvdownscale = 2;
2519 break;
2520 case DRM_FORMAT_YUYV:
2521 case DRM_FORMAT_UYVY:
2522 maxhdownscale = 2;
2523 maxvdownscale = 4;
2524 break;
2525 default:
2526 break;
2527 }
2528 }
2529 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2530 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2531 return -EINVAL;
2532 }
2533
2534 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2535 return -EINVAL;
2536
2537 if (mem_to_mem) {
2538 *x_predecim = *y_predecim = 1;
2539 } else {
2540 *x_predecim = max_decim_limit;
2541 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2542 dispc_has_feature(dispc, FEAT_BURST_2D)) ?
2543 2 : max_decim_limit;
2544 }
2545
2546 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale);
2547 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxvdownscale);
2548
2549 if (decim_x > *x_predecim || out_width > width * 8)
2550 return -EINVAL;
2551
2552 if (decim_y > *y_predecim || out_height > height * 8)
2553 return -EINVAL;
2554
2555 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height,
2556 out_width, out_height, fourcc,
2557 five_taps, x_predecim, y_predecim,
2558 &decim_x, &decim_y, pos_x, &core_clk,
2559 mem_to_mem);
2560 if (ret)
2561 return ret;
2562
2563 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2564 width, height,
2565 out_width, out_height,
2566 out_width / width, DIV_FRAC(out_width, width),
2567 out_height / height, DIV_FRAC(out_height, height),
2568
2569 decim_x, decim_y,
2570 width / decim_x, height / decim_y,
2571 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2572 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2573
2574 *five_taps ? 5 : 3,
2575 core_clk, dispc_core_clk_rate(dispc));
2576
2577 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) {
2578 DSSERR("failed to set up scaling, "
2579 "required core clk rate = %lu Hz, "
2580 "current core clk rate = %lu Hz\n",
2581 core_clk, dispc_core_clk_rate(dispc));
2582 return -EINVAL;
2583 }
2584
2585 *x_predecim = decim_x;
2586 *y_predecim = decim_y;
2587 return 0;
2588 }
2589
2590 static int dispc_ovl_setup_common(struct dispc_device *dispc,
2591 enum omap_plane_id plane,
2592 enum omap_overlay_caps caps,
2593 u32 paddr, u32 p_uv_addr,
2594 u16 screen_width, int pos_x, int pos_y,
2595 u16 width, u16 height,
2596 u16 out_width, u16 out_height,
2597 u32 fourcc, u8 rotation, u8 zorder,
2598 u8 pre_mult_alpha, u8 global_alpha,
2599 enum omap_dss_rotation_type rotation_type,
2600 bool replication, const struct videomode *vm,
2601 bool mem_to_mem)
2602 {
2603 bool five_taps = true;
2604 bool fieldmode = false;
2605 int r, cconv = 0;
2606 unsigned int offset0, offset1;
2607 s32 row_inc;
2608 s32 pix_inc;
2609 u16 frame_width;
2610 unsigned int field_offset = 0;
2611 u16 in_height = height;
2612 u16 in_width = width;
2613 int x_predecim = 1, y_predecim = 1;
2614 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2615 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
2616 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
2617 const struct drm_format_info *info;
2618
2619 info = drm_format_info(fourcc);
2620
2621 /* when setting up WB, dispc_plane_pclk_rate() returns 0 */
2622 if (plane == OMAP_DSS_WB)
2623 pclk = vm->pixelclock;
2624
2625 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2626 return -EINVAL;
2627
2628 if (info->is_yuv && (in_width & 1)) {
2629 DSSERR("input width %d is not even for YUV format\n", in_width);
2630 return -EINVAL;
2631 }
2632
2633 out_width = out_width == 0 ? width : out_width;
2634 out_height = out_height == 0 ? height : out_height;
2635
2636 if (plane != OMAP_DSS_WB) {
2637 if (ilace && height == out_height)
2638 fieldmode = true;
2639
2640 if (ilace) {
2641 if (fieldmode)
2642 in_height /= 2;
2643 pos_y /= 2;
2644 out_height /= 2;
2645
2646 DSSDBG("adjusting for ilace: height %d, pos_y %d, out_height %d\n",
2647 in_height, pos_y, out_height);
2648 }
2649 }
2650
2651 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc))
2652 return -EINVAL;
2653
2654 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width,
2655 in_height, out_width, out_height, fourcc,
2656 &five_taps, &x_predecim, &y_predecim, pos_x,
2657 rotation_type, mem_to_mem);
2658 if (r)
2659 return r;
2660
2661 in_width = in_width / x_predecim;
2662 in_height = in_height / y_predecim;
2663
2664 if (x_predecim > 1 || y_predecim > 1)
2665 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2666 x_predecim, y_predecim, in_width, in_height);
2667
2668 if (info->is_yuv && (in_width & 1)) {
2669 DSSDBG("predecimated input width is not even for YUV format\n");
2670 DSSDBG("adjusting input width %d -> %d\n",
2671 in_width, in_width & ~1);
2672
2673 in_width &= ~1;
2674 }
2675
2676 if (info->is_yuv)
2677 cconv = 1;
2678
2679 if (ilace && !fieldmode) {
2680 /*
2681 * when downscaling the bottom field may have to start several
2682 * source lines below the top field. Unfortunately ACCUI
2683 * registers will only hold the fractional part of the offset
2684 * so the integer part must be added to the base address of the
2685 * bottom field.
2686 */
2687 if (!in_height || in_height == out_height)
2688 field_offset = 0;
2689 else
2690 field_offset = in_height / out_height / 2;
2691 }
2692
2693 /* Fields are independent but interleaved in memory. */
2694 if (fieldmode)
2695 field_offset = 1;
2696
2697 offset0 = 0;
2698 offset1 = 0;
2699 row_inc = 0;
2700 pix_inc = 0;
2701
2702 if (plane == OMAP_DSS_WB)
2703 frame_width = out_width;
2704 else
2705 frame_width = in_width;
2706
2707 calc_offset(screen_width, frame_width,
2708 fourcc, fieldmode, field_offset,
2709 &offset0, &offset1, &row_inc, &pix_inc,
2710 x_predecim, y_predecim,
2711 rotation_type, rotation);
2712
2713 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2714 offset0, offset1, row_inc, pix_inc);
2715
2716 dispc_ovl_set_color_mode(dispc, plane, fourcc);
2717
2718 dispc_ovl_configure_burst_type(dispc, plane, rotation_type);
2719
2720 if (dispc->feat->reverse_ilace_field_order)
2721 swap(offset0, offset1);
2722
2723 dispc_ovl_set_ba0(dispc, plane, paddr + offset0);
2724 dispc_ovl_set_ba1(dispc, plane, paddr + offset1);
2725
2726 if (fourcc == DRM_FORMAT_NV12) {
2727 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0);
2728 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1);
2729 }
2730
2731 if (dispc->feat->last_pixel_inc_missing)
2732 row_inc += pix_inc - 1;
2733
2734 dispc_ovl_set_row_inc(dispc, plane, row_inc);
2735 dispc_ovl_set_pix_inc(dispc, plane, pix_inc);
2736
2737 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2738 in_height, out_width, out_height);
2739
2740 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y);
2741
2742 dispc_ovl_set_input_size(dispc, plane, in_width, in_height);
2743
2744 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2745 dispc_ovl_set_scaling(dispc, plane, in_width, in_height,
2746 out_width, out_height, ilace, five_taps,
2747 fieldmode, fourcc, rotation);
2748 dispc_ovl_set_output_size(dispc, plane, out_width, out_height);
2749 dispc_ovl_set_vid_color_conv(dispc, plane, cconv);
2750 }
2751
2752 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type,
2753 fourcc);
2754
2755 dispc_ovl_set_zorder(dispc, plane, caps, zorder);
2756 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha);
2757 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha);
2758
2759 dispc_ovl_enable_replication(dispc, plane, caps, replication);
2760
2761 return 0;
2762 }
2763
2764 static int dispc_ovl_setup(struct dispc_device *dispc,
2765 enum omap_plane_id plane,
2766 const struct omap_overlay_info *oi,
2767 const struct videomode *vm, bool mem_to_mem,
2768 enum omap_channel channel)
2769 {
2770 int r;
2771 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane];
2772 const bool replication = true;
2773
2774 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2775 " %dx%d, cmode %x, rot %d, chan %d repl %d\n",
2776 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2777 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2778 oi->fourcc, oi->rotation, channel, replication);
2779
2780 dispc_ovl_set_channel_out(dispc, plane, channel);
2781
2782 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr,
2783 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2784 oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
2785 oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2786 oi->rotation_type, replication, vm, mem_to_mem);
2787
2788 return r;
2789 }
2790
2791 static int dispc_wb_setup(struct dispc_device *dispc,
2792 const struct omap_dss_writeback_info *wi,
2793 bool mem_to_mem, const struct videomode *vm,
2794 enum dss_writeback_channel channel_in)
2795 {
2796 int r;
2797 u32 l;
2798 enum omap_plane_id plane = OMAP_DSS_WB;
2799 const int pos_x = 0, pos_y = 0;
2800 const u8 zorder = 0, global_alpha = 0;
2801 const bool replication = true;
2802 bool truncation;
2803 int in_width = vm->hactive;
2804 int in_height = vm->vactive;
2805 enum omap_overlay_caps caps =
2806 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2807
2808 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2809 in_height /= 2;
2810
2811 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2812 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
2813 in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
2814
2815 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr,
2816 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2817 wi->height, wi->fourcc, wi->rotation, zorder,
2818 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2819 replication, vm, mem_to_mem);
2820 if (r)
2821 return r;
2822
2823 switch (wi->fourcc) {
2824 case DRM_FORMAT_RGB565:
2825 case DRM_FORMAT_RGB888:
2826 case DRM_FORMAT_ARGB4444:
2827 case DRM_FORMAT_RGBA4444:
2828 case DRM_FORMAT_RGBX4444:
2829 case DRM_FORMAT_ARGB1555:
2830 case DRM_FORMAT_XRGB1555:
2831 case DRM_FORMAT_XRGB4444:
2832 truncation = true;
2833 break;
2834 default:
2835 truncation = false;
2836 break;
2837 }
2838
2839 /* setup extra DISPC_WB_ATTRIBUTES */
2840 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
2841 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2842 l = FLD_MOD(l, channel_in, 18, 16); /* CHANNELIN */
2843 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2844 if (mem_to_mem)
2845 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2846 else
2847 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2848 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
2849
2850 if (mem_to_mem) {
2851 /* WBDELAYCOUNT */
2852 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2853 } else {
2854 u32 wbdelay;
2855
2856 if (channel_in == DSS_WB_TV_MGR)
2857 wbdelay = vm->vsync_len + vm->vback_porch;
2858 else
2859 wbdelay = vm->vfront_porch + vm->vsync_len +
2860 vm->vback_porch;
2861
2862 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2863 wbdelay /= 2;
2864
2865 wbdelay = min(wbdelay, 255u);
2866
2867 /* WBDELAYCOUNT */
2868 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2869 }
2870
2871 return 0;
2872 }
2873
2874 static bool dispc_has_writeback(struct dispc_device *dispc)
2875 {
2876 return dispc->feat->has_writeback;
2877 }
2878
2879 static int dispc_ovl_enable(struct dispc_device *dispc,
2880 enum omap_plane_id plane, bool enable)
2881 {
2882 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2883
2884 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2885
2886 return 0;
2887 }
2888
2889 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc,
2890 bool act_high)
2891 {
2892 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL))
2893 return;
2894
2895 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2896 }
2897
2898 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable)
2899 {
2900 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL))
2901 return;
2902
2903 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2904 }
2905
2906 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable)
2907 {
2908 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE))
2909 return;
2910
2911 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2912 }
2913
2914 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc,
2915 enum omap_channel channel,
2916 bool enable)
2917 {
2918 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2919 }
2920
2921
2922 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc,
2923 enum omap_channel channel)
2924 {
2925 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1);
2926 }
2927
2928 static void dispc_set_loadmode(struct dispc_device *dispc,
2929 enum omap_dss_load_mode mode)
2930 {
2931 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1);
2932 }
2933
2934
2935 static void dispc_mgr_set_default_color(struct dispc_device *dispc,
2936 enum omap_channel channel, u32 color)
2937 {
2938 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color);
2939 }
2940
2941 static void dispc_mgr_set_trans_key(struct dispc_device *dispc,
2942 enum omap_channel ch,
2943 enum omap_dss_trans_key_type type,
2944 u32 trans_key)
2945 {
2946 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type);
2947
2948 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key);
2949 }
2950
2951 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc,
2952 enum omap_channel ch, bool enable)
2953 {
2954 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable);
2955 }
2956
2957 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc,
2958 enum omap_channel ch,
2959 bool enable)
2960 {
2961 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER))
2962 return;
2963
2964 if (ch == OMAP_DSS_CHANNEL_LCD)
2965 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);
2966 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2967 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);
2968 }
2969
2970 static void dispc_mgr_setup(struct dispc_device *dispc,
2971 enum omap_channel channel,
2972 const struct omap_overlay_manager_info *info)
2973 {
2974 dispc_mgr_set_default_color(dispc, channel, info->default_color);
2975 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type,
2976 info->trans_key);
2977 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled);
2978 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel,
2979 info->partial_alpha_enabled);
2980 if (dispc_has_feature(dispc, FEAT_CPR)) {
2981 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable);
2982 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs);
2983 }
2984 }
2985
2986 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc,
2987 enum omap_channel channel,
2988 u8 data_lines)
2989 {
2990 int code;
2991
2992 switch (data_lines) {
2993 case 12:
2994 code = 0;
2995 break;
2996 case 16:
2997 code = 1;
2998 break;
2999 case 18:
3000 code = 2;
3001 break;
3002 case 24:
3003 code = 3;
3004 break;
3005 default:
3006 BUG();
3007 return;
3008 }
3009
3010 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code);
3011 }
3012
3013 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc,
3014 enum dss_io_pad_mode mode)
3015 {
3016 u32 l;
3017 int gpout0, gpout1;
3018
3019 switch (mode) {
3020 case DSS_IO_PAD_MODE_RESET:
3021 gpout0 = 0;
3022 gpout1 = 0;
3023 break;
3024 case DSS_IO_PAD_MODE_RFBI:
3025 gpout0 = 1;
3026 gpout1 = 0;
3027 break;
3028 case DSS_IO_PAD_MODE_BYPASS:
3029 gpout0 = 1;
3030 gpout1 = 1;
3031 break;
3032 default:
3033 BUG();
3034 return;
3035 }
3036
3037 l = dispc_read_reg(dispc, DISPC_CONTROL);
3038 l = FLD_MOD(l, gpout0, 15, 15);
3039 l = FLD_MOD(l, gpout1, 16, 16);
3040 dispc_write_reg(dispc, DISPC_CONTROL, l);
3041 }
3042
3043 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc,
3044 enum omap_channel channel, bool enable)
3045 {
3046 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
3047 }
3048
3049 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
3050 enum omap_channel channel,
3051 const struct dss_lcd_mgr_config *config)
3052 {
3053 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode);
3054
3055 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode);
3056 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck);
3057
3058 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info);
3059
3060 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width);
3061
3062 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity);
3063
3064 dispc_mgr_set_lcd_type_tft(dispc, channel);
3065 }
3066
3067 static bool _dispc_mgr_size_ok(struct dispc_device *dispc,
3068 u16 width, u16 height)
3069 {
3070 return width <= dispc->feat->mgr_width_max &&
3071 height <= dispc->feat->mgr_height_max;
3072 }
3073
3074 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc,
3075 int hsync_len, int hfp, int hbp,
3076 int vsw, int vfp, int vbp)
3077 {
3078 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max ||
3079 hfp < 1 || hfp > dispc->feat->hp_max ||
3080 hbp < 1 || hbp > dispc->feat->hp_max ||
3081 vsw < 1 || vsw > dispc->feat->sw_max ||
3082 vfp < 0 || vfp > dispc->feat->vp_max ||
3083 vbp < 0 || vbp > dispc->feat->vp_max)
3084 return false;
3085 return true;
3086 }
3087
3088 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc,
3089 enum omap_channel channel,
3090 unsigned long pclk)
3091 {
3092 if (dss_mgr_is_lcd(channel))
3093 return pclk <= dispc->feat->max_lcd_pclk;
3094 else
3095 return pclk <= dispc->feat->max_tv_pclk;
3096 }
3097
3098 static int dispc_mgr_check_timings(struct dispc_device *dispc,
3099 enum omap_channel channel,
3100 const struct videomode *vm)
3101 {
3102 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive))
3103 return MODE_BAD;
3104
3105 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock))
3106 return MODE_BAD;
3107
3108 if (dss_mgr_is_lcd(channel)) {
3109 /* TODO: OMAP4+ supports interlace for LCD outputs */
3110 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
3111 return MODE_BAD;
3112
3113 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len,
3114 vm->hfront_porch, vm->hback_porch,
3115 vm->vsync_len, vm->vfront_porch,
3116 vm->vback_porch))
3117 return MODE_BAD;
3118 }
3119
3120 return MODE_OK;
3121 }
3122
3123 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc,
3124 enum omap_channel channel,
3125 const struct videomode *vm)
3126 {
3127 u32 timing_h, timing_v, l;
3128 bool onoff, rf, ipc, vs, hs, de;
3129
3130 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) |
3131 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) |
3132 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20);
3133 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) |
3134 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) |
3135 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20);
3136
3137 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h);
3138 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v);
3139
3140 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
3141 vs = false;
3142 else
3143 vs = true;
3144
3145 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
3146 hs = false;
3147 else
3148 hs = true;
3149
3150 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
3151 de = false;
3152 else
3153 de = true;
3154
3155 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
3156 ipc = false;
3157 else
3158 ipc = true;
3159
3160 /* always use the 'rf' setting */
3161 onoff = true;
3162
3163 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
3164 rf = true;
3165 else
3166 rf = false;
3167
3168 l = FLD_VAL(onoff, 17, 17) |
3169 FLD_VAL(rf, 16, 16) |
3170 FLD_VAL(de, 15, 15) |
3171 FLD_VAL(ipc, 14, 14) |
3172 FLD_VAL(hs, 13, 13) |
3173 FLD_VAL(vs, 12, 12);
3174
3175 /* always set ALIGN bit when available */
3176 if (dispc->feat->supports_sync_align)
3177 l |= (1 << 18);
3178
3179 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l);
3180
3181 if (dispc->syscon_pol) {
3182 const int shifts[] = {
3183 [OMAP_DSS_CHANNEL_LCD] = 0,
3184 [OMAP_DSS_CHANNEL_LCD2] = 1,
3185 [OMAP_DSS_CHANNEL_LCD3] = 2,
3186 };
3187
3188 u32 mask, val;
3189
3190 mask = (1 << 0) | (1 << 3) | (1 << 6);
3191 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3192
3193 mask <<= 16 + shifts[channel];
3194 val <<= 16 + shifts[channel];
3195
3196 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset,
3197 mask, val);
3198 }
3199 }
3200
3201 static int vm_flag_to_int(enum display_flags flags, enum display_flags high,
3202 enum display_flags low)
3203 {
3204 if (flags & high)
3205 return 1;
3206 if (flags & low)
3207 return -1;
3208 return 0;
3209 }
3210
3211 /* change name to mode? */
3212 static void dispc_mgr_set_timings(struct dispc_device *dispc,
3213 enum omap_channel channel,
3214 const struct videomode *vm)
3215 {
3216 unsigned int xtot, ytot;
3217 unsigned long ht, vt;
3218 struct videomode t = *vm;
3219
3220 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3221
3222 if (dispc_mgr_check_timings(dispc, channel, &t)) {
3223 BUG();
3224 return;
3225 }
3226
3227 if (dss_mgr_is_lcd(channel)) {
3228 _dispc_mgr_set_lcd_timings(dispc, channel, &t);
3229
3230 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3231 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3232
3233 ht = vm->pixelclock / xtot;
3234 vt = vm->pixelclock / xtot / ytot;
3235
3236 DSSDBG("pck %lu\n", vm->pixelclock);
3237 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3238 t.hsync_len, t.hfront_porch, t.hback_porch,
3239 t.vsync_len, t.vfront_porch, t.vback_porch);
3240 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3241 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW),
3242 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW),
3243 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE),
3244 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW),
3245 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE));
3246
3247 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3248 } else {
3249 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3250 t.vactive /= 2;
3251
3252 if (dispc->feat->supports_double_pixel)
3253 REG_FLD_MOD(dispc, DISPC_CONTROL,
3254 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3255 19, 17);
3256 }
3257
3258 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive);
3259 }
3260
3261 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc,
3262 enum omap_channel channel, u16 lck_div,
3263 u16 pck_div)
3264 {
3265 BUG_ON(lck_div < 1);
3266 BUG_ON(pck_div < 1);
3267
3268 dispc_write_reg(dispc, DISPC_DIVISORo(channel),
3269 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3270
3271 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) &&
3272 channel == OMAP_DSS_CHANNEL_LCD)
3273 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div;
3274 }
3275
3276 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc,
3277 enum omap_channel channel, int *lck_div,
3278 int *pck_div)
3279 {
3280 u32 l;
3281 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3282 *lck_div = FLD_GET(l, 23, 16);
3283 *pck_div = FLD_GET(l, 7, 0);
3284 }
3285
3286 static unsigned long dispc_fclk_rate(struct dispc_device *dispc)
3287 {
3288 unsigned long r;
3289 enum dss_clk_source src;
3290
3291 src = dss_get_dispc_clk_source(dispc->dss);
3292
3293 if (src == DSS_CLK_SRC_FCK) {
3294 r = dss_get_dispc_clk_rate(dispc->dss);
3295 } else {
3296 struct dss_pll *pll;
3297 unsigned int clkout_idx;
3298
3299 pll = dss_pll_find_by_src(dispc->dss, src);
3300 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3301
3302 r = pll->cinfo.clkout[clkout_idx];
3303 }
3304
3305 return r;
3306 }
3307
3308 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
3309 enum omap_channel channel)
3310 {
3311 int lcd;
3312 unsigned long r;
3313 enum dss_clk_source src;
3314
3315 /* for TV, LCLK rate is the FCLK rate */
3316 if (!dss_mgr_is_lcd(channel))
3317 return dispc_fclk_rate(dispc);
3318
3319 src = dss_get_lcd_clk_source(dispc->dss, channel);
3320
3321 if (src == DSS_CLK_SRC_FCK) {
3322 r = dss_get_dispc_clk_rate(dispc->dss);
3323 } else {
3324 struct dss_pll *pll;
3325 unsigned int clkout_idx;
3326
3327 pll = dss_pll_find_by_src(dispc->dss, src);
3328 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3329
3330 r = pll->cinfo.clkout[clkout_idx];
3331 }
3332
3333 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3334
3335 return r / lcd;
3336 }
3337
3338 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
3339 enum omap_channel channel)
3340 {
3341 unsigned long r;
3342
3343 if (dss_mgr_is_lcd(channel)) {
3344 int pcd;
3345 u32 l;
3346
3347 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3348
3349 pcd = FLD_GET(l, 7, 0);
3350
3351 r = dispc_mgr_lclk_rate(dispc, channel);
3352
3353 return r / pcd;
3354 } else {
3355 return dispc->tv_pclk_rate;
3356 }
3357 }
3358
3359 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk)
3360 {
3361 dispc->tv_pclk_rate = pclk;
3362 }
3363
3364 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc)
3365 {
3366 return dispc->core_clk_rate;
3367 }
3368
3369 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
3370 enum omap_plane_id plane)
3371 {
3372 enum omap_channel channel;
3373
3374 if (plane == OMAP_DSS_WB)
3375 return 0;
3376
3377 channel = dispc_ovl_get_channel_out(dispc, plane);
3378
3379 return dispc_mgr_pclk_rate(dispc, channel);
3380 }
3381
3382 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
3383 enum omap_plane_id plane)
3384 {
3385 enum omap_channel channel;
3386
3387 if (plane == OMAP_DSS_WB)
3388 return 0;
3389
3390 channel = dispc_ovl_get_channel_out(dispc, plane);
3391
3392 return dispc_mgr_lclk_rate(dispc, channel);
3393 }
3394
3395 static void dispc_dump_clocks_channel(struct dispc_device *dispc,
3396 struct seq_file *s,
3397 enum omap_channel channel)
3398 {
3399 int lcd, pcd;
3400 enum dss_clk_source lcd_clk_src;
3401
3402 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3403
3404 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel);
3405
3406 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3407 dss_get_clk_source_name(lcd_clk_src));
3408
3409 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd);
3410
3411 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3412 dispc_mgr_lclk_rate(dispc, channel), lcd);
3413 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3414 dispc_mgr_pclk_rate(dispc, channel), pcd);
3415 }
3416
3417 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s)
3418 {
3419 enum dss_clk_source dispc_clk_src;
3420 int lcd;
3421 u32 l;
3422
3423 if (dispc_runtime_get(dispc))
3424 return;
3425
3426 seq_printf(s, "- DISPC -\n");
3427
3428 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss);
3429 seq_printf(s, "dispc fclk source = %s\n",
3430 dss_get_clk_source_name(dispc_clk_src));
3431
3432 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc));
3433
3434 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3435 seq_printf(s, "- DISPC-CORE-CLK -\n");
3436 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3437 lcd = FLD_GET(l, 23, 16);
3438
3439 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3440 (dispc_fclk_rate(dispc)/lcd), lcd);
3441 }
3442
3443 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD);
3444
3445 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3446 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2);
3447 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3448 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3);
3449
3450 dispc_runtime_put(dispc);
3451 }
3452
3453 static int dispc_dump_regs(struct seq_file *s, void *p)
3454 {
3455 struct dispc_device *dispc = s->private;
3456 int i, j;
3457 const char *mgr_names[] = {
3458 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3459 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3460 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3461 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3462 };
3463 const char *ovl_names[] = {
3464 [OMAP_DSS_GFX] = "GFX",
3465 [OMAP_DSS_VIDEO1] = "VID1",
3466 [OMAP_DSS_VIDEO2] = "VID2",
3467 [OMAP_DSS_VIDEO3] = "VID3",
3468 [OMAP_DSS_WB] = "WB",
3469 };
3470 const char **p_names;
3471
3472 #define DUMPREG(dispc, r) \
3473 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r))
3474
3475 if (dispc_runtime_get(dispc))
3476 return 0;
3477
3478 /* DISPC common registers */
3479 DUMPREG(dispc, DISPC_REVISION);
3480 DUMPREG(dispc, DISPC_SYSCONFIG);
3481 DUMPREG(dispc, DISPC_SYSSTATUS);
3482 DUMPREG(dispc, DISPC_IRQSTATUS);
3483 DUMPREG(dispc, DISPC_IRQENABLE);
3484 DUMPREG(dispc, DISPC_CONTROL);
3485 DUMPREG(dispc, DISPC_CONFIG);
3486 DUMPREG(dispc, DISPC_CAPABLE);
3487 DUMPREG(dispc, DISPC_LINE_STATUS);
3488 DUMPREG(dispc, DISPC_LINE_NUMBER);
3489 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
3490 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
3491 DUMPREG(dispc, DISPC_GLOBAL_ALPHA);
3492 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
3493 DUMPREG(dispc, DISPC_CONTROL2);
3494 DUMPREG(dispc, DISPC_CONFIG2);
3495 }
3496 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
3497 DUMPREG(dispc, DISPC_CONTROL3);
3498 DUMPREG(dispc, DISPC_CONFIG3);
3499 }
3500 if (dispc_has_feature(dispc, FEAT_MFLAG))
3501 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3502
3503 #undef DUMPREG
3504
3505 #define DISPC_REG(i, name) name(i)
3506 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3507 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3508 dispc_read_reg(dispc, DISPC_REG(i, r)))
3509
3510 p_names = mgr_names;
3511
3512 /* DISPC channel specific registers */
3513 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
3514 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR);
3515 DUMPREG(dispc, i, DISPC_TRANS_COLOR);
3516 DUMPREG(dispc, i, DISPC_SIZE_MGR);
3517
3518 if (i == OMAP_DSS_CHANNEL_DIGIT)
3519 continue;
3520
3521 DUMPREG(dispc, i, DISPC_TIMING_H);
3522 DUMPREG(dispc, i, DISPC_TIMING_V);
3523 DUMPREG(dispc, i, DISPC_POL_FREQ);
3524 DUMPREG(dispc, i, DISPC_DIVISORo);
3525
3526 DUMPREG(dispc, i, DISPC_DATA_CYCLE1);
3527 DUMPREG(dispc, i, DISPC_DATA_CYCLE2);
3528 DUMPREG(dispc, i, DISPC_DATA_CYCLE3);
3529
3530 if (dispc_has_feature(dispc, FEAT_CPR)) {
3531 DUMPREG(dispc, i, DISPC_CPR_COEF_R);
3532 DUMPREG(dispc, i, DISPC_CPR_COEF_G);
3533 DUMPREG(dispc, i, DISPC_CPR_COEF_B);
3534 }
3535 }
3536
3537 p_names = ovl_names;
3538
3539 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
3540 DUMPREG(dispc, i, DISPC_OVL_BA0);
3541 DUMPREG(dispc, i, DISPC_OVL_BA1);
3542 DUMPREG(dispc, i, DISPC_OVL_POSITION);
3543 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3544 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3545 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3546 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3547 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3548 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3549
3550 if (dispc_has_feature(dispc, FEAT_PRELOAD))
3551 DUMPREG(dispc, i, DISPC_OVL_PRELOAD);
3552 if (dispc_has_feature(dispc, FEAT_MFLAG))
3553 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3554
3555 if (i == OMAP_DSS_GFX) {
3556 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP);
3557 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA);
3558 continue;
3559 }
3560
3561 DUMPREG(dispc, i, DISPC_OVL_FIR);
3562 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3563 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3564 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3565 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3566 DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3567 DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3568 DUMPREG(dispc, i, DISPC_OVL_FIR2);
3569 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3570 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3571 }
3572 if (dispc_has_feature(dispc, FEAT_ATTR2))
3573 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3574 }
3575
3576 if (dispc->feat->has_writeback) {
3577 i = OMAP_DSS_WB;
3578 DUMPREG(dispc, i, DISPC_OVL_BA0);
3579 DUMPREG(dispc, i, DISPC_OVL_BA1);
3580 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3581 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3582 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3583 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3584 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3585 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3586
3587 if (dispc_has_feature(dispc, FEAT_MFLAG))
3588 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3589
3590 DUMPREG(dispc, i, DISPC_OVL_FIR);
3591 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3592 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3593 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3594 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3595 DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3596 DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3597 DUMPREG(dispc, i, DISPC_OVL_FIR2);
3598 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3599 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3600 }
3601 if (dispc_has_feature(dispc, FEAT_ATTR2))
3602 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3603 }
3604
3605 #undef DISPC_REG
3606 #undef DUMPREG
3607
3608 #define DISPC_REG(plane, name, i) name(plane, i)
3609 #define DUMPREG(dispc, plane, name, i) \
3610 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3611 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3612 dispc_read_reg(dispc, DISPC_REG(plane, name, i)))
3613
3614 /* Video pipeline coefficient registers */
3615
3616 /* start from OMAP_DSS_VIDEO1 */
3617 for (i = 1; i < dispc_get_num_ovls(dispc); i++) {
3618 for (j = 0; j < 8; j++)
3619 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j);
3620
3621 for (j = 0; j < 8; j++)
3622 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j);
3623
3624 for (j = 0; j < 5; j++)
3625 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j);
3626
3627 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
3628 for (j = 0; j < 8; j++)
3629 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j);
3630 }
3631
3632 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3633 for (j = 0; j < 8; j++)
3634 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j);
3635
3636 for (j = 0; j < 8; j++)
3637 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j);
3638
3639 for (j = 0; j < 8; j++)
3640 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j);
3641 }
3642 }
3643
3644 dispc_runtime_put(dispc);
3645
3646 #undef DISPC_REG
3647 #undef DUMPREG
3648
3649 return 0;
3650 }
3651
3652 /* calculate clock rates using dividers in cinfo */
3653 int dispc_calc_clock_rates(struct dispc_device *dispc,
3654 unsigned long dispc_fclk_rate,
3655 struct dispc_clock_info *cinfo)
3656 {
3657 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3658 return -EINVAL;
3659 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3660 return -EINVAL;
3661
3662 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3663 cinfo->pck = cinfo->lck / cinfo->pck_div;
3664
3665 return 0;
3666 }
3667
3668 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
3669 unsigned long pck_min, unsigned long pck_max,
3670 dispc_div_calc_func func, void *data)
3671 {
3672 int lckd, lckd_start, lckd_stop;
3673 int pckd, pckd_start, pckd_stop;
3674 unsigned long pck, lck;
3675 unsigned long lck_max;
3676 unsigned long pckd_hw_min, pckd_hw_max;
3677 unsigned int min_fck_per_pck;
3678 unsigned long fck;
3679
3680 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3681 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3682 #else
3683 min_fck_per_pck = 0;
3684 #endif
3685
3686 pckd_hw_min = dispc->feat->min_pcd;
3687 pckd_hw_max = 255;
3688
3689 lck_max = dss_get_max_fck_rate(dispc->dss);
3690
3691 pck_min = pck_min ? pck_min : 1;
3692 pck_max = pck_max ? pck_max : ULONG_MAX;
3693
3694 lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul);
3695 lckd_stop = min(dispc_freq / pck_min, 255ul);
3696
3697 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3698 lck = dispc_freq / lckd;
3699
3700 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3701 pckd_stop = min(lck / pck_min, pckd_hw_max);
3702
3703 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3704 pck = lck / pckd;
3705
3706 /*
3707 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3708 * clock, which means we're configuring DISPC fclk here
3709 * also. Thus we need to use the calculated lck. For
3710 * OMAP4+ the DISPC fclk is a separate clock.
3711 */
3712 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
3713 fck = dispc_core_clk_rate(dispc);
3714 else
3715 fck = lck;
3716
3717 if (fck < pck * min_fck_per_pck)
3718 continue;
3719
3720 if (func(lckd, pckd, lck, pck, data))
3721 return true;
3722 }
3723 }
3724
3725 return false;
3726 }
3727
3728 void dispc_mgr_set_clock_div(struct dispc_device *dispc,
3729 enum omap_channel channel,
3730 const struct dispc_clock_info *cinfo)
3731 {
3732 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3733 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3734
3735 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div,
3736 cinfo->pck_div);
3737 }
3738
3739 int dispc_mgr_get_clock_div(struct dispc_device *dispc,
3740 enum omap_channel channel,
3741 struct dispc_clock_info *cinfo)
3742 {
3743 unsigned long fck;
3744
3745 fck = dispc_fclk_rate(dispc);
3746
3747 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3748 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0);
3749
3750 cinfo->lck = fck / cinfo->lck_div;
3751 cinfo->pck = cinfo->lck / cinfo->pck_div;
3752
3753 return 0;
3754 }
3755
3756 static u32 dispc_read_irqstatus(struct dispc_device *dispc)
3757 {
3758 return dispc_read_reg(dispc, DISPC_IRQSTATUS);
3759 }
3760
3761 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask)
3762 {
3763 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);
3764 }
3765
3766 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask)
3767 {
3768 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE);
3769
3770 /* clear the irqstatus for newly enabled irqs */
3771 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
3772
3773 dispc_write_reg(dispc, DISPC_IRQENABLE, mask);
3774
3775 /* flush posted write */
3776 dispc_read_reg(dispc, DISPC_IRQENABLE);
3777 }
3778
3779 void dispc_enable_sidle(struct dispc_device *dispc)
3780 {
3781 /* SIDLEMODE: smart idle */
3782 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3);
3783 }
3784
3785 void dispc_disable_sidle(struct dispc_device *dispc)
3786 {
3787 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3788 }
3789
3790 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
3791 enum omap_channel channel)
3792 {
3793 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3794
3795 if (!dispc->feat->has_gamma_table)
3796 return 0;
3797
3798 return gdesc->len;
3799 }
3800
3801 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc,
3802 enum omap_channel channel)
3803 {
3804 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3805 u32 *table = dispc->gamma_table[channel];
3806 unsigned int i;
3807
3808 DSSDBG("%s: channel %d\n", __func__, channel);
3809
3810 for (i = 0; i < gdesc->len; ++i) {
3811 u32 v = table[i];
3812
3813 if (gdesc->has_index)
3814 v |= i << 24;
3815 else if (i == 0)
3816 v |= 1 << 31;
3817
3818 dispc_write_reg(dispc, gdesc->reg, v);
3819 }
3820 }
3821
3822 static void dispc_restore_gamma_tables(struct dispc_device *dispc)
3823 {
3824 DSSDBG("%s()\n", __func__);
3825
3826 if (!dispc->feat->has_gamma_table)
3827 return;
3828
3829 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD);
3830
3831 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT);
3832
3833 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3834 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2);
3835
3836 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3837 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3);
3838 }
3839
3840 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3841 { .red = 0, .green = 0, .blue = 0, },
3842 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3843 };
3844
3845 static void dispc_mgr_set_gamma(struct dispc_device *dispc,
3846 enum omap_channel channel,
3847 const struct drm_color_lut *lut,
3848 unsigned int length)
3849 {
3850 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3851 u32 *table = dispc->gamma_table[channel];
3852 uint i;
3853
3854 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3855 channel, length, gdesc->len);
3856
3857 if (!dispc->feat->has_gamma_table)
3858 return;
3859
3860 if (lut == NULL || length < 2) {
3861 lut = dispc_mgr_gamma_default_lut;
3862 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3863 }
3864
3865 for (i = 0; i < length - 1; ++i) {
3866 uint first = i * (gdesc->len - 1) / (length - 1);
3867 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3868 uint w = last - first;
3869 u16 r, g, b;
3870 uint j;
3871
3872 if (w == 0)
3873 continue;
3874
3875 for (j = 0; j <= w; j++) {
3876 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3877 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3878 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3879
3880 r >>= 16 - gdesc->bits;
3881 g >>= 16 - gdesc->bits;
3882 b >>= 16 - gdesc->bits;
3883
3884 table[first + j] = (r << (gdesc->bits * 2)) |
3885 (g << gdesc->bits) | b;
3886 }
3887 }
3888
3889 if (dispc->is_enabled)
3890 dispc_mgr_write_gamma_table(dispc, channel);
3891 }
3892
3893 static int dispc_init_gamma_tables(struct dispc_device *dispc)
3894 {
3895 int channel;
3896
3897 if (!dispc->feat->has_gamma_table)
3898 return 0;
3899
3900 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) {
3901 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3902 u32 *gt;
3903
3904 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3905 !dispc_has_feature(dispc, FEAT_MGR_LCD2))
3906 continue;
3907
3908 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3909 !dispc_has_feature(dispc, FEAT_MGR_LCD3))
3910 continue;
3911
3912 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len,
3913 sizeof(u32), GFP_KERNEL);
3914 if (!gt)
3915 return -ENOMEM;
3916
3917 dispc->gamma_table[channel] = gt;
3918
3919 dispc_mgr_set_gamma(dispc, channel, NULL, 0);
3920 }
3921 return 0;
3922 }
3923
3924 static void _omap_dispc_initial_config(struct dispc_device *dispc)
3925 {
3926 u32 l;
3927
3928 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3929 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3930 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3931 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3932 l = FLD_MOD(l, 1, 0, 0);
3933 l = FLD_MOD(l, 1, 23, 16);
3934 dispc_write_reg(dispc, DISPC_DIVISOR, l);
3935
3936 dispc->core_clk_rate = dispc_fclk_rate(dispc);
3937 }
3938
3939 /* Use gamma table mode, instead of palette mode */
3940 if (dispc->feat->has_gamma_table)
3941 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3);
3942
3943 /* For older DSS versions (FEAT_FUNCGATED) this enables
3944 * func-clock auto-gating. For newer versions
3945 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables.
3946 */
3947 if (dispc_has_feature(dispc, FEAT_FUNCGATED) ||
3948 dispc->feat->has_gamma_table)
3949 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9);
3950
3951 dispc_setup_color_conv_coef(dispc);
3952
3953 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY);
3954
3955 dispc_init_fifos(dispc);
3956
3957 dispc_configure_burst_sizes(dispc);
3958
3959 dispc_ovl_enable_zorder_planes(dispc);
3960
3961 if (dispc->feat->mstandby_workaround)
3962 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0);
3963
3964 if (dispc_has_feature(dispc, FEAT_MFLAG))
3965 dispc_init_mflag(dispc);
3966 }
3967
3968 static const enum dispc_feature_id omap2_dispc_features_list[] = {
3969 FEAT_LCDENABLEPOL,
3970 FEAT_LCDENABLESIGNAL,
3971 FEAT_PCKFREEENABLE,
3972 FEAT_FUNCGATED,
3973 FEAT_ROWREPEATENABLE,
3974 FEAT_RESIZECONF,
3975 };
3976
3977 static const enum dispc_feature_id omap3_dispc_features_list[] = {
3978 FEAT_LCDENABLEPOL,
3979 FEAT_LCDENABLESIGNAL,
3980 FEAT_PCKFREEENABLE,
3981 FEAT_FUNCGATED,
3982 FEAT_LINEBUFFERSPLIT,
3983 FEAT_ROWREPEATENABLE,
3984 FEAT_RESIZECONF,
3985 FEAT_CPR,
3986 FEAT_PRELOAD,
3987 FEAT_FIR_COEF_V,
3988 FEAT_ALPHA_FIXED_ZORDER,
3989 FEAT_FIFO_MERGE,
3990 FEAT_OMAP3_DSI_FIFO_BUG,
3991 };
3992
3993 static const enum dispc_feature_id am43xx_dispc_features_list[] = {
3994 FEAT_LCDENABLEPOL,
3995 FEAT_LCDENABLESIGNAL,
3996 FEAT_PCKFREEENABLE,
3997 FEAT_FUNCGATED,
3998 FEAT_LINEBUFFERSPLIT,
3999 FEAT_ROWREPEATENABLE,
4000 FEAT_RESIZECONF,
4001 FEAT_CPR,
4002 FEAT_PRELOAD,
4003 FEAT_FIR_COEF_V,
4004 FEAT_ALPHA_FIXED_ZORDER,
4005 FEAT_FIFO_MERGE,
4006 };
4007
4008 static const enum dispc_feature_id omap4_dispc_features_list[] = {
4009 FEAT_MGR_LCD2,
4010 FEAT_CORE_CLK_DIV,
4011 FEAT_HANDLE_UV_SEPARATE,
4012 FEAT_ATTR2,
4013 FEAT_CPR,
4014 FEAT_PRELOAD,
4015 FEAT_FIR_COEF_V,
4016 FEAT_ALPHA_FREE_ZORDER,
4017 FEAT_FIFO_MERGE,
4018 FEAT_BURST_2D,
4019 };
4020
4021 static const enum dispc_feature_id omap5_dispc_features_list[] = {
4022 FEAT_MGR_LCD2,
4023 FEAT_MGR_LCD3,
4024 FEAT_CORE_CLK_DIV,
4025 FEAT_HANDLE_UV_SEPARATE,
4026 FEAT_ATTR2,
4027 FEAT_CPR,
4028 FEAT_PRELOAD,
4029 FEAT_FIR_COEF_V,
4030 FEAT_ALPHA_FREE_ZORDER,
4031 FEAT_FIFO_MERGE,
4032 FEAT_BURST_2D,
4033 FEAT_MFLAG,
4034 };
4035
4036 static const struct dss_reg_field omap2_dispc_reg_fields[] = {
4037 [FEAT_REG_FIRHINC] = { 11, 0 },
4038 [FEAT_REG_FIRVINC] = { 27, 16 },
4039 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
4040 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
4041 [FEAT_REG_FIFOSIZE] = { 8, 0 },
4042 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
4043 [FEAT_REG_VERTICALACCU] = { 25, 16 },
4044 };
4045
4046 static const struct dss_reg_field omap3_dispc_reg_fields[] = {
4047 [FEAT_REG_FIRHINC] = { 12, 0 },
4048 [FEAT_REG_FIRVINC] = { 28, 16 },
4049 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
4050 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
4051 [FEAT_REG_FIFOSIZE] = { 10, 0 },
4052 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
4053 [FEAT_REG_VERTICALACCU] = { 25, 16 },
4054 };
4055
4056 static const struct dss_reg_field omap4_dispc_reg_fields[] = {
4057 [FEAT_REG_FIRHINC] = { 12, 0 },
4058 [FEAT_REG_FIRVINC] = { 28, 16 },
4059 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
4060 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
4061 [FEAT_REG_FIFOSIZE] = { 15, 0 },
4062 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
4063 [FEAT_REG_VERTICALACCU] = { 26, 16 },
4064 };
4065
4066 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = {
4067 /* OMAP_DSS_GFX */
4068 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4069
4070 /* OMAP_DSS_VIDEO1 */
4071 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4072 OMAP_DSS_OVL_CAP_REPLICATION,
4073
4074 /* OMAP_DSS_VIDEO2 */
4075 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4076 OMAP_DSS_OVL_CAP_REPLICATION,
4077 };
4078
4079 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = {
4080 /* OMAP_DSS_GFX */
4081 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
4082 OMAP_DSS_OVL_CAP_REPLICATION,
4083
4084 /* OMAP_DSS_VIDEO1 */
4085 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4086 OMAP_DSS_OVL_CAP_REPLICATION,
4087
4088 /* OMAP_DSS_VIDEO2 */
4089 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4090 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4091 };
4092
4093 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = {
4094 /* OMAP_DSS_GFX */
4095 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
4096 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4097
4098 /* OMAP_DSS_VIDEO1 */
4099 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4100 OMAP_DSS_OVL_CAP_REPLICATION,
4101
4102 /* OMAP_DSS_VIDEO2 */
4103 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4104 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
4105 OMAP_DSS_OVL_CAP_REPLICATION,
4106 };
4107
4108 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = {
4109 /* OMAP_DSS_GFX */
4110 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
4111 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
4112 OMAP_DSS_OVL_CAP_REPLICATION,
4113
4114 /* OMAP_DSS_VIDEO1 */
4115 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4116 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4117 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4118
4119 /* OMAP_DSS_VIDEO2 */
4120 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4121 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4122 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4123
4124 /* OMAP_DSS_VIDEO3 */
4125 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4126 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4127 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4128 };
4129
4130 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 }
4131
4132 static const u32 *omap2_dispc_supported_color_modes[] = {
4133
4134 /* OMAP_DSS_GFX */
4135 COLOR_ARRAY(
4136 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
4137 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888),
4138
4139 /* OMAP_DSS_VIDEO1 */
4140 COLOR_ARRAY(
4141 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4142 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4143 DRM_FORMAT_UYVY),
4144
4145 /* OMAP_DSS_VIDEO2 */
4146 COLOR_ARRAY(
4147 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4148 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4149 DRM_FORMAT_UYVY),
4150 };
4151
4152 static const u32 *omap3_dispc_supported_color_modes[] = {
4153 /* OMAP_DSS_GFX */
4154 COLOR_ARRAY(
4155 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4156 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4157 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
4158 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
4159
4160 /* OMAP_DSS_VIDEO1 */
4161 COLOR_ARRAY(
4162 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888,
4163 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
4164 DRM_FORMAT_YUYV, DRM_FORMAT_UYVY),
4165
4166 /* OMAP_DSS_VIDEO2 */
4167 COLOR_ARRAY(
4168 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4169 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4170 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4171 DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888,
4172 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
4173 };
4174
4175 static const u32 *omap4_dispc_supported_color_modes[] = {
4176 /* OMAP_DSS_GFX */
4177 COLOR_ARRAY(
4178 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4179 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4180 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
4181 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888,
4182 DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444,
4183 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555),
4184
4185 /* OMAP_DSS_VIDEO1 */
4186 COLOR_ARRAY(
4187 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4188 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4189 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4190 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4191 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4192 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4193 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4194 DRM_FORMAT_RGBX8888),
4195
4196 /* OMAP_DSS_VIDEO2 */
4197 COLOR_ARRAY(
4198 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4199 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4200 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4201 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4202 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4203 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4204 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4205 DRM_FORMAT_RGBX8888),
4206
4207 /* OMAP_DSS_VIDEO3 */
4208 COLOR_ARRAY(
4209 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4210 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4211 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4212 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4213 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4214 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4215 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4216 DRM_FORMAT_RGBX8888),
4217
4218 /* OMAP_DSS_WB */
4219 COLOR_ARRAY(
4220 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4221 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4222 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4223 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4224 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4225 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4226 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4227 DRM_FORMAT_RGBX8888),
4228 };
4229
4230 static const u32 omap3_dispc_supported_scaler_color_modes[] = {
4231 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_YUYV,
4232 DRM_FORMAT_UYVY,
4233 0,
4234 };
4235
4236 static const struct dispc_features omap24xx_dispc_feats = {
4237 .sw_start = 5,
4238 .fp_start = 15,
4239 .bp_start = 27,
4240 .sw_max = 64,
4241 .vp_max = 255,
4242 .hp_max = 256,
4243 .mgr_width_start = 10,
4244 .mgr_height_start = 26,
4245 .mgr_width_max = 2048,
4246 .mgr_height_max = 2048,
4247 .max_lcd_pclk = 66500000,
4248 .max_downscale = 2,
4249 /*
4250 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4251 * cannot scale an image width larger than 768.
4252 */
4253 .max_line_width = 768,
4254 .min_pcd = 2,
4255 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4256 .calc_core_clk = calc_core_clk_24xx,
4257 .num_fifos = 3,
4258 .features = omap2_dispc_features_list,
4259 .num_features = ARRAY_SIZE(omap2_dispc_features_list),
4260 .reg_fields = omap2_dispc_reg_fields,
4261 .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields),
4262 .overlay_caps = omap2_dispc_overlay_caps,
4263 .supported_color_modes = omap2_dispc_supported_color_modes,
4264 .supported_scaler_color_modes = COLOR_ARRAY(DRM_FORMAT_XRGB8888),
4265 .num_mgrs = 2,
4266 .num_ovls = 3,
4267 .buffer_size_unit = 1,
4268 .burst_size_unit = 8,
4269 .no_framedone_tv = true,
4270 .set_max_preload = false,
4271 .last_pixel_inc_missing = true,
4272 };
4273
4274 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
4275 .sw_start = 5,
4276 .fp_start = 15,
4277 .bp_start = 27,
4278 .sw_max = 64,
4279 .vp_max = 255,
4280 .hp_max = 256,
4281 .mgr_width_start = 10,
4282 .mgr_height_start = 26,
4283 .mgr_width_max = 2048,
4284 .mgr_height_max = 2048,
4285 .max_lcd_pclk = 173000000,
4286 .max_tv_pclk = 59000000,
4287 .max_downscale = 4,
4288 .max_line_width = 1024,
4289 .min_pcd = 1,
4290 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4291 .calc_core_clk = calc_core_clk_34xx,
4292 .num_fifos = 3,
4293 .features = omap3_dispc_features_list,
4294 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4295 .reg_fields = omap3_dispc_reg_fields,
4296 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4297 .overlay_caps = omap3430_dispc_overlay_caps,
4298 .supported_color_modes = omap3_dispc_supported_color_modes,
4299 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes,
4300 .num_mgrs = 2,
4301 .num_ovls = 3,
4302 .buffer_size_unit = 1,
4303 .burst_size_unit = 8,
4304 .no_framedone_tv = true,
4305 .set_max_preload = false,
4306 .last_pixel_inc_missing = true,
4307 };
4308
4309 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
4310 .sw_start = 7,
4311 .fp_start = 19,
4312 .bp_start = 31,
4313 .sw_max = 256,
4314 .vp_max = 4095,
4315 .hp_max = 4096,
4316 .mgr_width_start = 10,
4317 .mgr_height_start = 26,
4318 .mgr_width_max = 2048,
4319 .mgr_height_max = 2048,
4320 .max_lcd_pclk = 173000000,
4321 .max_tv_pclk = 59000000,
4322 .max_downscale = 4,
4323 .max_line_width = 1024,
4324 .min_pcd = 1,
4325 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4326 .calc_core_clk = calc_core_clk_34xx,
4327 .num_fifos = 3,
4328 .features = omap3_dispc_features_list,
4329 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4330 .reg_fields = omap3_dispc_reg_fields,
4331 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4332 .overlay_caps = omap3430_dispc_overlay_caps,
4333 .supported_color_modes = omap3_dispc_supported_color_modes,
4334 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes,
4335 .num_mgrs = 2,
4336 .num_ovls = 3,
4337 .buffer_size_unit = 1,
4338 .burst_size_unit = 8,
4339 .no_framedone_tv = true,
4340 .set_max_preload = false,
4341 .last_pixel_inc_missing = true,
4342 };
4343
4344 static const struct dispc_features omap36xx_dispc_feats = {
4345 .sw_start = 7,
4346 .fp_start = 19,
4347 .bp_start = 31,
4348 .sw_max = 256,
4349 .vp_max = 4095,
4350 .hp_max = 4096,
4351 .mgr_width_start = 10,
4352 .mgr_height_start = 26,
4353 .mgr_width_max = 2048,
4354 .mgr_height_max = 2048,
4355 .max_lcd_pclk = 173000000,
4356 .max_tv_pclk = 59000000,
4357 .max_downscale = 4,
4358 .max_line_width = 1024,
4359 .min_pcd = 1,
4360 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4361 .calc_core_clk = calc_core_clk_34xx,
4362 .num_fifos = 3,
4363 .features = omap3_dispc_features_list,
4364 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4365 .reg_fields = omap3_dispc_reg_fields,
4366 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4367 .overlay_caps = omap3630_dispc_overlay_caps,
4368 .supported_color_modes = omap3_dispc_supported_color_modes,
4369 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes,
4370 .num_mgrs = 2,
4371 .num_ovls = 3,
4372 .buffer_size_unit = 1,
4373 .burst_size_unit = 8,
4374 .no_framedone_tv = true,
4375 .set_max_preload = false,
4376 .last_pixel_inc_missing = true,
4377 };
4378
4379 static const struct dispc_features am43xx_dispc_feats = {
4380 .sw_start = 7,
4381 .fp_start = 19,
4382 .bp_start = 31,
4383 .sw_max = 256,
4384 .vp_max = 4095,
4385 .hp_max = 4096,
4386 .mgr_width_start = 10,
4387 .mgr_height_start = 26,
4388 .mgr_width_max = 2048,
4389 .mgr_height_max = 2048,
4390 .max_lcd_pclk = 173000000,
4391 .max_tv_pclk = 59000000,
4392 .max_downscale = 4,
4393 .max_line_width = 1024,
4394 .min_pcd = 1,
4395 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4396 .calc_core_clk = calc_core_clk_34xx,
4397 .num_fifos = 3,
4398 .features = am43xx_dispc_features_list,
4399 .num_features = ARRAY_SIZE(am43xx_dispc_features_list),
4400 .reg_fields = omap3_dispc_reg_fields,
4401 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4402 .overlay_caps = omap3430_dispc_overlay_caps,
4403 .supported_color_modes = omap3_dispc_supported_color_modes,
4404 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes,
4405 .num_mgrs = 1,
4406 .num_ovls = 3,
4407 .buffer_size_unit = 1,
4408 .burst_size_unit = 8,
4409 .no_framedone_tv = true,
4410 .set_max_preload = false,
4411 .last_pixel_inc_missing = true,
4412 };
4413
4414 static const struct dispc_features omap44xx_dispc_feats = {
4415 .sw_start = 7,
4416 .fp_start = 19,
4417 .bp_start = 31,
4418 .sw_max = 256,
4419 .vp_max = 4095,
4420 .hp_max = 4096,
4421 .mgr_width_start = 10,
4422 .mgr_height_start = 26,
4423 .mgr_width_max = 2048,
4424 .mgr_height_max = 2048,
4425 .max_lcd_pclk = 170000000,
4426 .max_tv_pclk = 185625000,
4427 .max_downscale = 4,
4428 .max_line_width = 2048,
4429 .min_pcd = 1,
4430 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4431 .calc_core_clk = calc_core_clk_44xx,
4432 .num_fifos = 5,
4433 .features = omap4_dispc_features_list,
4434 .num_features = ARRAY_SIZE(omap4_dispc_features_list),
4435 .reg_fields = omap4_dispc_reg_fields,
4436 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
4437 .overlay_caps = omap4_dispc_overlay_caps,
4438 .supported_color_modes = omap4_dispc_supported_color_modes,
4439 .num_mgrs = 3,
4440 .num_ovls = 4,
4441 .buffer_size_unit = 16,
4442 .burst_size_unit = 16,
4443 .gfx_fifo_workaround = true,
4444 .set_max_preload = true,
4445 .supports_sync_align = true,
4446 .has_writeback = true,
4447 .supports_double_pixel = true,
4448 .reverse_ilace_field_order = true,
4449 .has_gamma_table = true,
4450 .has_gamma_i734_bug = true,
4451 };
4452
4453 static const struct dispc_features omap54xx_dispc_feats = {
4454 .sw_start = 7,
4455 .fp_start = 19,
4456 .bp_start = 31,
4457 .sw_max = 256,
4458 .vp_max = 4095,
4459 .hp_max = 4096,
4460 .mgr_width_start = 11,
4461 .mgr_height_start = 27,
4462 .mgr_width_max = 4096,
4463 .mgr_height_max = 4096,
4464 .max_lcd_pclk = 170000000,
4465 .max_tv_pclk = 186000000,
4466 .max_downscale = 4,
4467 .max_line_width = 2048,
4468 .min_pcd = 1,
4469 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4470 .calc_core_clk = calc_core_clk_44xx,
4471 .num_fifos = 5,
4472 .features = omap5_dispc_features_list,
4473 .num_features = ARRAY_SIZE(omap5_dispc_features_list),
4474 .reg_fields = omap4_dispc_reg_fields,
4475 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
4476 .overlay_caps = omap4_dispc_overlay_caps,
4477 .supported_color_modes = omap4_dispc_supported_color_modes,
4478 .num_mgrs = 4,
4479 .num_ovls = 4,
4480 .buffer_size_unit = 16,
4481 .burst_size_unit = 16,
4482 .gfx_fifo_workaround = true,
4483 .mstandby_workaround = true,
4484 .set_max_preload = true,
4485 .supports_sync_align = true,
4486 .has_writeback = true,
4487 .supports_double_pixel = true,
4488 .reverse_ilace_field_order = true,
4489 .has_gamma_table = true,
4490 .has_gamma_i734_bug = true,
4491 };
4492
4493 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4494 {
4495 struct dispc_device *dispc = arg;
4496
4497 if (!dispc->is_enabled)
4498 return IRQ_NONE;
4499
4500 return dispc->user_handler(irq, dispc->user_data);
4501 }
4502
4503 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
4504 void *dev_id)
4505 {
4506 int r;
4507
4508 if (dispc->user_handler != NULL)
4509 return -EBUSY;
4510
4511 dispc->user_handler = handler;
4512 dispc->user_data = dev_id;
4513
4514 /* ensure the dispc_irq_handler sees the values above */
4515 smp_wmb();
4516
4517 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler,
4518 IRQF_SHARED, "OMAP DISPC", dispc);
4519 if (r) {
4520 dispc->user_handler = NULL;
4521 dispc->user_data = NULL;
4522 }
4523
4524 return r;
4525 }
4526
4527 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id)
4528 {
4529 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc);
4530
4531 dispc->user_handler = NULL;
4532 dispc->user_data = NULL;
4533 }
4534
4535 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc)
4536 {
4537 u32 limit = 0;
4538
4539 /* Optional maximum memory bandwidth */
4540 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth",
4541 &limit);
4542
4543 return limit;
4544 }
4545
4546 /*
4547 * Workaround for errata i734 in DSS dispc
4548 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4549 *
4550 * For gamma tables to work on LCD1 the GFX plane has to be used at
4551 * least once after DSS HW has come out of reset. The workaround
4552 * sets up a minimal LCD setup with GFX plane and waits for one
4553 * vertical sync irq before disabling the setup and continuing with
4554 * the context restore. The physical outputs are gated during the
4555 * operation. This workaround requires that gamma table's LOADMODE
4556 * is set to 0x2 in DISPC_CONTROL1 register.
4557 *
4558 * For details see:
4559 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4560 * Literature Number: SWPZ037E
4561 * Or some other relevant errata document for the DSS IP version.
4562 */
4563
4564 static const struct dispc_errata_i734_data {
4565 struct videomode vm;
4566 struct omap_overlay_info ovli;
4567 struct omap_overlay_manager_info mgri;
4568 struct dss_lcd_mgr_config lcd_conf;
4569 } i734 = {
4570 .vm = {
4571 .hactive = 8, .vactive = 1,
4572 .pixelclock = 16000000,
4573 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4574 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
4575
4576 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4577 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
4578 DISPLAY_FLAGS_PIXDATA_POSEDGE,
4579 },
4580 .ovli = {
4581 .screen_width = 1,
4582 .width = 1, .height = 1,
4583 .fourcc = DRM_FORMAT_XRGB8888,
4584 .rotation = DRM_MODE_ROTATE_0,
4585 .rotation_type = OMAP_DSS_ROT_NONE,
4586 .pos_x = 0, .pos_y = 0,
4587 .out_width = 0, .out_height = 0,
4588 .global_alpha = 0xff,
4589 .pre_mult_alpha = 0,
4590 .zorder = 0,
4591 },
4592 .mgri = {
4593 .default_color = 0,
4594 .trans_enabled = false,
4595 .partial_alpha_enabled = false,
4596 .cpr_enable = false,
4597 },
4598 .lcd_conf = {
4599 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
4600 .stallmode = false,
4601 .fifohandcheck = false,
4602 .clock_info = {
4603 .lck_div = 1,
4604 .pck_div = 2,
4605 },
4606 .video_port_width = 24,
4607 .lcden_sig_polarity = 0,
4608 },
4609 };
4610
4611 static struct i734_buf {
4612 size_t size;
4613 dma_addr_t paddr;
4614 void *vaddr;
4615 } i734_buf;
4616
4617 static int dispc_errata_i734_wa_init(struct dispc_device *dispc)
4618 {
4619 if (!dispc->feat->has_gamma_i734_bug)
4620 return 0;
4621
4622 i734_buf.size = i734.ovli.width * i734.ovli.height *
4623 color_mode_to_bpp(i734.ovli.fourcc) / 8;
4624
4625 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size,
4626 &i734_buf.paddr, GFP_KERNEL);
4627 if (!i734_buf.vaddr) {
4628 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n",
4629 __func__);
4630 return -ENOMEM;
4631 }
4632
4633 return 0;
4634 }
4635
4636 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc)
4637 {
4638 if (!dispc->feat->has_gamma_i734_bug)
4639 return;
4640
4641 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr,
4642 i734_buf.paddr);
4643 }
4644
4645 static void dispc_errata_i734_wa(struct dispc_device *dispc)
4646 {
4647 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc,
4648 OMAP_DSS_CHANNEL_LCD);
4649 struct omap_overlay_info ovli;
4650 struct dss_lcd_mgr_config lcd_conf;
4651 u32 gatestate;
4652 unsigned int count;
4653
4654 if (!dispc->feat->has_gamma_i734_bug)
4655 return;
4656
4657 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4);
4658
4659 ovli = i734.ovli;
4660 ovli.paddr = i734_buf.paddr;
4661 lcd_conf = i734.lcd_conf;
4662
4663 /* Gate all LCD1 outputs */
4664 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4);
4665
4666 /* Setup and enable GFX plane */
4667 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false,
4668 OMAP_DSS_CHANNEL_LCD);
4669 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true);
4670
4671 /* Set up and enable display manager for LCD1 */
4672 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4673 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss),
4674 &lcd_conf.clock_info);
4675 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4676 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm);
4677
4678 dispc_clear_irqstatus(dispc, framedone_irq);
4679
4680 /* Enable and shut the channel to produce just one frame */
4681 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true);
4682 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false);
4683
4684 /* Busy wait for framedone. We can't fiddle with irq handlers
4685 * in PM resume. Typically the loop runs less than 5 times and
4686 * waits less than a micro second.
4687 */
4688 count = 0;
4689 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) {
4690 if (count++ > 10000) {
4691 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n",
4692 __func__);
4693 break;
4694 }
4695 }
4696 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false);
4697
4698 /* Clear all irq bits before continuing */
4699 dispc_clear_irqstatus(dispc, 0xffffffff);
4700
4701 /* Restore the original state to LCD1 output gates */
4702 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);
4703 }
4704
4705 static const struct dispc_ops dispc_ops = {
4706 .read_irqstatus = dispc_read_irqstatus,
4707 .clear_irqstatus = dispc_clear_irqstatus,
4708 .write_irqenable = dispc_write_irqenable,
4709
4710 .request_irq = dispc_request_irq,
4711 .free_irq = dispc_free_irq,
4712
4713 .runtime_get = dispc_runtime_get,
4714 .runtime_put = dispc_runtime_put,
4715
4716 .get_num_ovls = dispc_get_num_ovls,
4717 .get_num_mgrs = dispc_get_num_mgrs,
4718
4719 .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,
4720
4721 .mgr_enable = dispc_mgr_enable,
4722 .mgr_is_enabled = dispc_mgr_is_enabled,
4723 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,
4724 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq,
4725 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq,
4726 .mgr_go_busy = dispc_mgr_go_busy,
4727 .mgr_go = dispc_mgr_go,
4728 .mgr_set_lcd_config = dispc_mgr_set_lcd_config,
4729 .mgr_check_timings = dispc_mgr_check_timings,
4730 .mgr_set_timings = dispc_mgr_set_timings,
4731 .mgr_setup = dispc_mgr_setup,
4732 .mgr_gamma_size = dispc_mgr_gamma_size,
4733 .mgr_set_gamma = dispc_mgr_set_gamma,
4734
4735 .ovl_enable = dispc_ovl_enable,
4736 .ovl_setup = dispc_ovl_setup,
4737 .ovl_get_color_modes = dispc_ovl_get_color_modes,
4738
4739 .wb_get_framedone_irq = dispc_wb_get_framedone_irq,
4740 .wb_setup = dispc_wb_setup,
4741 .has_writeback = dispc_has_writeback,
4742 .wb_go_busy = dispc_wb_go_busy,
4743 .wb_go = dispc_wb_go,
4744 };
4745
4746 /* DISPC HW IP initialisation */
4747 static const struct of_device_id dispc_of_match[] = {
4748 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4749 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4750 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4751 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4752 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4753 {},
4754 };
4755
4756 static const struct soc_device_attribute dispc_soc_devices[] = {
4757 { .machine = "OMAP3[45]*",
4758 .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats },
4759 { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats },
4760 { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats },
4761 { .machine = "AM43*", .data = &am43xx_dispc_feats },
4762 { /* sentinel */ }
4763 };
4764
4765 static int dispc_bind(struct device *dev, struct device *master, void *data)
4766 {
4767 struct platform_device *pdev = to_platform_device(dev);
4768 const struct soc_device_attribute *soc;
4769 struct dss_device *dss = dss_get_device(master);
4770 struct dispc_device *dispc;
4771 u32 rev;
4772 int r = 0;
4773 struct resource *dispc_mem;
4774 struct device_node *np = pdev->dev.of_node;
4775
4776 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL);
4777 if (!dispc)
4778 return -ENOMEM;
4779
4780 dispc->pdev = pdev;
4781 platform_set_drvdata(pdev, dispc);
4782 dispc->dss = dss;
4783
4784 /*
4785 * The OMAP3-based models can't be told apart using the compatible
4786 * string, use SoC device matching.
4787 */
4788 soc = soc_device_match(dispc_soc_devices);
4789 if (soc)
4790 dispc->feat = soc->data;
4791 else
4792 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data;
4793
4794 r = dispc_errata_i734_wa_init(dispc);
4795 if (r)
4796 goto err_free;
4797
4798 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0);
4799 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem);
4800 if (IS_ERR(dispc->base)) {
4801 r = PTR_ERR(dispc->base);
4802 goto err_free;
4803 }
4804
4805 dispc->irq = platform_get_irq(dispc->pdev, 0);
4806 if (dispc->irq < 0) {
4807 DSSERR("platform_get_irq failed\n");
4808 r = -ENODEV;
4809 goto err_free;
4810 }
4811
4812 if (np && of_property_read_bool(np, "syscon-pol")) {
4813 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4814 if (IS_ERR(dispc->syscon_pol)) {
4815 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4816 r = PTR_ERR(dispc->syscon_pol);
4817 goto err_free;
4818 }
4819
4820 if (of_property_read_u32_index(np, "syscon-pol", 1,
4821 &dispc->syscon_pol_offset)) {
4822 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4823 r = -EINVAL;
4824 goto err_free;
4825 }
4826 }
4827
4828 r = dispc_init_gamma_tables(dispc);
4829 if (r)
4830 goto err_free;
4831
4832 pm_runtime_enable(&pdev->dev);
4833
4834 r = dispc_runtime_get(dispc);
4835 if (r)
4836 goto err_runtime_get;
4837
4838 _omap_dispc_initial_config(dispc);
4839
4840 rev = dispc_read_reg(dispc, DISPC_REVISION);
4841 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4842 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4843
4844 dispc_runtime_put(dispc);
4845
4846 dss->dispc = dispc;
4847 dss->dispc_ops = &dispc_ops;
4848
4849 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs,
4850 dispc);
4851
4852 return 0;
4853
4854 err_runtime_get:
4855 pm_runtime_disable(&pdev->dev);
4856 err_free:
4857 kfree(dispc);
4858 return r;
4859 }
4860
4861 static void dispc_unbind(struct device *dev, struct device *master, void *data)
4862 {
4863 struct dispc_device *dispc = dev_get_drvdata(dev);
4864 struct dss_device *dss = dispc->dss;
4865
4866 dss_debugfs_remove_file(dispc->debugfs);
4867
4868 dss->dispc = NULL;
4869 dss->dispc_ops = NULL;
4870
4871 pm_runtime_disable(dev);
4872
4873 dispc_errata_i734_wa_fini(dispc);
4874
4875 kfree(dispc);
4876 }
4877
4878 static const struct component_ops dispc_component_ops = {
4879 .bind = dispc_bind,
4880 .unbind = dispc_unbind,
4881 };
4882
4883 static int dispc_probe(struct platform_device *pdev)
4884 {
4885 return component_add(&pdev->dev, &dispc_component_ops);
4886 }
4887
4888 static int dispc_remove(struct platform_device *pdev)
4889 {
4890 component_del(&pdev->dev, &dispc_component_ops);
4891 return 0;
4892 }
4893
4894 static int dispc_runtime_suspend(struct device *dev)
4895 {
4896 struct dispc_device *dispc = dev_get_drvdata(dev);
4897
4898 dispc->is_enabled = false;
4899 /* ensure the dispc_irq_handler sees the is_enabled value */
4900 smp_wmb();
4901 /* wait for current handler to finish before turning the DISPC off */
4902 synchronize_irq(dispc->irq);
4903
4904 dispc_save_context(dispc);
4905
4906 return 0;
4907 }
4908
4909 static int dispc_runtime_resume(struct device *dev)
4910 {
4911 struct dispc_device *dispc = dev_get_drvdata(dev);
4912
4913 /*
4914 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4915 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4916 * _omap_dispc_initial_config(). We can thus use it to detect if
4917 * we have lost register context.
4918 */
4919 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4920 _omap_dispc_initial_config(dispc);
4921
4922 dispc_errata_i734_wa(dispc);
4923
4924 dispc_restore_context(dispc);
4925
4926 dispc_restore_gamma_tables(dispc);
4927 }
4928
4929 dispc->is_enabled = true;
4930 /* ensure the dispc_irq_handler sees the is_enabled value */
4931 smp_wmb();
4932
4933 return 0;
4934 }
4935
4936 static const struct dev_pm_ops dispc_pm_ops = {
4937 .runtime_suspend = dispc_runtime_suspend,
4938 .runtime_resume = dispc_runtime_resume,
4939 };
4940
4941 struct platform_driver omap_dispchw_driver = {
4942 .probe = dispc_probe,
4943 .remove = dispc_remove,
4944 .driver = {
4945 .name = "omapdss_dispc",
4946 .pm = &dispc_pm_ops,
4947 .of_match_table = dispc_of_match,
4948 .suppress_bind_attrs = true,
4949 },
4950 };
Linux with added FPC-III support