drivers/gpu/drm/omapdrm/dss/hdmi.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * HDMI driver definition for TI OMAP4 Processor.
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #ifndef _HDMI_H
   9 #define _HDMI_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/hdmi.h>
  15 #include <sound/omap-hdmi-audio.h>
  16 #include <media/cec.h>
  17
  18 #include "omapdss.h"
  19 #include "dss.h"
  20
  21 struct dss_device;
  22
  23 /* HDMI Wrapper */
  24
  25 #define HDMI_WP_REVISION                        0x0
  26 #define HDMI_WP_SYSCONFIG                       0x10
  27 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  28 #define HDMI_WP_IRQSTATUS                       0x28
  29 #define HDMI_WP_IRQENABLE_SET                   0x2C
  30 #define HDMI_WP_IRQENABLE_CLR                   0x30
  31 #define HDMI_WP_IRQWAKEEN                       0x34
  32 #define HDMI_WP_PWR_CTRL                        0x40
  33 #define HDMI_WP_DEBOUNCE                        0x44
  34 #define HDMI_WP_VIDEO_CFG                       0x50
  35 #define HDMI_WP_VIDEO_SIZE                      0x60
  36 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  37 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  38 #define HDMI_WP_CLK                             0x70
  39 #define HDMI_WP_AUDIO_CFG                       0x80
  40 #define HDMI_WP_AUDIO_CFG2                      0x84
  41 #define HDMI_WP_AUDIO_CTRL                      0x88
  42 #define HDMI_WP_AUDIO_DATA                      0x8C
  43
  44 /* HDMI WP IRQ flags */
  45 #define HDMI_IRQ_CORE                           (1 << 0)
  46 #define HDMI_IRQ_OCP_TIMEOUT                    (1 << 4)
  47 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW           (1 << 8)
  48 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW            (1 << 9)
  49 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ          (1 << 10)
  50 #define HDMI_IRQ_VIDEO_VSYNC                    (1 << 16)
  51 #define HDMI_IRQ_VIDEO_FRAME_DONE               (1 << 17)
  52 #define HDMI_IRQ_PHY_LINE5V_ASSERT              (1 << 24)
  53 #define HDMI_IRQ_LINK_CONNECT                   (1 << 25)
  54 #define HDMI_IRQ_LINK_DISCONNECT                (1 << 26)
  55 #define HDMI_IRQ_PLL_LOCK                       (1 << 29)
  56 #define HDMI_IRQ_PLL_UNLOCK                     (1 << 30)
  57 #define HDMI_IRQ_PLL_RECAL                      (1 << 31)
  58
  59 /* HDMI PLL */
  60
  61 #define PLLCTRL_PLL_CONTROL                     0x0
  62 #define PLLCTRL_PLL_STATUS                      0x4
  63 #define PLLCTRL_PLL_GO                          0x8
  64 #define PLLCTRL_CFG1                            0xC
  65 #define PLLCTRL_CFG2                            0x10
  66 #define PLLCTRL_CFG3                            0x14
  67 #define PLLCTRL_SSC_CFG1                        0x18
  68 #define PLLCTRL_SSC_CFG2                        0x1C
  69 #define PLLCTRL_CFG4                            0x20
  70
  71 /* HDMI PHY */
  72
  73 #define HDMI_TXPHY_TX_CTRL                      0x0
  74 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
  75 #define HDMI_TXPHY_POWER_CTRL                   0x8
  76 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
  77 #define HDMI_TXPHY_BIST_CONTROL                 0x1C
  78
  79 enum hdmi_pll_pwr {
  80         HDMI_PLLPWRCMD_ALLOFF = 0,
  81         HDMI_PLLPWRCMD_PLLONLY = 1,
  82         HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
  83         HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
  84 };
  85
  86 enum hdmi_phy_pwr {
  87         HDMI_PHYPWRCMD_OFF = 0,
  88         HDMI_PHYPWRCMD_LDOON = 1,
  89         HDMI_PHYPWRCMD_TXON = 2
  90 };
  91
  92 enum hdmi_core_hdmi_dvi {
  93         HDMI_DVI = 0,
  94         HDMI_HDMI = 1
  95 };
  96
  97 enum hdmi_packing_mode {
  98         HDMI_PACK_10b_RGB_YUV444 = 0,
  99         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 100         HDMI_PACK_20b_YUV422 = 2,
 101         HDMI_PACK_ALREADYPACKED = 7
 102 };
 103
 104 enum hdmi_stereo_channels {
 105         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 106         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 107         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 108         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 109         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 110 };
 111
 112 enum hdmi_audio_type {
 113         HDMI_AUDIO_TYPE_LPCM = 0,
 114         HDMI_AUDIO_TYPE_IEC = 1
 115 };
 116
 117 enum hdmi_audio_justify {
 118         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 119         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 120 };
 121
 122 enum hdmi_audio_sample_order {
 123         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 124         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 125 };
 126
 127 enum hdmi_audio_samples_perword {
 128         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 129         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 130 };
 131
 132 enum hdmi_audio_sample_size_omap {
 133         HDMI_AUDIO_SAMPLE_16BITS = 0,
 134         HDMI_AUDIO_SAMPLE_24BITS = 1
 135 };
 136
 137 enum hdmi_audio_transf_mode {
 138         HDMI_AUDIO_TRANSF_DMA = 0,
 139         HDMI_AUDIO_TRANSF_IRQ = 1
 140 };
 141
 142 enum hdmi_audio_blk_strt_end_sig {
 143         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 144         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 145 };
 146
 147 enum hdmi_core_audio_layout {
 148         HDMI_AUDIO_LAYOUT_2CH = 0,
 149         HDMI_AUDIO_LAYOUT_8CH = 1,
 150         HDMI_AUDIO_LAYOUT_6CH = 2
 151 };
 152
 153 enum hdmi_core_cts_mode {
 154         HDMI_AUDIO_CTS_MODE_HW = 0,
 155         HDMI_AUDIO_CTS_MODE_SW = 1
 156 };
 157
 158 enum hdmi_audio_mclk_mode {
 159         HDMI_AUDIO_MCLK_128FS = 0,
 160         HDMI_AUDIO_MCLK_256FS = 1,
 161         HDMI_AUDIO_MCLK_384FS = 2,
 162         HDMI_AUDIO_MCLK_512FS = 3,
 163         HDMI_AUDIO_MCLK_768FS = 4,
 164         HDMI_AUDIO_MCLK_1024FS = 5,
 165         HDMI_AUDIO_MCLK_1152FS = 6,
 166         HDMI_AUDIO_MCLK_192FS = 7
 167 };
 168
 169 struct hdmi_video_format {
 170         enum hdmi_packing_mode  packing_mode;
 171         u32                     y_res;  /* Line per panel */
 172         u32                     x_res;  /* pixel per line */
 173 };
 174
 175 struct hdmi_config {
 176         struct videomode vm;
 177         struct hdmi_avi_infoframe infoframe;
 178         enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
 179 };
 180
 181 struct hdmi_audio_format {
 182         enum hdmi_stereo_channels               stereo_channels;
 183         u8                                      active_chnnls_msk;
 184         enum hdmi_audio_type                    type;
 185         enum hdmi_audio_justify                 justification;
 186         enum hdmi_audio_sample_order            sample_order;
 187         enum hdmi_audio_samples_perword         samples_per_word;
 188         enum hdmi_audio_sample_size_omap        sample_size;
 189         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 190 };
 191
 192 struct hdmi_audio_dma {
 193         u8                              transfer_size;
 194         u8                              block_size;
 195         enum hdmi_audio_transf_mode     mode;
 196         u16                             fifo_threshold;
 197 };
 198
 199 struct hdmi_core_audio_i2s_config {
 200         u8 in_length_bits;
 201         u8 justification;
 202         u8 sck_edge_mode;
 203         u8 vbit;
 204         u8 direction;
 205         u8 shift;
 206         u8 active_sds;
 207 };
 208
 209 struct hdmi_core_audio_config {
 210         struct hdmi_core_audio_i2s_config       i2s_cfg;
 211         struct snd_aes_iec958                   *iec60958_cfg;
 212         bool                                    fs_override;
 213         u32                                     n;
 214         u32                                     cts;
 215         u32                                     aud_par_busclk;
 216         enum hdmi_core_audio_layout             layout;
 217         enum hdmi_core_cts_mode                 cts_mode;
 218         bool                                    use_mclk;
 219         enum hdmi_audio_mclk_mode               mclk_mode;
 220         bool                                    en_acr_pkt;
 221         bool                                    en_dsd_audio;
 222         bool                                    en_parallel_aud_input;
 223         bool                                    en_spdif;
 224 };
 225
 226 struct hdmi_wp_data {
 227         void __iomem *base;
 228         phys_addr_t phys_base;
 229         unsigned int version;
 230 };
 231
 232 struct hdmi_pll_data {
 233         struct dss_pll pll;
 234
 235         void __iomem *base;
 236
 237         struct platform_device *pdev;
 238         struct hdmi_wp_data *wp;
 239 };
 240
 241 struct hdmi_phy_features {
 242         bool bist_ctrl;
 243         bool ldo_voltage;
 244         unsigned long max_phy;
 245 };
 246
 247 struct hdmi_phy_data {
 248         void __iomem *base;
 249
 250         const struct hdmi_phy_features *features;
 251         u8 lane_function[4];
 252         u8 lane_polarity[4];
 253 };
 254
 255 struct hdmi_core_data {
 256         void __iomem *base;
 257         bool cts_swmode;
 258         bool audio_use_mclk;
 259
 260         struct hdmi_wp_data *wp;
 261         unsigned int core_pwr_cnt;
 262         struct cec_adapter *adap;
 263 };
 264
 265 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
 266                 u32 val)
 267 {
 268         __raw_writel(val, base_addr + idx);
 269 }
 270
 271 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
 272 {
 273         return __raw_readl(base_addr + idx);
 274 }
 275
 276 #define REG_FLD_MOD(base, idx, val, start, end) \
 277         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 278                                                         val, start, end))
 279 #define REG_GET(base, idx, start, end) \
 280         FLD_GET(hdmi_read_reg(base, idx), start, end)
 281
 282 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
 283                 const u32 idx, int b2, int b1, u32 val)
 284 {
 285         u32 t = 0, v;
 286         while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
 287                 if (t++ > 10000)
 288                         return v;
 289                 udelay(1);
 290         }
 291         return v;
 292 }
 293
 294 /* HDMI wrapper funcs */
 295 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
 296 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
 297 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
 298 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
 299 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
 300 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
 301 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
 302 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
 303 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
 304 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 305                 const struct hdmi_video_format *video_fmt);
 306 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 307                 const struct videomode *vm);
 308 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 309                 const struct videomode *vm);
 310 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 311                 struct videomode *vm, const struct hdmi_config *param);
 312 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
 313                  unsigned int version);
 314 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
 315
 316 /* HDMI PLL funcs */
 317 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
 318 int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
 319                   struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
 320 void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
 321
 322 /* HDMI PHY funcs */
 323 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
 324         unsigned long lfbitclk);
 325 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
 326 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy,
 327                   unsigned int version);
 328 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
 329
 330 /* HDMI common funcs */
 331 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
 332         struct hdmi_phy_data *phy);
 333
 334 /* Audio funcs */
 335 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
 336 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
 337 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
 338 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 339                 struct hdmi_audio_format *aud_fmt);
 340 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 341                 struct hdmi_audio_dma *aud_dma);
 342 static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
 343 {
 344         return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
 345 }
 346
 347 /* HDMI DRV data */
 348 struct omap_hdmi {
 349         struct mutex lock;
 350         struct platform_device *pdev;
 351         struct dss_device *dss;
 352
 353         struct dss_debugfs_entry *debugfs;
 354
 355         struct hdmi_wp_data     wp;
 356         struct hdmi_pll_data    pll;
 357         struct hdmi_phy_data    phy;
 358         struct hdmi_core_data   core;
 359
 360         struct hdmi_config cfg;
 361
 362         struct regulator *vdda_reg;
 363
 364         bool core_enabled;
 365
 366         struct omap_dss_device output;
 367
 368         struct platform_device *audio_pdev;
 369         void (*audio_abort_cb)(struct device *dev);
 370         int wp_idlemode;
 371
 372         bool audio_configured;
 373         struct omap_dss_audio audio_config;
 374
 375         /* This lock should be taken when booleans below are touched. */
 376         spinlock_t audio_playing_lock;
 377         bool audio_playing;
 378         bool display_enabled;
 379 };
 380
 381 #define dssdev_to_hdmi(dssdev) container_of(dssdev, struct omap_hdmi, output)
 382
 383 #endif