treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / panel / panel-raydium-rm68200.c
blobe8982948e0ea61c6536e3489c0d946d74a8aa40c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 */
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
15 #include <video/mipi_display.h>
17 #include <drm/drm_mipi_dsi.h>
18 #include <drm/drm_modes.h>
19 #include <drm/drm_panel.h>
20 #include <drm/drm_print.h>
22 /*** Manufacturer Command Set ***/
23 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
24 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
25 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
26 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
27 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
28 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
30 /* CMD2 P0 commands (Display Options and Power) */
31 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
32 #define MCS_SGOPCTR 0x16 /* Source Bias Current */
33 #define MCS_SDCTR 0x1A /* Source Output Delay Time */
34 #define MCS_INVCTR 0x1B /* Inversion Type */
35 #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
36 #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
37 #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
38 #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
39 #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
40 #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
41 #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
42 #define MCS_SETVGN 0x52 /* VG M/S N Control */
43 #define MCS_SETVGP 0x54 /* VG M/S P Control */
44 #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
46 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
47 #define GOA_VSTV1 0x00
48 #define GOA_VSTV2 0x07
49 #define GOA_VCLK1 0x0E
50 #define GOA_VCLK2 0x17
51 #define GOA_VCLK_OPT1 0x20
52 #define GOA_BICLK1 0x2A
53 #define GOA_BICLK2 0x37
54 #define GOA_BICLK3 0x44
55 #define GOA_BICLK4 0x4F
56 #define GOA_BICLK_OPT1 0x5B
57 #define GOA_BICLK_OPT2 0x60
58 #define MCS_GOA_GPO1 0x6D
59 #define MCS_GOA_GPO2 0x71
60 #define MCS_GOA_EQ 0x74
61 #define MCS_GOA_CLK_GALLON 0x7C
62 #define MCS_GOA_FS_SEL0 0x7E
63 #define MCS_GOA_FS_SEL1 0x87
64 #define MCS_GOA_FS_SEL2 0x91
65 #define MCS_GOA_FS_SEL3 0x9B
66 #define MCS_GOA_BS_SEL0 0xAC
67 #define MCS_GOA_BS_SEL1 0xB5
68 #define MCS_GOA_BS_SEL2 0xBF
69 #define MCS_GOA_BS_SEL3 0xC9
70 #define MCS_GOA_BS_SEL4 0xD3
72 /* CMD2 P3 commands (Gamma) */
73 #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
74 #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
76 struct rm68200 {
77 struct device *dev;
78 struct drm_panel panel;
79 struct gpio_desc *reset_gpio;
80 struct regulator *supply;
81 bool prepared;
82 bool enabled;
85 static const struct drm_display_mode default_mode = {
86 .clock = 52582,
87 .hdisplay = 720,
88 .hsync_start = 720 + 38,
89 .hsync_end = 720 + 38 + 8,
90 .htotal = 720 + 38 + 8 + 38,
91 .vdisplay = 1280,
92 .vsync_start = 1280 + 12,
93 .vsync_end = 1280 + 12 + 4,
94 .vtotal = 1280 + 12 + 4 + 12,
95 .vrefresh = 50,
96 .flags = 0,
97 .width_mm = 68,
98 .height_mm = 122,
101 static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
103 return container_of(panel, struct rm68200, panel);
106 static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
107 size_t len)
109 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
110 int err;
112 err = mipi_dsi_dcs_write_buffer(dsi, data, len);
113 if (err < 0)
114 DRM_ERROR_RATELIMITED("MIPI DSI DCS write buffer failed: %d\n",
115 err);
118 static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
120 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
121 int err;
123 err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
124 if (err < 0)
125 DRM_ERROR_RATELIMITED("MIPI DSI DCS write failed: %d\n", err);
128 #define dcs_write_seq(ctx, seq...) \
129 ({ \
130 static const u8 d[] = { seq }; \
132 rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
136 * This panel is not able to auto-increment all cmd addresses so for some of
137 * them, we need to send them one by one...
139 #define dcs_write_cmd_seq(ctx, cmd, seq...) \
140 ({ \
141 static const u8 d[] = { seq }; \
142 unsigned int i; \
144 for (i = 0; i < ARRAY_SIZE(d) ; i++) \
145 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
148 static void rm68200_init_sequence(struct rm68200 *ctx)
150 /* Enter CMD2 with page 0 */
151 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
152 dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
153 dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
154 dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
155 dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
156 dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
157 dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
158 dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
159 dcs_write_seq(ctx, MCS_INVCTR, 0x00);
160 dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
161 dcs_write_seq(ctx, MCS_SDCTR, 0x06);
162 dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
163 dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
164 dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
165 dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
167 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
168 dcs_write_seq(ctx, GOA_VSTV1, 0x05);
169 dcs_write_seq(ctx, 0x02, 0x0B);
170 dcs_write_seq(ctx, 0x03, 0x0F);
171 dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
172 dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
173 0x50);
174 dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
175 0x00, 0x85, 0x08);
176 dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
177 0x00, 0x85, 0x08);
178 dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179 0x00, 0x00, 0x00, 0x00);
180 dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
181 dcs_write_seq(ctx, 0x2D, 0x01);
182 dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
183 0x00);
184 dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
185 dcs_write_seq(ctx, 0x3D, 0x40);
186 dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
187 dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
188 0x00, 0x00, 0x00, 0x00, 0x00);
189 dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
190 0x00, 0x00);
191 dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
192 dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
193 dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
195 dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
196 dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
197 dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
198 0x00, 0x00);
199 dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
200 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
201 0x16, 0x12, 0x08, 0x3F);
202 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
203 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
204 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
205 0x05, 0x01, 0x3F, 0x3F, 0x0F);
206 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
207 0x3F);
208 dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
209 dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
210 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
211 0x15, 0x11, 0x0F, 0x3F);
212 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
213 0x0D, 0x09, 0x3F, 0x3F, 0x07);
214 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
215 0x02, 0x06, 0x3F, 0x3F, 0x08);
216 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
217 0x3F, 0x3F, 0x0E, 0x10, 0x14);
218 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
219 dcs_write_seq(ctx, 0xDC, 0x02);
220 dcs_write_seq(ctx, 0xDE, 0x12);
222 dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
223 dcs_write_seq(ctx, 0x01, 0x75);
225 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
226 dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
227 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
228 0x12, 0x0C, 0x00);
229 dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
230 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
231 0x12, 0x0C, 0x00);
233 /* Exit CMD2 */
234 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
237 static int rm68200_disable(struct drm_panel *panel)
239 struct rm68200 *ctx = panel_to_rm68200(panel);
241 if (!ctx->enabled)
242 return 0;
244 ctx->enabled = false;
246 return 0;
249 static int rm68200_unprepare(struct drm_panel *panel)
251 struct rm68200 *ctx = panel_to_rm68200(panel);
252 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
253 int ret;
255 if (!ctx->prepared)
256 return 0;
258 ret = mipi_dsi_dcs_set_display_off(dsi);
259 if (ret)
260 DRM_WARN("failed to set display off: %d\n", ret);
262 ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
263 if (ret)
264 DRM_WARN("failed to enter sleep mode: %d\n", ret);
266 msleep(120);
268 if (ctx->reset_gpio) {
269 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
270 msleep(20);
273 regulator_disable(ctx->supply);
275 ctx->prepared = false;
277 return 0;
280 static int rm68200_prepare(struct drm_panel *panel)
282 struct rm68200 *ctx = panel_to_rm68200(panel);
283 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
284 int ret;
286 if (ctx->prepared)
287 return 0;
289 ret = regulator_enable(ctx->supply);
290 if (ret < 0) {
291 DRM_ERROR("failed to enable supply: %d\n", ret);
292 return ret;
295 if (ctx->reset_gpio) {
296 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
297 msleep(20);
298 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
299 msleep(100);
302 rm68200_init_sequence(ctx);
304 ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
305 if (ret)
306 return ret;
308 msleep(125);
310 ret = mipi_dsi_dcs_set_display_on(dsi);
311 if (ret)
312 return ret;
314 msleep(20);
316 ctx->prepared = true;
318 return 0;
321 static int rm68200_enable(struct drm_panel *panel)
323 struct rm68200 *ctx = panel_to_rm68200(panel);
325 if (ctx->enabled)
326 return 0;
328 ctx->enabled = true;
330 return 0;
333 static int rm68200_get_modes(struct drm_panel *panel,
334 struct drm_connector *connector)
336 struct drm_display_mode *mode;
338 mode = drm_mode_duplicate(connector->dev, &default_mode);
339 if (!mode) {
340 DRM_ERROR("failed to add mode %ux%ux@%u\n",
341 default_mode.hdisplay, default_mode.vdisplay,
342 default_mode.vrefresh);
343 return -ENOMEM;
346 drm_mode_set_name(mode);
348 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
349 drm_mode_probed_add(connector, mode);
351 connector->display_info.width_mm = mode->width_mm;
352 connector->display_info.height_mm = mode->height_mm;
354 return 1;
357 static const struct drm_panel_funcs rm68200_drm_funcs = {
358 .disable = rm68200_disable,
359 .unprepare = rm68200_unprepare,
360 .prepare = rm68200_prepare,
361 .enable = rm68200_enable,
362 .get_modes = rm68200_get_modes,
365 static int rm68200_probe(struct mipi_dsi_device *dsi)
367 struct device *dev = &dsi->dev;
368 struct rm68200 *ctx;
369 int ret;
371 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
372 if (!ctx)
373 return -ENOMEM;
375 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
376 if (IS_ERR(ctx->reset_gpio)) {
377 ret = PTR_ERR(ctx->reset_gpio);
378 dev_err(dev, "cannot get reset GPIO: %d\n", ret);
379 return ret;
382 ctx->supply = devm_regulator_get(dev, "power");
383 if (IS_ERR(ctx->supply)) {
384 ret = PTR_ERR(ctx->supply);
385 if (ret != -EPROBE_DEFER)
386 dev_err(dev, "cannot get regulator: %d\n", ret);
387 return ret;
390 mipi_dsi_set_drvdata(dsi, ctx);
392 ctx->dev = dev;
394 dsi->lanes = 2;
395 dsi->format = MIPI_DSI_FMT_RGB888;
396 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
397 MIPI_DSI_MODE_LPM;
399 drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs,
400 DRM_MODE_CONNECTOR_DSI);
402 ret = drm_panel_of_backlight(&ctx->panel);
403 if (ret)
404 return ret;
406 drm_panel_add(&ctx->panel);
408 ret = mipi_dsi_attach(dsi);
409 if (ret < 0) {
410 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
411 drm_panel_remove(&ctx->panel);
412 return ret;
415 return 0;
418 static int rm68200_remove(struct mipi_dsi_device *dsi)
420 struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
422 mipi_dsi_detach(dsi);
423 drm_panel_remove(&ctx->panel);
425 return 0;
428 static const struct of_device_id raydium_rm68200_of_match[] = {
429 { .compatible = "raydium,rm68200" },
432 MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
434 static struct mipi_dsi_driver raydium_rm68200_driver = {
435 .probe = rm68200_probe,
436 .remove = rm68200_remove,
437 .driver = {
438 .name = "panel-raydium-rm68200",
439 .of_match_table = raydium_rm68200_of_match,
442 module_mipi_dsi_driver(raydium_rm68200_driver);
444 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
445 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
446 MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
447 MODULE_LICENSE("GPL v2");