drivers/gpu/drm/panel/panel-tpo-td028ttec1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Toppoly TD028TTEC1 Panel Driver
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated
   6  *
   7  * Based on the omapdrm-specific panel-tpo-td028ttec1 driver
   8  *
   9  * Copyright (C) 2008 Nokia Corporation
  10  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  11  *
  12  * Neo 1973 code (jbt6k74.c):
  13  * Copyright (C) 2006-2007 OpenMoko, Inc.
  14  * Author: Harald Welte <laforge@openmoko.org>
  15  *
  16  * Ported and adapted from Neo 1973 U-Boot by:
  17  * H. Nikolaus Schaller <hns@goldelico.com>
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include <drm/drm_connector.h>
  25 #include <drm/drm_modes.h>
  26 #include <drm/drm_panel.h>
  27
  28 #define JBT_COMMAND                     0x000
  29 #define JBT_DATA                        0x100
  30
  31 #define JBT_REG_SLEEP_IN                0x10
  32 #define JBT_REG_SLEEP_OUT               0x11
  33
  34 #define JBT_REG_DISPLAY_OFF             0x28
  35 #define JBT_REG_DISPLAY_ON              0x29
  36
  37 #define JBT_REG_RGB_FORMAT              0x3a
  38 #define JBT_REG_QUAD_RATE               0x3b
  39
  40 #define JBT_REG_POWER_ON_OFF            0xb0
  41 #define JBT_REG_BOOSTER_OP              0xb1
  42 #define JBT_REG_BOOSTER_MODE            0xb2
  43 #define JBT_REG_BOOSTER_FREQ            0xb3
  44 #define JBT_REG_OPAMP_SYSCLK            0xb4
  45 #define JBT_REG_VSC_VOLTAGE             0xb5
  46 #define JBT_REG_VCOM_VOLTAGE            0xb6
  47 #define JBT_REG_EXT_DISPL               0xb7
  48 #define JBT_REG_OUTPUT_CONTROL          0xb8
  49 #define JBT_REG_DCCLK_DCEV              0xb9
  50 #define JBT_REG_DISPLAY_MODE1           0xba
  51 #define JBT_REG_DISPLAY_MODE2           0xbb
  52 #define JBT_REG_DISPLAY_MODE            0xbc
  53 #define JBT_REG_ASW_SLEW                0xbd
  54 #define JBT_REG_DUMMY_DISPLAY           0xbe
  55 #define JBT_REG_DRIVE_SYSTEM            0xbf
  56
  57 #define JBT_REG_SLEEP_OUT_FR_A          0xc0
  58 #define JBT_REG_SLEEP_OUT_FR_B          0xc1
  59 #define JBT_REG_SLEEP_OUT_FR_C          0xc2
  60 #define JBT_REG_SLEEP_IN_LCCNT_D        0xc3
  61 #define JBT_REG_SLEEP_IN_LCCNT_E        0xc4
  62 #define JBT_REG_SLEEP_IN_LCCNT_F        0xc5
  63 #define JBT_REG_SLEEP_IN_LCCNT_G        0xc6
  64
  65 #define JBT_REG_GAMMA1_FINE_1           0xc7
  66 #define JBT_REG_GAMMA1_FINE_2           0xc8
  67 #define JBT_REG_GAMMA1_INCLINATION      0xc9
  68 #define JBT_REG_GAMMA1_BLUE_OFFSET      0xca
  69
  70 #define JBT_REG_BLANK_CONTROL           0xcf
  71 #define JBT_REG_BLANK_TH_TV             0xd0
  72 #define JBT_REG_CKV_ON_OFF              0xd1
  73 #define JBT_REG_CKV_1_2                 0xd2
  74 #define JBT_REG_OEV_TIMING              0xd3
  75 #define JBT_REG_ASW_TIMING_1            0xd4
  76 #define JBT_REG_ASW_TIMING_2            0xd5
  77
  78 #define JBT_REG_HCLOCK_VGA              0xec
  79 #define JBT_REG_HCLOCK_QVGA             0xed
  80
  81 struct td028ttec1_panel {
  82         struct drm_panel panel;
  83
  84         struct spi_device *spi;
  85 };
  86
  87 #define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
  88
  89 static int jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
  90 {
  91         struct spi_device *spi = lcd->spi;
  92         u16 tx_buf = JBT_COMMAND | reg;
  93         int ret;
  94
  95         if (err && *err)
  96                 return *err;
  97
  98         ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
  99         if (ret < 0) {
 100                 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
 101                 if (err)
 102                         *err = ret;
 103         }
 104
 105         return ret;
 106 }
 107
 108 static int jbt_reg_write_1(struct td028ttec1_panel *lcd,
 109                            u8 reg, u8 data, int *err)
 110 {
 111         struct spi_device *spi = lcd->spi;
 112         u16 tx_buf[2];
 113         int ret;
 114
 115         if (err && *err)
 116                 return *err;
 117
 118         tx_buf[0] = JBT_COMMAND | reg;
 119         tx_buf[1] = JBT_DATA | data;
 120
 121         ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
 122         if (ret < 0) {
 123                 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
 124                 if (err)
 125                         *err = ret;
 126         }
 127
 128         return ret;
 129 }
 130
 131 static int jbt_reg_write_2(struct td028ttec1_panel *lcd,
 132                            u8 reg, u16 data, int *err)
 133 {
 134         struct spi_device *spi = lcd->spi;
 135         u16 tx_buf[3];
 136         int ret;
 137
 138         if (err && *err)
 139                 return *err;
 140
 141         tx_buf[0] = JBT_COMMAND | reg;
 142         tx_buf[1] = JBT_DATA | (data >> 8);
 143         tx_buf[2] = JBT_DATA | (data & 0xff);
 144
 145         ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
 146         if (ret < 0) {
 147                 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
 148                 if (err)
 149                         *err = ret;
 150         }
 151
 152         return ret;
 153 }
 154
 155 static int td028ttec1_prepare(struct drm_panel *panel)
 156 {
 157         struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
 158         unsigned int i;
 159         int ret = 0;
 160
 161         /* Three times command zero */
 162         for (i = 0; i < 3; ++i) {
 163                 jbt_ret_write_0(lcd, 0x00, &ret);
 164                 usleep_range(1000, 2000);
 165         }
 166
 167         /* deep standby out */
 168         jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
 169
 170         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 171         jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
 172
 173         /* Quad mode off */
 174         jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
 175
 176         /* AVDD on, XVDD on */
 177         jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
 178
 179         /* Output control */
 180         jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
 181
 182         /* Sleep mode off */
 183         jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
 184
 185         /* at this point we have like 50% grey */
 186
 187         /* initialize register set */
 188         jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
 189         jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
 190         jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
 191         jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
 192         jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
 193         jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
 194         jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
 195         jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
 196         jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
 197         jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
 198         jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
 199         jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
 200         jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
 201         /*
 202          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 203          * to avoid red / blue flicker
 204          */
 205         jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
 206         jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
 207
 208         jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
 209         jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
 210         jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
 211         jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
 212         jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
 213         jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
 214         jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
 215
 216         jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
 217         jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
 218         jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
 219         jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
 220
 221         jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
 222         jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
 223         jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
 224
 225         jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
 226         jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
 227
 228         jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
 229         jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
 230         jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
 231
 232         return ret;
 233 }
 234
 235 static int td028ttec1_enable(struct drm_panel *panel)
 236 {
 237         struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
 238         int ret;
 239
 240         ret = jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
 241         if (ret)
 242                 return ret;
 243
 244         return 0;
 245 }
 246
 247 static int td028ttec1_disable(struct drm_panel *panel)
 248 {
 249         struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
 250
 251         jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
 252
 253         return 0;
 254 }
 255
 256 static int td028ttec1_unprepare(struct drm_panel *panel)
 257 {
 258         struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
 259
 260         jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
 261         jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
 262         jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
 263
 264         return 0;
 265 }
 266
 267 static const struct drm_display_mode td028ttec1_mode = {
 268         .clock = 22153,
 269         .hdisplay = 480,
 270         .hsync_start = 480 + 24,
 271         .hsync_end = 480 + 24 + 8,
 272         .htotal = 480 + 24 + 8 + 8,
 273         .vdisplay = 640,
 274         .vsync_start = 640 + 4,
 275         .vsync_end = 640 + 4 + 2,
 276         .vtotal = 640 + 4 + 2 + 2,
 277         .vrefresh = 66,
 278         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 279         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 280         .width_mm = 43,
 281         .height_mm = 58,
 282 };
 283
 284 static int td028ttec1_get_modes(struct drm_panel *panel,
 285                                 struct drm_connector *connector)
 286 {
 287         struct drm_display_mode *mode;
 288
 289         mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
 290         if (!mode)
 291                 return -ENOMEM;
 292
 293         drm_mode_set_name(mode);
 294         drm_mode_probed_add(connector, mode);
 295
 296         connector->display_info.width_mm = td028ttec1_mode.width_mm;
 297         connector->display_info.height_mm = td028ttec1_mode.height_mm;
 298         /*
 299          * FIXME: According to the datasheet sync signals are sampled on the
 300          * rising edge of the clock, but the code running on the OpenMoko Neo
 301          * FreeRunner and Neo 1973 indicates sampling on the falling edge. This
 302          * should be tested on a real device.
 303          */
 304         connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
 305                                           | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
 306                                           | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
 307
 308         return 1;
 309 }
 310
 311 static const struct drm_panel_funcs td028ttec1_funcs = {
 312         .prepare = td028ttec1_prepare,
 313         .enable = td028ttec1_enable,
 314         .disable = td028ttec1_disable,
 315         .unprepare = td028ttec1_unprepare,
 316         .get_modes = td028ttec1_get_modes,
 317 };
 318
 319 static int td028ttec1_probe(struct spi_device *spi)
 320 {
 321         struct td028ttec1_panel *lcd;
 322         int ret;
 323
 324         lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
 325         if (!lcd)
 326                 return -ENOMEM;
 327
 328         spi_set_drvdata(spi, lcd);
 329         lcd->spi = spi;
 330
 331         spi->mode = SPI_MODE_3;
 332         spi->bits_per_word = 9;
 333
 334         ret = spi_setup(spi);
 335         if (ret < 0) {
 336                 dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
 337                 return ret;
 338         }
 339
 340         drm_panel_init(&lcd->panel, &lcd->spi->dev, &td028ttec1_funcs,
 341                        DRM_MODE_CONNECTOR_DPI);
 342
 343         ret = drm_panel_of_backlight(&lcd->panel);
 344         if (ret)
 345                 return ret;
 346
 347         return drm_panel_add(&lcd->panel);
 348 }
 349
 350 static int td028ttec1_remove(struct spi_device *spi)
 351 {
 352         struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
 353
 354         drm_panel_remove(&lcd->panel);
 355         drm_panel_disable(&lcd->panel);
 356         drm_panel_unprepare(&lcd->panel);
 357
 358         return 0;
 359 }
 360
 361 static const struct of_device_id td028ttec1_of_match[] = {
 362         { .compatible = "tpo,td028ttec1", },
 363         /* DT backward compatibility. */
 364         { .compatible = "toppoly,td028ttec1", },
 365         { /* sentinel */ },
 366 };
 367
 368 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 369
 370 static const struct spi_device_id td028ttec1_ids[] = {
 371         { "td028ttec1", 0 },
 372         { /* sentinel */ }
 373 };
 374
 375 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
 376
 377 static struct spi_driver td028ttec1_driver = {
 378         .probe          = td028ttec1_probe,
 379         .remove         = td028ttec1_remove,
 380         .id_table       = td028ttec1_ids,
 381         .driver         = {
 382                 .name   = "panel-tpo-td028ttec1",
 383                 .of_match_table = td028ttec1_of_match,
 384         },
 385 };
 386
 387 module_spi_driver(td028ttec1_driver);
 388
 389 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 390 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 391 MODULE_LICENSE("GPL");