drivers/gpu/drm/pl111/pl111_drm.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *
   4  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
   5  *
   6  * Parts of this file were based on sources as follows:
   7  *
   8  * Copyright (c) 2006-2008 Intel Corporation
   9  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  10  * Copyright (C) 2011 Texas Instruments
  11  */
  12
  13 #ifndef _PL111_DRM_H_
  14 #define _PL111_DRM_H_
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/interrupt.h>
  18
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_connector.h>
  21 #include <drm/drm_encoder.h>
  22 #include <drm/drm_gem.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_simple_kms_helper.h>
  25
  26 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
  27
  28 struct drm_minor;
  29
  30 /**
  31  * struct pl111_variant_data - encodes IP differences
  32  * @name: the name of this variant
  33  * @is_pl110: this is the early PL110 variant
  34  * @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant
  35  * @external_bgr: this is the Versatile Pl110 variant with external
  36  *      BGR/RGB routing
  37  * @broken_clockdivider: the clock divider is broken and we need to
  38  *      use the supplied clock directly
  39  * @broken_vblank: the vblank IRQ is broken on this variant
  40  * @st_bitmux_control: this variant is using the ST Micro bitmux
  41  *      extensions to the control register
  42  * @formats: array of supported pixel formats on this variant
  43  * @nformats: the length of the array of supported pixel formats
  44  * @fb_bpp: desired bits per pixel on the default framebuffer
  45  */
  46 struct pl111_variant_data {
  47         const char *name;
  48         bool is_pl110;
  49         bool is_lcdc;
  50         bool external_bgr;
  51         bool broken_clockdivider;
  52         bool broken_vblank;
  53         bool st_bitmux_control;
  54         const u32 *formats;
  55         unsigned int nformats;
  56         unsigned int fb_bpp;
  57 };
  58
  59 struct pl111_drm_dev_private {
  60         struct drm_device *drm;
  61
  62         struct drm_connector *connector;
  63         struct drm_panel *panel;
  64         struct drm_bridge *bridge;
  65         struct drm_simple_display_pipe pipe;
  66
  67         void *regs;
  68         u32 memory_bw;
  69         u32 ienb;
  70         u32 ctrl;
  71         /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
  72         struct clk *clk;
  73         /* pl111's internal clock divider. */
  74         struct clk_hw clk_div;
  75         /* Lock to sync access to CLCD_TIM2 between the common clock
  76          * subsystem and pl111_display_enable().
  77          */
  78         spinlock_t tim2_lock;
  79         const struct pl111_variant_data *variant;
  80         void (*variant_display_enable) (struct drm_device *drm, u32 format);
  81         void (*variant_display_disable) (struct drm_device *drm);
  82         bool use_device_memory;
  83 };
  84
  85 int pl111_display_init(struct drm_device *dev);
  86 irqreturn_t pl111_irq(int irq, void *data);
  87 int pl111_debugfs_init(struct drm_minor *minor);
  88
  89 #endif /* _PL111_DRM_H_ */